JPH0248885U - - Google Patents
Info
- Publication number
- JPH0248885U JPH0248885U JP12790288U JP12790288U JPH0248885U JP H0248885 U JPH0248885 U JP H0248885U JP 12790288 U JP12790288 U JP 12790288U JP 12790288 U JP12790288 U JP 12790288U JP H0248885 U JPH0248885 U JP H0248885U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- output
- overflow warning
- pulse doppler
- warning signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 2
- 230000001186 cumulative effect Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 3
- 238000009825 accumulation Methods 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
Landscapes
- Radar Systems Or Details Thereof (AREA)
Description
第１図はこの考案によるレーダ信号処理装置の
全体構成図、第２図は従来のレーダ信号処理装置
の全体構成図、第３図ａ〜ｄはこの考案によるレ
ーダ信号処理装置にて示される波形及びカウント
数を示す図、第４図ａ，ｂは従来のレーダ信号処
理装置にて示される波形及びカウント数を示す図
である。
図において、１はパルスドツプラフイルタ、２
はスレツシヨルド発生回路、３は可変係数設定回
路、４は比較回路、５は累積カウンタ回路、６は
オーバーフロー警告信号発生回路、７はオーバー
フロー警告ランプ、８は目標数検出回路、９は固
定係数設定回路、１０はスレツシヨルドレベル信
号、１１はパルスドツプラフイルタ１出力、１２
は最初の目標、１３は２番目の目標、１４は３番
目の目標、１５はｍ番目の目標、１６はｍ＋１番
目の目標、１７はｍ＋２番目の目標、１８は最終
目標である。なお、各図中同一符号は同一または
相当部分を示す。
FIG. 1 is an overall configuration diagram of a radar signal processing device according to this invention, FIG. 2 is an overall configuration diagram of a conventional radar signal processing device, and FIGS. 3 a to 3 d are waveforms shown in a radar signal processing device according to this invention. Figures 4a and 4b are diagrams showing waveforms and counts shown in a conventional radar signal processing device. In the figure, 1 is a pulse Doppler filter, 2
3 is a threshold generation circuit, 3 is a variable coefficient setting circuit, 4 is a comparison circuit, 5 is an accumulation counter circuit, 6 is an overflow warning signal generation circuit, 7 is an overflow warning lamp, 8 is a target number detection circuit, 9 is a fixed coefficient setting circuit , 10 is a threshold level signal, 11 is a pulse Doppler filter 1 output, 12
is the first target, 13 is the second target, 14 is the third target, 15 is the m-th target, 16 is the m+1-th target, 17 is the m+2-th target, and 18 is the final target. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
で構成されたパルスドツプラフイルタと、前記パ
ルスドツプラフイルタ出力を入力とし、不要信号
のため、距離によつてノイズレスポンスが変化し
ても誤警報確率が一定となるようなスレツシヨル
ド値を得るためのスレツシヨルド発生回路と、係
数を自由に設定できる可変係数設定回路と、前記
スレツシヨルド発生回路出力と前記可変係数設定
回路出力を乗算したもの及び、前記パルスドツプ
ラフイルタ出力を入力とし、両者を比較するため
の比較回路と、前記比較回路出力を入力とし、前
記パルスドツプラフイルタ出力が前記スレツシヨ
ルド発生回路と前記可変係数設定回路出力を乗算
したものを越えた場合、それを目標とみなし、そ
の数をカウントするための累積カウンタ回路に、
前記累積カウンタ回路がオーバーフローを起こし
た場合、オーバーフロー警告信号を発生するため
のオーバーフロー警造信号発生回路と、前記オー
バーフロー警告信号発生回路がオーバーフロー警
告信号を出力した場合、点灯するためのオーバー
フロー警告ランプを加えた、不要信号から分離し
た目標数を検出するための目標数検出回路とを備
えたことを特徴とするレーダ信号処理装置。 A pulse Doppler filter composed of a digital filter or a fast Fourier transformer and the output of the pulse Doppler filter are used as inputs, and since the pulse Doppler filter output is an unnecessary signal, the false alarm probability remains constant even if the noise response changes depending on the distance. a threshold generation circuit for obtaining a threshold value, a variable coefficient setting circuit that can freely set coefficients, a product obtained by multiplying the output of the threshold generation circuit by the output of the variable coefficient setting circuit, and an output of the pulse Doppler filter. a comparator circuit for comparing the two, and an output of the comparator circuit; A cumulative counter circuit is used to count the number of targets.
an overflow warning signal generating circuit for generating an overflow warning signal when the cumulative counter circuit overflows; and an overflow warning lamp for lighting when the overflow warning signal generating circuit outputs an overflow warning signal. A radar signal processing device characterized by further comprising: a target number detection circuit for detecting a target number separated from unnecessary signals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12790288U JPH0248885U (en) | 1988-09-29 | 1988-09-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12790288U JPH0248885U (en) | 1988-09-29 | 1988-09-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0248885U true JPH0248885U (en) | 1990-04-04 |
Family
ID=31380750
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12790288U Pending JPH0248885U (en) | 1988-09-29 | 1988-09-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0248885U (en) |
-
1988
- 1988-09-29 JP JP12790288U patent/JPH0248885U/ja active Pending
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