JPH0249049B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to an analog amplifier circuit using a MOS transistor as a source follower.

Conventional technology and problems In the source follower circuit, when the amplifying element used is an n-channel MOS transistor, its drain is connected to the power supply, the source is connected to the ground via a load resistor, the input voltage is applied to the gate, and the source and load resistor are connected. Take out the output voltage from the contact. Although the source follower has a gain of 1 or less, it is often used for impedance conversion. One practical example is the output section of a CCD (charge coupled device), an outline of which is shown in Figure 1.

In this figure, Tr ₁ to _{Tr 7} are n-channel MOS transistors, and Tr ₄ to _{Tr 7} constitute a two-stage source follower. That is, the drains of Tr ₄ and Tr ₆ are connected to the voltage V _DD , and the sources of the transistors Tr ₅ and Tr 6 are connected to the load resistance.
It is connected to the drain of Tr ₇ , and the sources of Tr ₅ and Tr ₇ are connected to the power supply (ground) V _SS . Tr ₁ , Tr ₂
is a load bias circuit, and transistors Tr ₅ ,
Supply gate voltage to Tr ₇ to set these as load resistances of appropriate values. If the source follower is connected in two stages, the gain will further decrease, but two stages are often used in CCDs to accommodate load capacitance.
D, indicated by the diode mark, is the output part of the CCD (charge-coupled device), which connects the source of the transistor,
It consists of a diffusion region similar to the drain. The output D is connected to the power supply V _DD via the transistor Tr ₃ .
This transistor Tr ₃ C is a depletion type and is normally cut off. When the reset clock φ _R is input, it becomes cut-on (on) and directly connects the output section D to the power supply V _DD (equivalently), and Reset the output section.

b in Fig. 2 shows the waveform of the reset lock _φR ,
Figure a shows the waveform of the output voltage Vout. When the reset clock φ _R is input to the transistor Tr ₃ in Fig. 1,
Tr ₃ is turned on and fixed to the source V _DD of the output section D of the CCD, and is divided according to the on-resistance values of transistors Tr ₄ , Tr ₅ , TR ₆ , and _{TR 7} to obtain an output voltage Vout. When the reset clock _φR is turned off, the potential of the output portion D drops slightly due to the gate-source capacitance of the transistor _Tr3 , and the output voltage Vout also drops slightly. This portion Q becomes the DC (direct current) reference belt. Next, when the charges (electrons) of the CCD are transferred and enter the output section D, the potential of the output section decreases.
The potential change of this portion D is determined by the inflow charge,
Therefore, QR becomes the signal voltage Vsg. To read the signal voltage, the potential of the portion R is read at the middle of each portion, and the difference from the reference level Q is determined to obtain an output.

When a CCD is used in a portable television camera or the like, the power source is a dry battery or the like, and the power supply voltage is likely to fluctuate when power is supplied after boosting the voltage from the dry battery. The output voltage Vout where the power supply voltage V _DD fluctuates is the second
As shown in Figure c, the whole changes as the power supply voltage fluctuates. In this case, since the partial Q and R levels also fluctuate, the output signal obtained by sampling them includes power supply voltage fluctuations and becomes unstable.

OBJECTS OF THE INVENTION The present invention aims to improve these points and generate a stable output voltage that is not affected by power supply voltage fluctuations.

Structure of the Invention The present invention includes a MOS transistor circuit connected to a source follower, and a MOS transistor circuit that serves as a load resistance of the circuit.
In a MOS analog amplifier circuit equipped with a load bias circuit that applies a bias voltage obtained by dividing the power supply voltage to the gate of the transistor with a pair of MOS transistors whose gates are connected to their drains,
One of the pair of MOS transistors constituting the load bias circuit is made to be a depletion type and operated in a non-saturation region, so that the output voltage of the source follower fluctuates when the power supply voltage fluctuates so that the output voltage of the source follower does not fluctuate due to fluctuations in the power supply voltage. The present invention is characterized in that it outputs a voltage of 100%, and this will be explained next with reference to embodiments.

Embodiments of the Invention In the present invention, the transistor Tr ₂ of the load bias circuit shown in FIG. 1 is of a depletion type, and the operating point is selected to be in the non-saturation region (triode region). In the conventional circuit, this transistor Tr ₂ is of an enhancement type, and its operating point is in the saturation region. The transistor Tr ₁ of the load bias circuit is of an enhancement type in both the circuit of the present invention and the conventional circuit, and the gate is connected to the drain to operate in the saturation region.

The transistors Tr ₁ and Tr ₂ divide the power supply voltage V _DD , output the divided voltage from the connection point, and supply the divided voltage Vb to the gates of the transistors Tr ₂ , Tr ₅ , and Tr ₇ . As in the conventional circuit, the transistor Tr ₁ ,
When both Tr ₂ operate in the saturation region, the voltage Vb is not affected much by the power supply voltage V _DD and remains substantially constant.
Therefore, when the power supply voltage V _DD increases, for example, the output voltage Vout of the source follower stage also increases.
On the other hand, in the circuit of the present invention, since the transistor Tr ₂ is in the unsaturated triode region, when the power supply voltage V _DD increases, the voltage Vb at the output terminal A increases, and as a result, the gate voltage of the transistors Tr ₅ and Tr ₇ increases. increases, increasing the conductivity, i.e., lower resistance, and the output voltage
Vout no longer rises as the power supply voltage _VDD rises. It is desirable that the voltage Vb changes to sufficiently suppress changes in Vout due to changes in V _DD , and this depends on the size of transistors Tr ₁ and Tr ₂ such as W/L (gate width/gate length), and the operation of Tr ₂ . This can be achieved by selecting the area appropriately. transistor
Depletion of Tr ₂ is performed by implanting an impurity such as P (phosphorus) into the channel region of the transistor.

Effects of the Invention As explained above, in the present invention, the gate voltage of the MOS transistor serving as the load resistance of the source follower is adjusted by the bias voltage circuit so as to cancel out the output voltage change due to the change in the power supply voltage. A stable output voltage can be obtained even when the output voltage is likely to fluctuate.
Since it is simple in that one is of depletion type and operates in a non-saturation region, there is an advantage that the circuit does not become complicated.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a waveform diagram illustrating the operation. In the drawing, Tr ₆ and Tr ₇ are connected to the source follower.
MOS transistor circuit, Tr ₇ becomes load resistance
The MOS transistors Tr ₁ and Tr ₂ are transistors of a load bias circuit that divides the power supply voltage, and Tr ₂ is one of the transistors.

Claims (1)

[Claims] 1. A bias voltage obtained by dividing the power supply voltage between a MOS transistor circuit connected to a source follower, a pair of MOS transistors whose gates are connected to their drains, and a pair of MOS transistors whose gates are connected to their drains. In a MOS analog amplifier circuit equipped with a load bias circuit that adds A MOS analog amplifier circuit configured to output a voltage that fluctuates so that the output voltage of the circuit does not fluctuate due to fluctuations in the power supply voltage.