JPH0249064B2 - DOKIJOTAIHANTEISOCHI - Google Patents

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to a synchronization state determination device used in a symbol synchronizer equipped with an integrator, and in particular to a method for reliably determining the synchronization state in a low S/N state. Regarding.

(Prior art) Conventional symbol synchronizers using integrators are usually DTTL (DATA
TRANSITION TRACKING LOOP) and early rate gate type symbol synchronizers have been used. Conventionally, in these methods, the synchronization state has been determined by inputting a data integral signal into a computer as a first method and calculating the S/N by dispersion.

On the other hand, as a simple second method, a method is known in which the data is filtered and then the determination is made based on the phase relationship between the zero-cross timing and the reproduced clock signal.

(Problem to be solved by the invention) In these methods, the determination threshold
A drawback was that it was difficult to generate a threshold effect when E _B /No was low.

Furthermore, in the above method, the first method requires a computer, which increases the scale of the device, and the second method requires the addition of a band-limiting filter, which increases the number of parts. There was a drawback.

The present invention aims to solve the drawbacks of the above two methods, and determines the synchronization state using hardware.

The purpose of the present invention is to eliminate the above-mentioned drawbacks by integrating 1-bit data using two integrators at the front and rear stages, and digitally processing these to obtain data values and synchronization judgment results. It is an object of the present invention to provide a synchronization state determination device configured to always give correct synchronization state determination results without being influenced.

(Means for Solving Problems) A synchronization state determination device according to the present invention includes a pair of data integrators, a pair of A/D converters, an addition circuit, an absolute value circuit, an accumulator, and a determination comparison. The device is configured to include means.

The pair of data integrators are used to independently integrate the first half and the second half of a unit symbol while maintaining a phase difference of 1/2 symbol.

The pair of A/D converters are for A/D converting the outputs of the pair of data integrators, respectively.

The adder circuit is for adding the outputs of the pair of A/D converters.

The absolute value circuit is for taking the absolute value of the output of the adder circuit.

The accumulator is for accumulating the output of the absolute value circuit.

The determination comparison means is for determining synchronous lock based on whether the output of the accumulator exceeds the determination threshold value.

(Example) Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a synchronization state determining device according to the present invention. In Figure 1, 1 and 3 are data integrators, 2 and 4 are A/D converters, 5 is an addition circuit, 6 is an absolute value circuit, 7 is an accumulator, 8 is a comparator, and 9 is a decision threshold. A hold circuit 10 is a timing generation circuit.

FIG. 2 is a diagram showing waveforms of each part of the synchronization state determination device. In FIG. 2, a is the input signal waveform on the signal line 101, b is the integral waveform on the signal line 102, c is the addition result on the signal line 103, and d is the absolute value on the signal line 104. , e is the timing waveform on the signal line 105, and f is the cumulative waveform on the signal line 106.

In FIG. 1, a pair of data integrators 1, 3
is prepared, and the first half and second half of each symbol are integrated. The output of data integrator 3 lags behind the output of data integrator 1 by 1/2 symbol.
Integration is performed in synchronization with the timing pulse output from the timing generation circuit 10, and it goes without saying that a normal output cannot be obtained unless the input signal is synchronized with the timing pulse. The outputs of the respective data integrators 1 and 3 are added by an adder 5 via a pair of A/D converters 2 and 4. The adder 5 outputs data every half symbol, and the 2Nth data is the complete integration of the unit symbol, and the 2N+1st data is the integration of the middle of the unit symbol. When the absolute values of these values are determined by the absolute value circuit 6,
When synchronization is normal, the absolute value of the 2Nth data takes a constant positive value, and when there is a transition, the absolute value of the 2N+1st data takes a value close to zero. On the other hand, when there is no transition, the absolute value of the 2N+1st data is a constant positive value. These values are accumulated by the accumulator 7. If positive integration is performed on the 2Nth data and negative integration is performed on the 2N+1st data, a value equal to zero will be obtained at lock-off after a certain number of bits have been integrated, and a positive value will be obtained at lock-on. Therefore, by comparing the above value with a reference threshold value set in the determination threshold circuit 9 by the comparator 8, the synchronous lock is determined.

If the synchronization status determination device is not locked,
Since the 2N-th and 2N+1-th data have almost the same value, the cumulative value becomes almost zero. By performing these calculations digitally, the threshold for determining synchronous lock does not change even if the symbol rate changes.

(Effects of the Invention) As explained above, in the present invention, 1-bit data is integrated by two-stage integrators at the front and rear stages, and these are digitally processed to obtain data values and synchronization determination results. This has the advantage that synchronization can be determined even in a low S/N state with a relatively simple circuit configuration.

Further, by digitizing the circuit configuration described above, there is an effect that the determination threshold E _B /N _O can be kept constant even if the symbol rate changes.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a synchronous state determining device according to the present invention, and FIG. 2 is a diagram showing waveforms of various parts of the synchronous state determining device. 1, 3... Integrator, 2, 4... A/D converter, 5... Adder, 6... Absolute value circuit, 7... Accumulator, 8... Comparator, 9... Judgment threshold Hold circuit, 10...timing generation circuit.

Claims (1)

[Claims] 1 A pair of data integrators for independently integrating the first and second half of a unit symbol while maintaining a phase difference of 1/2 symbol, and a pair of data integrators for A/D converting the outputs of the pair of data integrators, respectively. a pair of A/D converters, an adder circuit for adding the outputs of the pair of A/D converters, an absolute value circuit for taking an absolute value of the output of the adder circuit, and a It is characterized by comprising an accumulator for accumulating outputs, and a judgment comparison means for judging synchronization lock based on whether the output of the accumulator exceeds a judgment threshold value. A synchronization state determination device.