JPH0249300A - Microcomputer incorporated with eeprom - Google Patents

Abstract

PURPOSE:To always hold information data stored in an initial stage by preventing the chronological change of the information data stored in the initial stage and executing rewriting processing for the information data before the data retention of the information data occurs. CONSTITUTION:The information data are written to an exclusive-use memory cell 131, the storage performance of which is previously deteriorated compared with that of an EEPROM12, in the same manner as that in writing the information data to the EEPROM12. Further, the information data in the exclusive-use memory cell 131 are periodically read through a data processor 11 by a program or the treatment of software, an interruption to a data processing part 111 is requested before abnormality such as the data retention occurs, and the rewriting processing for the information data stored in the initial state can be executed for all the memory cells in the EEPROM12. Thus, the information data, which are stored in the initial stage and have high reliability, can be always held.

Description

[Detailed Description of the Invention] [Summary] Microcomputer with built-in EEPROM, especially EEPROM
P ROM (Electrically Eraser
ble Program-able Read 0nl
Regarding the retention of the information data written in the EEPROM, the information data initially stored in the EEPROM is prevented from changing over time, and the information data is rewritten before data retention occurs, so that the information data is always maintained. The purpose is to hold the information data stored initially, and the data processing section is connected to the data processing section through a control line consisting of an address signal, a data signal, a read/write signal, and an interrupt request signal. and an EEPROM in which written data can be electrically erased or written, and a storage content detection means for preventing the storage content of the EEPROM from disappearing, and when the storage content of the storage content detection unit is deteriorated. , including rewriting the storage contents of all EEPROMs.

[Industrial application field]

The present invention relates to a microcomputer with a built-in EEPROM, and more specifically, the present invention relates to a microcomputer with a built-in EEPROM.
(Electrically! Erasable
ProgrammableRead 0nly Memo
This relates to the retention of the data contents written in ry).

In recent years, microcomputers with built-in EPROMs and EEPROMs (erasable read-only storage devices) have become ICs.
It is often incorporated into cards, etc.

However, depending on the usage mode of the user, there are cases where the writing process is not performed for a long period of time after the -degree data is written into the memory cell, and in EEPROMs and EPROMs, data retention characteristics greatly affect reliability improvement.

Therefore, there is a demand for a microcomputer with a built-in EEPROM that has a function to prevent data retention (inversion).

[Conventional technology]

FIG. 7 is a diagram illustrating a conventional microcomputer with built-in EEPROM.

Figure (a) is a simple configuration diagram of a microcomputer with a built-in EEPROM, and 1 is an EEPROM built-in microcomputer.
A microcomputer with a built-in EPROM, 2 a CPU (central processing unit) that processes given data, and 3 an EEPROM in which written data can be electrically erased or programmed. Also, 4 is an address signal, 5 is a data signal, 6 is a read/write signal, and 7 is an E
During the data writing process by EPROM3, CPU2
An interrupt request signal 8 for requesting an interrupt is an external data input line for inputting user information data, and 9 is a control line.

When such a configuration is used, the information data is stored in the EEPROM.
When writing to EEPROM 3, the CPU
A read/write signal 6 is transmitted to the EEPROM 3, and an address signal 4 and a data signal 5 are input to the EEPROM 3. As a result, in the EEPROM memory cell shown in FIG.
Transistor Ql! Charge is accumulated in the FC (floating gate), and data is stored at a designated address.

Once information data is written to the 0M memory cell,
Write processing may not be performed for a long period of time (for example, several years).

Therefore, for some reason, charges accumulated in the floating gate of transistor Q+3 over time may cause a capacitive wave phenomenon, which may invert the channel. This causes problems such as data retention (data corruption) and erroneous reading, resulting in poor data retention characteristics.

The present invention was created in view of the problems of the conventional example, and prevents the information data initially stored in the EPROM from changing over time, and rewrites the information data before data rewriting occurs. EEPR that allows processing and always retaining initially stored information data
The purpose is to provide a microcomputer with built-in OM.

[YA problem that the invention attempts to solve]

Therefore, due to user a etc., EBPRCtIl
! ! [Means for Solving the Problems] The microcomputer with built-in EEPROM of the present invention is based on data on the configuration of the microcomputer, as shown in FIG. 1 for its principle and as shown in FIGS. The data processing unit 11 to be processed is connected to the data processing unit 11 via a control line BUS consisting of an address signal Add, a data signal Data, a read/write signal R/W, and an interrupt request signal PS, and is electrically connected to the data processing unit 11 for writing data. EEPROMI 2 that can be automatically erased or written to, and memory content detection means 13 that prevents the memory content of the EEPROMI 2 from disappearing, the memory content detection means 1
If the memory contents of 3 have deteriorated, all EEPROMI
The memory content detecting means 13 rewrites the memory contents of EEPROM I2, and the memory content detecting means 13 writes data to the dedicated memory cell 131 whose storage performance is worse than that of the EEPROMI2 and to the dedicated memory cell 131 via the read control line R3. It is characterized in that it consists of a check voltage generation section 132 connected to the EEPROM 2, and the memory content detection means 13 is
Read system drawn from some or all cells? IvAR
s, a voltage generation control circuit 133 that supplies a read detection voltage E0 and a normal read voltage E, and an attached processing circuit 19.
．． 20, which is characterized by changing the read voltage conditions, and achieves the above object.

[Effect]

According to the microcomputer of the present invention, the EEPROM
Memory content detection means 13 for preventing loss of memory content of I2
has been established.

Konotame has previously added the EEPROM to the dedicated memory cell 131, which has degraded storage performance compared to EEPROMI2.
The information data is written in the same way as in step 12, and the information data in the dedicated memory cell 131 is read out periodically through the data processing means 11 using a program or software processing method, for example, to prevent data retention (data garbled). If there is an abnormality such as that, an interrupt request is made to the data processing unit 11, and it becomes possible to rewrite the information data initially stored in all memory cells of the EEPROMI2.

This makes it possible to always retain initially stored and highly reliable information data.

Further, according to the present invention, the storage content detection means 13 targets part or all of the memory space and changes the read voltage conditions.

Therefore, it is possible to check the memory retention state of memory cells in EEPROMI 2 that have started to cause data retention.

This may make it difficult to read information data, or
If data retention is starting to occur, the CPU
It becomes possible to request an interrupt to it, perform rewriting processing on all cells of EEPROMI2, and retain the initially stored data.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

2 to 7 are diagrams for explaining an EEPR0M built-in microcomputer according to an embodiment of the present invention, and FIG.
4 is a diagram illustrating storage content detection means according to each embodiment of the present invention. FIG.

In the figure, 131 is a dedicated memory cell (check memory cell) that serves as an indicator for retaining the stored contents of the EEPROM, and is connected to a MOS transistor Q having a select gate SG connected to a word line Wl, and a read control line R3. a MOS transistor Q having a control gate CG and a floating gate FC connected;
It is composed of

Further, 122 is a constant voltage generator that generates a normal read voltage (about 2 to 2.5 (V)), and 132 is a check voltage generator that generates a read detection voltage. In addition, Q...
Q- is a switching transistor, and Q is an inverter. Further, R3 is a read control line that transmits a read detection voltage.

The operation is similar to the read operation of EEPROMI2, but rH is applied to the check command signal line C1.

When inputted, the transistor Q1 goes to 0FFL through the inverter Qs, the supply of the read voltage to the constant voltage generator is cut off, and the read voltage from the check voltage generator 132 goes through the read control line R3 to control the transistor Q4. The electric field is involved in the charge and O charge that are manually applied to the gate CG and accumulated in the floating gate FC,
Transistor Q4 turns ON, select gate SG of transistor Q becomes rHJ, and bit line Bl
Information data “0” or “IJ” is read out.

At this time, the transistor Q of the dedicated memory cell 131 is
The memory performance of No. 4 is worse than that of the normal EEPROMI2 memory cell.

These constitute a storage content detection means that prevents the storage contents of the normal EEPROMI 2 from disappearing.Next, a method for making the memory cells of the normal EEPROMI 2 deteriorate more will be explained.

Generally, the charge (data) retention ability is determined by the difficulty of moving the charges charged in the floating gate FG by the electric field applied to the memory cell of the EEPROM.

Therefore, the holding ability is greatly influenced by the electric field strength applied to the control gate CG.

Therefore, the dedicated memory cell 131 according to the embodiment of the present invention also has a transistor Q.
Memory performance can be degraded by increasing the electric field applied to the control gate CG of No. 4.

The method of deterioration is to inject a positive charge into the floating gate FC of the transistor Q4 as stored information data.
When charged, a power supply voltage vcc-5 (V) higher than the normal read voltage is applied to the control gate CG. Furthermore, when the floating gate FG is charged with a negative charge O as storage information data, 0 [v] is applied to the control gate CG. Furthermore, by keeping the select gate (SG) of transistor Q always in the "ON" state and flowing the memory cell current between the source and drain of transistor Q4, the dedicated memory cell has a higher memory performance than the memory cell of normal EEPROMI2. can deteriorate.

FIG. 3 is a block diagram of a microcomputer with built-in EEPROM according to the first embodiment of the present invention.

In the figure, the storage content detection means 13 is a normal EEPR.
It is provided separately from the OMI2 memory space. In addition,
I2 is an electrically erasable or writable EEPROM consisting of a memory cell 121 and a constant voltage generating section 122. 14 is a sense amplifier that reads information data; 15 is an ECC circuit that checks write/read errors; 16 is a data register that holds write/read data; 117 is an address register that holds an address (designated address); and 18 is a write circuit. 11 is a CPU (Central Processing Unit) that processes data. In addition, R3 is a read control line,
PS is an interrupt request line that requests an interrupt to the CPU.

These constitute the EEPR○M built-in microcomputer according to the first embodiment.

In this way, the storage content detection means 13 is provided to prevent the storage contents of the EEPROMI 2 from disappearing.

Therefore, in advance, the EEPRO is installed in the dedicated memory cell 131 whose storage performance has deteriorated compared to the EEPROMI 2.
The information data is written in the same way as M12, and the CPU II
The jR information data of the dedicated memory cell 131 is read and processed periodically via the memory cell 131, and if there is an abnormality such as data retention (garbled data), an interrupt request is sent to the CPU II, and the initial processing is performed for all memory cells of the EEPROMI2. It becomes possible to rewrite the stored information data.

This makes it possible to always retain initially stored and highly reliable information data.

FIG. 4 shows another EEPRO according to a second embodiment of the invention.
FIG. 2 is a configuration diagram of a microcomputer with a built-in M.

In the figure, the difference from the first embodiment is that a dedicated memory cell 131 constituting the storage content detection means 13 is a normal E
Several bytes are provided at specific addresses in the EPROM 12, and the check voltage generator 132 is also incorporated into a part of the constant voltage generator 122.

Components with the same reference numerals as those in the first embodiment have the same functions, so a description thereof will be omitted.

In this way, the memory content detection means 13 is
12 memory spaces.

Therefore, compared to the first embodiment, in the second embodiment,
Although the memory space of the EEPROM is reduced by the dedicated memory cell, there is no need to provide the dedicated memory cell 131 or the check generation voltage section 132 separately from the EEPROM 12 as in the first embodiment, so this is not limited to the area occupied by the EEPROM. .

FIG. 5 is a configuration diagram of a microcomputer with built-in EEPROM according to a third embodiment of the present invention.

In the figure, what is different from the first and second embodiments is the EEPR.
This method targets part or all of the memory space of the EEPROM and changes the read conditions without providing a special memory cell 131 in which the storage contents of the OM 12 are erased.

Note that 19 is a check-only register, and EEPRO
This is a dedicated register for detecting retention of the memory contents of M. Reference numeral 20 denotes a selection means, which constitutes a switch for selecting the normal operation time a and the detection operation time a. In addition,
The selection means 20 is periodically switched by a program or hardware processing, for example, at the end of the main routine of CPtJl 1, based on command data for checking the stored contents of the CPUI 1/) EEPROM.

133 is a voltage generation control circuit, and read control line R3
This is a control circuit that supplies a read detection voltage to the

Components with the same reference numerals as those in the first embodiment have the same functions, so their explanation will be omitted.

These constitute the EEPROM built-in microcomputer according to the third embodiment, and the voltage generation control circuit 133
This will be explained next.

FIG. 6 is a diagram illustrating a voltage generation control circuit according to a third embodiment of the present invention.

In the figure, TrI is a depletion type NchMOS transistor, T, zNT, , are enhancement type MchMO3l- transistors, and Q5 is an inverter. In addition, the select gate transistor 'rrs
, Tr&, and the inverter Q can constitute the selection means 20. Further, 122 is a constant voltage generator that normally supplies the read voltage E. Note that AS is an operation control signal, RD is read command data, VCe is a power supply voltage (-5V), E is a read detection voltage read control line of about 0.5 (V), and E is a normal read voltage 2 to 2.
5 (V).

In addition, the read detection voltage value. are transistors T, ~T,
, 4 is controlled by adjusting the dimensions of .

Here, a method for detecting the storage state of a memory cell will be explained. That is, the EEP connected to the read control line R3
The read voltage condition of the ROM 12 is set by the voltage generation control means to be higher than the normal read voltage of 2 to 2.5 (V), for example, when the floating gate (FC) of the memory cell is charged with a positive charge and the information data is "0". When reading, O(V) is applied to the control gate CG.

As a result, the charges are canceled and the transistor of the memory cell becomes difficult to rONJL, making the read processing operation difficult.

Furthermore, when the floating gate FG is charged with a negative charge and the information data []J is read out, the control gate CG is set to 'r:! , source voltage■. Add. Similarly, the negative charges are canceled out, making the transistor of the memory cell less prone to rONJL.

By changing these relationships for the memory portion or all of the memory portions in which data retention (data corruption) has begun to occur in the EEPROM 12, the memory retention state can be detected.

In this way, the storage content detection means 13 changes the read voltage conditions for part or all of the memory space.

Therefore, it is possible to change the memory retention state of a memory cell in the EEPROM 12 in which data retention has started to occur.

This may make it difficult to read information data, or
If data retention is starting to occur, the CPU
It becomes possible to request an interrupt to I1, rewrite processing for all cells of the EEPROM 12, and retain the data stored initially.

〔Effect of the invention〕

As described above, according to the present invention, the storage content detecting means can detect the data retention of the initially stored information data in advance and rewrite the information data for all EEPROMs.

For this reason, EEPR has highly reliable data retention characteristics.
It becomes possible to manufacture a microcomputer with a built-in OM.

[Brief explanation of the drawing]

FIG. 1 is a diagram illustrating the principle configuration of a microcomputer according to an embodiment of the present invention, FIG. 2 is a diagram illustrating a storage content detection means according to each embodiment of the present invention, and FIG. FIG. 4 is a block diagram of a microcomputer with a built-in EEPROM according to the second embodiment of the present invention, and FIG. 5 is a block diagram of a microcomputer with a built-in EEPROM according to the second embodiment of the present invention. Configuration diagram of a microcomputer with built-in EEPROM, No. 6
The figure is a diagram explaining a voltage generation control circuit according to a third embodiment of the present invention, and FIGS.
FIG. 2 is a diagram illustrating an M-embedded microcomputer. (Explanation of symbols) 1... EEPROM built-in microcomputer, 2.
11...Data processing unit (CPU, central processing unit), 3.12...EEPROM. 13... Memory content detection means, 121... Memory cell, 122... Constant voltage generation section, 131... Dedicated memory cell, 132... Check voltage generation section, 133... Voltage generation control circuit , 14...Sense amplifier, 15...ECC circuit, 16...Data register, 17...Address register, 18...R/W control unit, 19...Check-only register, 20... - Selection means, 4, Add... address signal, 5, Data... data signal, 8... external data input line, 9... control line, 6, R/W... read/write signal ,7,PS...
Interrupt request signal, C1...Check command signal line, RD...Read command data, R3...Read control line, Be...Bit line, W2...Word line, CG...Control gate, FC...Floating gate, SG...Select gate, AS...Operation control signal, E...Normal read voltage, Eo...Read detection voltage, ■7. ．． ...Reference voltage, Q■ ~Q + 3, Q + ~Q -+'T
r+ ~Ts-transistor, Q,...inverter.

Claims (3)

[Claims] (1) A data processing unit (11) that processes data, an address signal (Add), a data signal (Data), a read/write signal (R/W), and an interrupt request signal (PS)
The data processing unit (11
) and capable of electrically erasing or writing written data; and a storage content detection means (13) for preventing the storage contents of the EEPROM (12) from disappearing; If the memory content of the memory content detection means (13) has deteriorated, all E
A microcomputer with a built-in EEPROM characterized by rewriting the stored contents of the EPROM (12). (2) The storage content detection means (13) is an EEPROM.
(12) Dedicated memory cell with worse storage performance (
131), and a check voltage generator (131) connected to the dedicated memory cell (131) via a read control line (RS).
132).
Microcomputer with built-in PROM. (3) The storage content detection means (13) is an EEPROM.
A voltage generation control circuit (133
) and an auxiliary processing circuit (19, 20) for changing read voltage conditions.
Microcomputer with built-in EPROM.