JPH0249370A - Connecting terminal and manufacture thereof - Google Patents

Connecting terminal and manufacture thereof

Info

Publication number
JPH0249370A
JPH0249370A JP63199148A JP19914888A JPH0249370A JP H0249370 A JPH0249370 A JP H0249370A JP 63199148 A JP63199148 A JP 63199148A JP 19914888 A JP19914888 A JP 19914888A JP H0249370 A JPH0249370 A JP H0249370A
Authority
JP
Japan
Prior art keywords
substrate
groove
laminated
conductors
bumps
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63199148A
Other languages
Japanese (ja)
Inventor
Toshio Kumai
利夫 熊井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP63199148A priority Critical patent/JPH0249370A/en
Publication of JPH0249370A publication Critical patent/JPH0249370A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To form a connecting terminal capable of making efficient and accurate connection of electronics devices, by utilizing laminated conductors which are cut in a specified direction with an intervening insulator set opposing to the arrangement of connecting electrodes of an electronics device to be equipped. CONSTITUTION:Plural V grooves 1a-1 are formed in parallel at specified intervals on one side of substrate 1a such as a silicon wafer and the like by means of a photo-lithography technique, a dry etching method and the like. After insulator films 5 are formed on both surface and back sides including the grooves, a metal conductor 1b of about 50mum diameter is inserted in every groove. Necessary number of such substrate are laminated and stuck in the same direction, and the thickness of the substrate 1a is determined so that a distance between adjoining conductors 1b may equal to an interval between the connecting electrodes 2a of an electronics device. A group of the substrates thus laminated are cut transverse to the direction of the groove, bumps 1b-1 are formed in places of the conductors 1b, and insulator films 5a are produced in other surface than the bumps to form a connecting terminal 1.

Description

【発明の詳細な説明】 〔概 要〕 回路基板などに電子デバイスを実装する際に用いる接続
用端子及びその製造方法に関し、電子デバイスを回路基
板と電子デバイスとの間に介挿して効率よく正確に接続
することを目的とし、 両面が少なくとも絶縁され片面に■溝を並列穿設し該■
溝に導体を介挿する基板を同一方向に積層し格子状に配
列された導体の■溝と直交する両端面上にバンプを備え
るように構成し、前記基板に■溝を形成する工程と、該
■溝に棒状の前記導体を介挿し基板を同一方向に積層接
着し積層基板を形成する工程と、該積層基板を■溝と直
交する方向にスライスして薄片基板を形成する工程と、
該薄片基板の導体の両端スライス面上にバンプを形成す
る工程とを含んで製造するように構成する。
[Detailed Description of the Invention] [Summary] Regarding connection terminals used when mounting electronic devices on a circuit board, etc., and a method for manufacturing the same, the electronic device can be inserted between the circuit board and the electronic device in an efficient and accurate manner. Both sides are at least insulated and grooves are drilled in parallel on one side to connect the
(2) forming substrates in which conductors are inserted in the grooves in the same direction so that bumps are provided on both end faces of the conductors arranged in a lattice pattern perpendicular to the (2) grooves; (1) inserting the rod-shaped conductor into the groove and laminating and bonding the substrates in the same direction to form a laminated substrate; (2) slicing the laminated substrate in a direction perpendicular to the groove to form a thin piece substrate;
The manufacturing method is configured to include a step of forming bumps on both end sliced surfaces of the conductor of the thin piece substrate.

〔産業上の利用分野〕[Industrial application field]

本発明は回路基板などに電子デバイスを実装する際に用
いる接続用端子及びその製造方法に関する。
The present invention relates to a connection terminal used when mounting an electronic device on a circuit board or the like, and a method for manufacturing the same.

回路基板等に電子デバイス、例えば半導体ベアチップ等
をフリップチップ方式で実装する場合、格子状に並んだ
半導体チップの電極側、または回路基板のランド側に半
田ボールを接合して半田バンプを形成し、回路基板に半
導体チップを載せて加熱圧着して接続する。
When mounting electronic devices, such as semiconductor bare chips, on a circuit board using the flip-chip method, solder balls are bonded to the electrode side of the semiconductor chips arranged in a grid or to the land side of the circuit board to form solder bumps. A semiconductor chip is placed on a circuit board and connected by heat and pressure bonding.

この半田ボールは、直径100μm程度の銅ボールに半
田めっきを施した微小径の半田ボールで接合の際、半導
体チップの電極ピンチが高密度になるに伴って高精度に
位置合わせするのに難点があり、しかも半田ボールを1
個づつ接合するため、相当の工数が掛かる問題がある。
This solder ball is a copper ball with a diameter of about 100 μm that is solder-plated. When bonding, it is difficult to align the electrodes with high precision as the density of the electrode pinches on the semiconductor chip increases. Yes, and one solder ball
There is a problem in that it takes a considerable amount of man-hours to join each piece one by one.

そのため、回路基板と電子デバイスとの間に介挿して効
率よ(正確に接続することのできる接続用端子が要望さ
れている。
Therefore, there is a need for a connection terminal that can be inserted between a circuit board and an electronic device for efficient (accurate) connection.

〔従来の技術〕[Conventional technology]

従来は第5図の側断面図に示すように、回路基板103
のランド103a、または電子デバイス102、例えば
半導体チ・ノブの電極102aに半田ボール104を1
個つづ接合して半田ハンプを形成し、回路基板103に
半導体チップ102を載せて加熱圧着し実装している。
Conventionally, as shown in the side sectional view of FIG.
A solder ball 104 is placed on the land 103a of the electronic device 102, for example, on the electrode 102a of a semiconductor chip knob.
The semiconductor chips 102 are bonded one by one to form a solder hump, and the semiconductor chip 102 is placed on the circuit board 103 and bonded under heat and pressure for mounting.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかしながら、このような上記バンプ接続によれば、半
導体チップの電極ピッチが高密度になるに伴って半田ボ
ールの直径も小径となり、その微小径の半田ボールを回
路基板のランドに接合する場合、位置合わせを高精度に
行うのが難しく、しかも半田ボールを1個つづ接合する
ため工数が大幅に掛かり製造コストが嵩むといった問題
があった。
However, according to the bump connection described above, as the electrode pitch of the semiconductor chip becomes denser, the diameter of the solder ball also becomes smaller, and when bonding the solder ball with the minute diameter to the land of the circuit board, the position becomes smaller. There are problems in that it is difficult to perform alignment with high precision, and moreover, the number of man-hours required to join the solder balls one by one increases, which increases manufacturing costs.

上記問題点に鑑み、本発明は電子デバイスを回路基板と
電子デバイスとの間に介挿して効率よく正確に接続する
ことのできる接続用端子及びその製造方法を提供するこ
とを目的とする。
In view of the above-mentioned problems, an object of the present invention is to provide a connection terminal that can efficiently and accurately connect an electronic device by inserting it between a circuit board and an electronic device, and a method for manufacturing the same.

〔課題を解決するための手段〕[Means to solve the problem]

上記目的を達成するために、本発明の接続用端子及びそ
の製造方法においては、両面が少なくとも絶縁され片面
にV溝を並列穿設し該■溝に導体を介挿する基板を同一
方向に積層し格子状に配列された導体のV溝と直交する
両端面上にバンプを備えるように構成する。
In order to achieve the above object, in the connection terminal and the method for manufacturing the same of the present invention, substrates are laminated in the same direction, both sides of which are at least insulated, V-grooves are bored in parallel on one side, and conductors are inserted into the grooves. Bumps are provided on both end faces perpendicular to the V-grooves of the conductors arranged in a lattice pattern.

そして、前記基板に■溝を形成する工程と、該V溝に棒
状の前記導体を介挿し基板を同一方向に積層接着し積層
基板を形成する工程と、該積層基板をV溝と直交する方
向にスライスして薄片基板を形成する工程と、該薄片基
板の導体の両端スライス面上にバンプを形成する工程と
を含んで製造するように構成する。
a step of forming a groove in the substrate; a step of inserting the bar-shaped conductor into the V-groove and laminating and bonding the substrates in the same direction to form a laminated substrate; and forming a laminated substrate in a direction perpendicular to the V-groove. The manufacturing method is configured to include a step of slicing the thin substrate to form a thin piece substrate, and a step of forming bumps on both end sliced surfaces of the conductor of the thin piece substrate.

〔作用〕[Effect]

基板の片面にV溝を設は棒状導体を挿入した基板を同一
方向に多層に積層することにより、■溝と直角な面に導
体を格子状に配列することができ、積層基板を■溝と直
交する方向にスライスし、そのスライス面に露出する導
体の両端面にバンプを形成することにより、回路基板の
ランドと電子デバイスの電極とを一度に接続することが
できる。
By creating a V-groove on one side of a board and stacking multiple boards in the same direction with rod-shaped conductors inserted, it is possible to arrange the conductors in a lattice pattern on a surface perpendicular to the groove, and the laminated board can be By slicing the conductor in orthogonal directions and forming bumps on both end surfaces of the conductor exposed on the sliced surface, the lands of the circuit board and the electrodes of the electronic device can be connected at once.

〔実施例〕〔Example〕

以下図面に示した実施例に基づいて本発明の要旨を詳細
に説明する。
The gist of the present invention will be explained in detail below based on embodiments shown in the drawings.

本実施例の接続用端子lは、第2図の側断面図に示すよ
うに回路基板3に電子デバイス2、例えば格子配列の電
極を備える半導体チップをフリップチップ方式で実装す
る場合に用いる。
The connection terminal 1 of this embodiment is used when an electronic device 2, for example, a semiconductor chip having a grid array of electrodes, is mounted on a circuit board 3 by a flip-chip method, as shown in the side cross-sectional view of FIG.

接続用端子1は基板1a、例えばシリコンウェーハの片
面に半導体チップ2の電極(Au)2aに対応し同じ配
列間隔でV溝1a−1を備え、基板1aの全面を絶縁酸
化処理してV?J*1a−1に棒状の導体1b、即ち直
径約50μmの金線(Au)または銅線(Cu)を介挿
し、基板1aを同一方向に積層することにより■溝1a
−1と直角な面に半導体チップ2の電t12aと同じ格
子配列の導体1bを形成し、■溝1a−1と直角な導体
1bの両端面上にバンプ用金属、即ち鉛(Pb)を蒸着
形成したバンプ1b−1を突設して構成する。
The connection terminal 1 is provided with V grooves 1a-1 on one side of a substrate 1a, for example a silicon wafer, corresponding to the electrodes (Au) 2a of the semiconductor chip 2 and arranged at the same spacing, and the entire surface of the substrate 1a is subjected to insulation oxidation treatment to form V grooves 1a-1. By inserting a rod-shaped conductor 1b, that is, a gold wire (Au) or a copper wire (Cu) with a diameter of approximately 50 μm, into J*1a-1 and stacking the substrates 1a in the same direction, the groove 1a is formed.
A conductor 1b having the same lattice arrangement as the conductor t12a of the semiconductor chip 2 is formed on a surface perpendicular to the groove 1a-1, and bump metal, that is, lead (Pb) is vapor-deposited on both end surfaces of the conductor 1b perpendicular to the groove 1a-1. The formed bump 1b-1 is provided in a protruding manner.

次に、この接続用端子1の製造方法について、第1図の
工程順に示す側断面図を用いて説明する。
Next, a method for manufacturing the connection terminal 1 will be described using side sectional views shown in the order of steps in FIG.

第1図(alはレジストパターンの形成工程を示す。FIG. 1 (al indicates the process of forming a resist pattern).

基板1a、即ち表面のミラー指数100、後工程で形成
する■溝1a−1面のミラー指数111を有する板厚3
00μmのシリコンウェーへの片面にホトリソグラフィ
技術により接続する電極2aと同じ配列間隔の■溝1a
−1をエツチング形成するためのレジストパターン4を
形成する。基板1aの厚さは、次工程で形成するV溝1
a−1の深さと関連し、V溝1a−1に後工程で導体i
bを介挿し積層・圧着したとき、積層方向の導体1bの
間隔が接続する電極2aの配列間隔と対応し同じ間隔と
なるように決定する。
Substrate 1a, that is, plate thickness 3 having a Miller index of 100 on the front surface and a Miller index of 111 on the groove 1a-1 surface formed in a later process.
Grooves 1a with the same spacing as the electrodes 2a connected by photolithography on one side of the 00 μm silicon wafer.
A resist pattern 4 is formed for etching. The thickness of the substrate 1a is the same as that of the V-groove 1 formed in the next step.
In relation to the depth of a-1, a conductor i is placed in the V-groove 1a-1 in a later process.
When the conductors 1b are inserted and laminated and crimped, the spacing between the conductors 1b in the lamination direction is determined to correspond to and be the same as the spacing between the electrodes 2a to be connected.

第1図tb+は■溝1a−1の形成工程を示す。ドライ
エツチング法、例えばプラズマエツチング法により異方
性エツチングを利用して頂角約70どのV溝1a−1を
形成した後、レジストパターン4を除去する。■溝1a
−1の深さは、導体1bをV溝面に当接したとき導体1
bの上面が基板1aの表面から出るようにする。
FIG. 1 tb+ shows the step of forming the groove 1a-1. After forming a V-groove 1a-1 with an apex angle of about 70 mm using anisotropic etching using a dry etching method, for example, a plasma etching method, the resist pattern 4 is removed. ■ Groove 1a
-1 depth is the depth of conductor 1 when conductor 1b is in contact with the V-groove surface.
The upper surface of the substrate 1b is made to protrude from the surface of the substrate 1a.

第1図(C)は絶縁皮膜形成5の工程を示す。スチーム
酸化法により基板1aのV溝1a−2を含む表裏面に絶
縁皮膜(SiO□)5を形成する。
FIG. 1(C) shows the step 5 of forming an insulating film. An insulating film (SiO□) 5 is formed on the front and back surfaces of the substrate 1a including the V-groove 1a-2 by a steam oxidation method.

第1図(d)は基板1aの積層工程を示す。電気絶縁さ
れたV溝18−1に棒状の導体1b、即ち直径約50μ
mの金線(Au)または銅線(Cu)を介挿し、基板1
aを同一方向に順次、積層し接着剤6、例えばポリイミ
ド樹脂接着剤または低融点ガラス接着剤により圧着する
。基板1aの積層する段数は接続する電極2aの配列数
に合わせ、最後層の導体1b上には■溝1a−1のある
基板1aでな(、図示するように■溝1a−1のない基
板11aを積層してもよい。
FIG. 1(d) shows the process of laminating the substrate 1a. A rod-shaped conductor 1b, that is, a diameter of about 50μ, is placed in the electrically insulated V-groove 18-1.
m gold wire (Au) or copper wire (Cu) is inserted, and the substrate 1
(a) are laminated one after another in the same direction and pressed together with an adhesive 6, such as a polyimide resin adhesive or a low melting point glass adhesive. The number of laminated layers of substrates 1a is matched to the number of arrays of electrodes 2a to be connected. 11a may be stacked.

第1図(e)は積層基板12aのスライス工程を示す。FIG. 1(e) shows the slicing process of the laminated substrate 12a.

マルチワイヤソー切断機により、積層した基板1a、即
ち積層基板12aを■溝1a−1と直交する方向に10
0〜200μmの厚さにスライスする。即ち、導体1b
が多芯の格子状配・列のなった薄片基板13aを得るこ
とができる。
Using a multi-wire saw cutting machine, the laminated substrate 1a, that is, the laminated substrate 12a, is cut 10 times in the direction perpendicular to the groove 1a-1.
Slice to a thickness of 0-200 μm. That is, conductor 1b
It is possible to obtain a thin piece substrate 13a in which a multi-core lattice-like arrangement/column is formed.

第1図(f)は絶縁皮膜5aの形成工程を示す。薄片基
板13aの表裏スライス面は基板1aの素地が出て電気
絶縁性がないため、スチーム酸化法により絶縁皮膜(S
ing)5aを形成する。このとき、積層に用いた接着
剤6、即ちポリイミド樹脂または低融点ガラス接着剤は
耐酸性があるので侵されることはない。なお、導体1b
が金線でなく銅線の場合は、次工程のために酸化形成さ
れた酸化銅(Cub)皮膜(図示路)を塩酸処理により
剥離除去する工程が入る。
FIG. 1(f) shows the process of forming the insulating film 5a. Since the base material of the substrate 1a is exposed on the front and back sliced surfaces of the thin substrate 13a and there is no electrical insulation, an insulating film (S
ing) form 5a. At this time, the adhesive 6 used for lamination, ie, polyimide resin or low melting point glass adhesive, is acid resistant and will not be attacked. Note that the conductor 1b
If the wire is not a gold wire but a copper wire, there is a step in which the oxidized copper oxide (Cub) film (as shown in the figure) is peeled off and removed by hydrochloric acid treatment for the next step.

第1図(glはバンプの形成工程を示す。薄片基板13
aの表裏面にホトリソグラフィ技術により導体1bだけ
を露出してレジストパターン(図示路)を形成した後、
導体1bの両端スライス面上にバンプ用金属、即ち鉛(
Pb)または錫(Sn)などの低融点金属を蒸着法によ
り真空蒸着し、高さ約10μmのバンプ1b〜1を形成
して接続用端子1を完成する。
FIG. 1 (gl indicates the bump formation process. Thin substrate 13
After forming a resist pattern (path shown) on the front and back surfaces of a by exposing only the conductor 1b using photolithography technology,
Bump metal, namely lead (
A low melting point metal such as Pb) or tin (Sn) is vacuum-deposited by a vapor deposition method to form bumps 1b to 1 with a height of about 10 μm, thereby completing the connection terminal 1.

なお、バンプ1b−1形成に用いるバンプ用金属は接続
する電極2aの材質により選定するが、上記実施例の金
とは異なり、アルミニウム(八β)電極の場合は金(^
U)を蒸着する。また、蒸着は蒸着法の他、スパッタリ
ング法、あるいは電気めっき法によってもよい。
Note that the bump metal used to form the bump 1b-1 is selected depending on the material of the electrode 2a to be connected, but unlike the gold in the above example, gold (^
U) is deposited. In addition to the vapor deposition method, the vapor deposition may be performed by a sputtering method or an electroplating method.

第2図は第1図(幻の斜視図で完成した接続用端子1を
示す。
FIG. 2 shows the completed connection terminal 1 in FIG. 1 (phantom perspective view).

この接続用端子1を用いて回路基板3のランド3aに半
導体チップ2を実装する場合は、第3図の実装状態を示
す側断面図のように、接続用端子1のバンプ1b−1に
半田ペースト(図示路)を付着し接続用端子1を半導体
チップ2の電極2aに仮固定し、ついで回路基板3のラ
ンド3a上に仮固定した後、加熱圧着して実装する。
When mounting the semiconductor chip 2 on the land 3a of the circuit board 3 using this connection terminal 1, solder is applied to the bump 1b-1 of the connection terminal 1 as shown in the side sectional view showing the mounting state in FIG. The connection terminals 1 are temporarily fixed to the electrodes 2a of the semiconductor chip 2 by adhering a paste (as shown in the diagram), and then temporarily fixed onto the lands 3a of the circuit board 3, followed by heat-pressing and mounting.

なお、上記第1図(e)の積層基板のスライス工程の次
に、絶縁皮膜5aを形成する前に薄片基板13aの表裏
両面をエツチングして板厚をtに薄くシ、導体1bを僅
かに突出させるためのウェットエツチング工程を組入れ
てもよい。即ち、第4図の側断面図に示すように導体1
bが金線の場合、スライス面は腐食される恐れがないの
でレジストパターンを形成することなくそのままの状態
で、また導体1bがw4線の場合はスライスされた薄片
基板13aの表裏両面にホトリソグラフィ技術により導
体1bの両スライス面を覆い薄片基板13a面だけを露
出するレジストパターン(図示路)を形成した後、薄片
基板13aだけを弗酸エツチングによりエツチングする
。これにより導体1bを突出させてバンプ1b1を形成
し易くするとともに、接続を確実に行うことができる。
In addition, after the step of slicing the laminated substrate shown in FIG. 1(e) above, before forming the insulating film 5a, both the front and back surfaces of the thin substrate 13a are etched to reduce the thickness to t, and the conductor 1b is slightly etched. A wet etching step for protrusion may also be incorporated. That is, as shown in the side sectional view of FIG.
When b is a gold wire, the sliced surface is left as it is without forming a resist pattern because there is no risk of corrosion, and when the conductor 1b is a W4 wire, photolithography is performed on both the front and back sides of the sliced thin substrate 13a. After forming a resist pattern (the path shown in the figure) covering both sliced surfaces of the conductor 1b and exposing only the surface of the thin substrate 13a using a technique, only the thin substrate 13a is etched using hydrofluoric acid etching. This allows the conductor 1b to protrude, making it easier to form the bump 1b1, and making it possible to securely connect the conductor 1b.

第4図の側断面図はこの方法によりバンプ1b−1を形
成した状態を示す。
The side sectional view of FIG. 4 shows the bump 1b-1 formed by this method.

このように上記構成の接続用端子とその製造方法によれ
ば、基板に高精度のV溝を設は導体を挿入して多層に積
層することにより、■溝と直角な面に導体を格子状に配
列することができ、この積層基板を■溝と直交する方向
にスライスし導体両端面にバンプを突設することにより
、回路基板のランドと半導体チップの電極との間に介挿
し短時間で接続することができる。
In this way, according to the connecting terminal having the above structure and its manufacturing method, by forming a high-precision V-groove in the board, inserting conductors and stacking them in multiple layers, conductors can be arranged in a grid pattern on a surface perpendicular to the grooves. By slicing this laminated board in the direction perpendicular to the groove and protruding bumps on both end faces of the conductor, it can be inserted between the land of the circuit board and the electrode of the semiconductor chip in a short time. Can be connected.

また、この場合、基板の素材に半導体チップと同じシリ
コンウェーハを用いているため、エツチングにより加工
される■溝は、極めて微細・精密に加工することができ
、電子デバイスの電極に正確に対応する接続用端子を形
成することができる。
In addition, in this case, since the same silicon wafer as the semiconductor chip is used as the substrate material, the grooves processed by etching can be processed extremely finely and precisely, allowing them to accurately correspond to the electrodes of electronic devices. A connection terminal can be formed.

また、基板の熱膨張係数が同じであるため、半導体チッ
プの発熱によって生じる熱膨張差により機械的、電気的
接続の信頼性を損なうことはない。
Furthermore, since the substrates have the same coefficient of thermal expansion, the reliability of mechanical and electrical connections will not be impaired due to differences in thermal expansion caused by heat generation of the semiconductor chip.

更にまた、回路基板への実装作業は接続される電極に合
わせて予め、配設されたバンプを用いるため、従来のよ
うに半田ボールを回路基板または電子デバイスに1個つ
づ付着するのに比べて一括処理で接続することでき、作
業が極めて簡単で工数を大幅に軽減することができる。
Furthermore, since the mounting work on the circuit board uses bumps that have been placed in advance according to the electrodes to be connected, it is faster than attaching solder balls one by one to the circuit board or electronic device as in the past. Connections can be made in batches, making the work extremely simple and greatly reducing man-hours.

〔発明の効果〕〔Effect of the invention〕

以上、詳述したように本発明によれば、電子デバイスの
電極に対応してシリコンウェーハなどの基板に■溝を形
成し、導体を介挿してこれを積層することにより、例え
ば格子状配列の端子を形成し、その端子に予め、バンプ
を形成し、1枚の多芯接続用端子とすることにより、回
路基板と電子デバイスとを一度に効率よく正確に実装す
ることができ、接続の信頌度を向上し製造コストの低減
を図ることができるといった工業上極めて有用な効果を
発揮する。
As described in detail above, according to the present invention, grooves are formed in a substrate such as a silicon wafer corresponding to the electrodes of an electronic device, and the grooves are stacked with conductors inserted therein, thereby forming, for example, a lattice-like arrangement. By forming a terminal and forming a bump on the terminal in advance to form a single multi-core connection terminal, a circuit board and an electronic device can be efficiently and accurately mounted at once, and connection reliability is improved. It exhibits extremely useful effects industrially, such as being able to improve sophistication and reduce manufacturing costs.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図fa)〜(川は本発明による一実施例の工程順を
示す側断面図、 第2図は第1図(g)の完成した接続用端子の斜視図、 第3図は第2図を用いた実装を示す側断面図、第4図は
第1図(g)の導体を突出させバンプを形成した状態を
示す側断面図、 第5図は従来技術による実装を示す側断面図、である。 図において、 ■は接続用端子、 1a、l1aは基板、 1a−1はV溝、 1bは導体、 1b−1はバンプ、 2は電子デバイス(半導体チップ)、 2aは電極、 3は回路基板、 3aはランド、 4はレジストパターン、 5.5aは絶縁皮膜、 6は接着剤、 12aは積層基板、 13aは薄片基板を示す。 レジストパターン形成工程 fal ■溝形成工程 (bl 基板の積石工程 積層基板のスライス工程 fal 絶縁皮膜形成工程 fl バンプ形成工程 gl
Figures 1 (fa) to (9) are side sectional views showing the process order of an embodiment according to the present invention, Figure 2 is a perspective view of the completed connection terminal shown in Figure 1 (g), and Figure 3 is a FIG. 4 is a side sectional view showing a state in which the conductor shown in FIG. 1(g) is protruded to form a bump; FIG. In the figure, ■ is a connection terminal, 1a and l1a are substrates, 1a-1 is a V-groove, 1b is a conductor, 1b-1 is a bump, 2 is an electronic device (semiconductor chip), 2a is an electrode, 3 is a circuit board, 3a is a land, 4 is a resist pattern, 5.5a is an insulating film, 6 is an adhesive, 12a is a laminated board, and 13a is a thin piece board.Resist pattern forming process fal ■Groove forming process (bl) of the substrate Stone stacking process Laminated substrate slicing process fal Insulating film formation process fl Bump formation process gl

Claims (1)

【特許請求の範囲】 〔1〕両面が少なくとも絶縁され片面にV溝(1a−1
)を並列穿設し該V溝(1a−1)に導体(1b)を介
挿する基板(1a)を同一方向に積層し格子状に配列さ
れた導体(1b)のV溝(1a−1)と直交する両端面
上にバンプ(1b−1)を備えることを特徴とする接続
用端子。 〔2〕基板(1a)にV溝(1a−1)を形成する工程
と、該V溝(1a−1)に棒状の前記導体(1b)を介
挿し基板(1a)を同一方向に積層接着し積層基板(1
2a)を形成する工程と、該積層基板(12a)をV溝
(1a−1)と直交する方向にスライスして薄片基板(
13a)を形成する工程と、該薄片基板(13a)の導
体(1b−1)の両端スライス面上にバンプ(1b−1
)を形成する工程とを含むことを特徴とする接続用端子
の製造方法。
[Scope of Claims] [1] Both sides are at least insulated and one side has a V-groove (1a-1
) are bored in parallel and the conductors (1b) are inserted into the V-grooves (1a-1).The substrates (1a) are laminated in the same direction, and the conductors (1b) are arranged in a grid pattern. ) A connection terminal comprising bumps (1b-1) on both end faces orthogonal to the bumps (1b-1). [2] Forming a V-groove (1a-1) in the substrate (1a), inserting the rod-shaped conductor (1b) into the V-groove (1a-1), and laminating and bonding the substrate (1a) in the same direction. Laminated board (1
2a) and slicing the laminated substrate (12a) in a direction perpendicular to the V-groove (1a-1) to form a thin piece substrate (
13a) and forming bumps (1b-1) on both end sliced surfaces of the conductor (1b-1) of the thin piece substrate (13a).
) A method for manufacturing a connection terminal, the method comprising:
JP63199148A 1988-08-09 1988-08-09 Connecting terminal and manufacture thereof Pending JPH0249370A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63199148A JPH0249370A (en) 1988-08-09 1988-08-09 Connecting terminal and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63199148A JPH0249370A (en) 1988-08-09 1988-08-09 Connecting terminal and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH0249370A true JPH0249370A (en) 1990-02-19

Family

ID=16402948

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63199148A Pending JPH0249370A (en) 1988-08-09 1988-08-09 Connecting terminal and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH0249370A (en)

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