JPH0249418A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To minimize the size of a semiconductor device for making a large scale integrated circuit by a method wherein adjacent two regions are exposed using the same alignment marks to reduce the margin with the alignment slip of a junction part. CONSTITUTION:First, during the pre-wiring process such as element isolating process, etc., a stepped part is previously formed between an alignment mark 1 and another alignment mark 2. Secondly, during the later wiring process, the surface is coated with a wiring metal and after further coating with a positive type photoresist, an exposure region 3 is aligned using the marks 1 and 2 to perform the exposure. Another exposure region 4 is exposed using the same marks 1 and 2 as well as another mask different from that for the region 3. The whole body is developed to form a wiring pattern of the resist. Later, the resist is released by metallic etching process to form a specified wiring. Through these procedures, the size of a semiconductor device is minimized to make a large scale integrated circuit (LSI).

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a method of manufacturing a semiconductor device having a large-scale integrated circuit.

[Summary of the invention]

The present invention provides functions of a reduced projection exposure apparatus by exposing each single semiconductor device multiple times using the same alignment mark in the photolithography process for manufacturing semiconductor devices having large-scale integrated circuits. This makes it possible to manufacture a semiconductor device having a larger integrated circuit without increasing the number of semiconductor manufacturing processes. [Conventional technology 1] In the conventional technology, a single semiconductor device 1 can be manufactured by -per process,-
It was manufactured using multiple exposures. [Problems to be Solved by the Invention] In the exposure method described above, the size of the exposure area of the lens of the reduction projection exposure device becomes the limit of the size of the semiconductor device. It has been difficult to manufacture large-scale integrated circuits exceeding 2 cm.Also, if you try to make a single large-scale integrated circuit by forcibly exposing the area several times, there will be difficulties in connecting the exposed areas. This method has the drawbacks that the process becomes complicated, such as requiring ample wiring space and increasing the number of wiring steps, and that the degree of integration does not increase as the size of the semiconductor device increases. [Means for Solving the Problems] In order to solve the above problems, in the present invention, in the process of manufacturing each single semiconductor device by multiple exposures, adjacent An alignment mark is inserted between the two chips, and in the later wiring process, the same alignment mark is used to align two adjacent exposures, and the boundary wiring part is exposed overlappingly. [Function] In the process of manufacturing each single semiconductor device by multiple exposures after one resist coating, adjacent exposures are performed using the same alignment mark, so the bonding portions are The margin for misalignment is extremely small, so there is no need to use particularly large wiring lines, and there is no need to increase the number of steps other than exposure and alignment, allowing for large areas (twice or more than conventional). [Embodiment] A first embodiment of the present invention will be described below based on Fig. 1. Fig. 1 is a plan view of the exposure area. In FIG. 1, alignment marks 1 are prepared in advance in a pre-process 1, such as a device isolation process, or a pre-wiring process.
A step is formed between and 2. In the later wiring process, after coating the wiring metal and coating it with a positive photoresist, area 3 is coated with
Using alignment marks 1 and 2, for example λThrough
gh The Lens method is used to perform alignment, and a reduction projection exposure device is used to perform exposure.
Similarly, in region 4, using alignment marks 1 and 2,
Exposure is performed using a reduction projection exposure apparatus using a mask different from that for area 3. After such an exposure step, development is performed to form a wiring pattern using resist. Thereafter, the desired wiring can be obtained by etching the metal and peeling off the resist. Here, even if alignment errors and the like are taken into consideration, the overlapping region 5 in regions 3 and 4 in FIG. Depending on the exposure area of the lens of the device, it is not necessarily as shown in Figure 1. - It does not need to be a straight line; any shape is possible as long as there is an overlapping exposure area of about 1 μm. Here, as an example in which the overlapping area is not in a straight line, the second
An embodiment will be described based on FIG. 2, a third embodiment on the basis of FIG. 3, and a fourth embodiment on the basis of FIG. 5. FIG. 2, FIG. 3, and FIG. 4 are plan views showing exposure areas in each example. In the second, third, and fourth embodiments, using alignment marks 1 and 2 in FIGS. 2 to 4, areas 3 and 4 are combined with an overlapping exposure area 5 having a complicated shape. By performing exposure, desired wiring can be obtained as in the first embodiment. In addition, when connecting the wiring between regions 3 and 4 in the overlapping region 5 in FIGS. 1 to 4, the design dimensions are determined in advance at the time of mask creation, taking into account misalignment and thinning of the line width due to overlapping exposure. It is necessary to make it thicker than the wiring pattern, but RB
In the lens and alignment method used in conventional reduction projection exposure equipment, this amount of thickening is determined by the size on the wafer. lLLm or less is quite possible. A more complicated fifth embodiment will be explained with reference to FIG. 5. FIG. 5 is a plan view of the exposure area of the fifth embodiment. Reference numerals 6, 7, 8, and 9 are alignment mark areas previously formed in the previous process. After coating the wiring metal and coating a positive photoresist thereon, first the region 10 is exposed using the alignment mark regions 6 and 7. At this time, areas 17a, 17b, and area 1
6 is also exposed at the same time. Next, using the same alignment mark areas 6 and 7, area 11 is exposed using a mask different from that used for exposing area 10. At this time, along with the area 11, the areas 18a, 18b, and 16.19 are also exposed at the same time. Therefore, region 16 is an overlapping region of regions IO and 11. Further, regions 14a and 14b are exposed using alignment mark regions 6 and 7 and another mask. At this time, regions 17a and 17b are also exposed. Then, regions 17a and 18b become overlapping regions with region IO. Further, the regions 14a and 14b may be exposed twice using separate masks. Similarly, using alignment mark areas 6 and 7, one overlapping area 18a is used using a mask different from the mask used previously.
, 18b as well as regions 15a and 15b are exposed. In the above, the overlap area 16,! 7a, 17b, 18a
, 18b are discussed in the first section.
This is similar to the consideration in region 5 of the figure. Furthermore, using alignment mark areas 8 and 9 and using a mask different from the mask used previously, area F! Expose i12. At this time, along with region 12, regions 19 and 20 are exposed. Finally, using alignment mark areas 8 and 9, area 13 is exposed using yet another mask. At this time, the area 20 as well as the area 13 are exposed. Since the consideration regarding the area 20 is similar to that of the area 5 in FIG. 1 showing the first embodiment, the design dimensions of the mask are also as follows.
The same procedure as in area 5 in FIG. 1 can be made. Also, area 19 is one overlapping area, but area 11 and area 1
2 is exposed using another alignment mark, so the line width of the mask and the interval between them must be made wider than in area 5 of FIG. 1. A desired wiring process can be obtained through development, metal etching, and resist peeling processes. By combining the alignment and exposure steps as described above, it is possible to form wiring for various large-scale integrated circuits. Note that it is more suitable for miniaturization if the alignment and exposure in the photolithography process, which is another process, are performed in the same manner as in the wiring process. [Effects of the Invention] As explained above, the present invention has the effect of making it possible to manufacture large-scale integrated circuits without increasing the number of steps while minimizing the size of the semiconductor device.

[Brief explanation of the drawing]

1 is a plan view of an exposure region of a semiconductor device according to a first embodiment of the present invention, FIG. 2 is a plan view of an exposure region of a semiconductor device according to a second embodiment of the present invention, and FIG. FIG. 4 is a plan view of an exposure region of a semiconductor device according to a third embodiment of the invention, and FIG. 5 is a plan view of an exposure region of a semiconductor device according to a fourth embodiment of the invention.
FIG. 7 is a plan view of an exposure region of a semiconductor device according to a fifth embodiment, which is a more complicated application example of the present invention. 6. 10°15a. 16゜20 ・ 7.8, 9 Alignment mark area 11.12.13.14a, 14b, 15b...Exposure area 17a, 17b, 18a, 18b, 19...Overlapping exposure area SEIKO ELECTRONICS INDUSTRIES CO., LTD. Patent Attorney Keisuke Hayashi / Alignment mark area / alignment mark area / exposure area / exposure area / overlapping exposure area Shiny (demand for 7I+) Product name of L area J side

Claims (1)

[Claims] In the microfabrication lithography process of semiconductor manufacturing, there are two steps: coating a semiconductor substrate with photoresist, dividing one semiconductor substrate into multiple exposures, and exposing two adjacent times during multiple exposures. Manufacture of a semiconductor device characterized by comprising the steps of exposing the boundary portion to light overlappingly using the same alignment mark on the boundary, and developing and etching leaving a desired location of the resist. Method.