JPH0249430A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0249430A JPH0249430A JP19900788A JP19900788A JPH0249430A JP H0249430 A JPH0249430 A JP H0249430A JP 19900788 A JP19900788 A JP 19900788A JP 19900788 A JP19900788 A JP 19900788A JP H0249430 A JPH0249430 A JP H0249430A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- layer
- wiring layer
- semiconductor device
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 239000010410 layer Substances 0.000 claims description 32
- 239000011229 interlayer Substances 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 239000010408 film Substances 0.000 description 11
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 230000001771 impaired effect Effects 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明は半導体装置に係り、特に半導体装置における配
線の構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device, and particularly to a wiring structure in a semiconductor device.
(従来の技術)
半導体装置においては機能素子を形成したのち、これら
の素子間に配線を施して各々の素子を電気的に連結させ
所望の回路機能を得ている。この際、配線を単一層のみ
で行なうと、素子の集積度を上げるとともに配線が複雑
化して@細化の限界に接近するため製造が困難であった
。そこで、ICの高度集積化に伴い配線の占有面積を少
なくするなめ、配線を複数層とする多層配線がなされて
いた。(Prior Art) In a semiconductor device, after functional elements are formed, wiring is provided between these elements to electrically connect each element to obtain a desired circuit function. At this time, if wiring is performed in only a single layer, manufacturing becomes difficult because the degree of integration of the elements increases and the wiring becomes complicated, approaching the limit of thinning. Therefore, in order to reduce the area occupied by wiring as ICs become more highly integrated, multilayer wiring in which wiring is arranged in multiple layers has been used.
゛多層配線は、基板内に形成された各素子領域と第1層
目の配線との間、配線と配線との間に層間絶縁膜を介在
させ、所定の領域に穿孔されるコンタクト孔を介して異
なる層の配線間を電気的に接続して形成される。゛Multilayer wiring is achieved by interposing an interlayer insulating film between each element region formed in the substrate and the first layer wiring, and between the wirings, and connecting the wiring through contact holes drilled in predetermined areas. It is formed by electrically connecting wires in different layers.
すなわち、例えば第2図に示すように、シリコン基板1
の素子分離領域1aに接続するように、アルミニウム金
属等から成る第1層目の配線2を図の表裏方向に帯状に
形成する。配線2上に層間絶縁膜3を着膜し、更にアル
ミニウム薄膜を堆積し、これをフォトリソ法によりパタ
ーニングし、第1層目の配線2とは異なり図の左右方向
に帯状となるパターン形状を有する第2層目の配線4を
形成する。配線2と配線4との接続が必要な場合には、
所望箇所の層間絶縁膜3にコンタクト孔(図示せず)を
形成して両者間を接続していた。That is, for example, as shown in FIG.
A first layer wiring 2 made of aluminum metal or the like is formed in a band shape in the front and back directions of the figure so as to be connected to the element isolation region 1a. An interlayer insulating film 3 is deposited on the wiring 2, a thin aluminum film is further deposited, and this is patterned by photolithography, and unlike the first layer wiring 2, it has a pattern shape that is band-shaped in the left and right direction in the figure. A second layer of wiring 4 is formed. If it is necessary to connect wiring 2 and wiring 4,
Contact holes (not shown) were formed in the interlayer insulating film 3 at desired locations to connect the two.
(発明が解決しようとする課題)
上述のような多層配線構造においては、第1層目の配置
!2と第2層目の配線4とが交差する部分においては、
層間絶縁膜3は素子分離領域11a上に形成された配線
2上に着膜されるので、その表面に急峻な高低差を生じ
させる。従って、層間絶縁膜3上に着膜した第2層目の
配線4に段差が生じ、この部分で第3図に示すように、
配a4に断線5が生じやすく半導体の回路機能が停止す
るという問題点があった。(Problem to be Solved by the Invention) In the multilayer wiring structure as described above, the arrangement of the first layer! 2 and the second layer wiring 4 intersect,
Since the interlayer insulating film 3 is deposited on the wiring 2 formed on the element isolation region 11a, a steep height difference is generated on the surface thereof. Therefore, a step is created in the second layer wiring 4 deposited on the interlayer insulating film 3, and as shown in FIG.
There was a problem that the wire breakage 5 was likely to occur in the wiring a4 and the semiconductor circuit function would stop.
本発明は上記実情に鑑みてなされたもので、多層配線構
造を有する半導体装置において、その信頼性の向上が図
れる配線の構造を提供することを目的とする。The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a wiring structure that can improve the reliability of a semiconductor device having a multilayer wiring structure.
(課題を解決するための手段)
上記課題を解消するため本発明に係る半導体装置は、層
間絶縁膜上に配線を形成した半導体装置において、前記
配線上に絶縁層を形成し、該絶縁層上に前記配線と同一
のパターン形状を有するバイパス配線を形成し、配線と
バイパス配線とを前記絶縁層に穿孔されたコンタクト孔
を介して電気的に接続したことを特徴とする。(Means for Solving the Problems) In order to solve the above problems, a semiconductor device according to the present invention includes a semiconductor device in which wiring is formed on an interlayer insulating film, in which an insulating layer is formed on the wiring, and an insulating layer is formed on the insulating layer. The invention is characterized in that a bypass wiring having the same pattern shape as the wiring is formed, and the wiring and the bypass wiring are electrically connected through a contact hole drilled in the insulating layer.
(作用)
本発明によれば、配線と同一のパターン形状を有するバ
イパス配線を形成したので、配線に断線が生じてもバイ
パス配線を介して信号が流れることにより半導体の回路
機能が損なわれることがない。(Function) According to the present invention, since the bypass wiring is formed having the same pattern shape as the wiring, even if a disconnection occurs in the wiring, the circuit function of the semiconductor will not be impaired due to the signal flowing through the bypass wiring. do not have.
(実施例)
本発明の一実施例について図面を参照しながら説明する
。(Example) An example of the present invention will be described with reference to the drawings.
第1図は、本発明の実施例にかかる多層配線構造を有す
る半導体装置の断面説明図である、第2図と同機に、素
子分離領域1aを有するシリコン基板1上にアルミニウ
ム金属等から成る第1層目の配線2が図の表裏方向に帯
状に形成される。配線2上に層間絶縁膜3を着膜し、更
にアルミニウム薄膜を堆積し、これをフォトリソ法によ
りパタニングし第1層目の配線2とは異なるパターン形
状を有する第2層目の配線4が形成されている。FIG. 1 is a cross-sectional explanatory diagram of a semiconductor device having a multilayer wiring structure according to an embodiment of the present invention. The first layer wiring 2 is formed in a band shape in the front and back directions of the figure. An interlayer insulating film 3 is deposited on the wiring 2, an aluminum thin film is further deposited, and this is patterned by photolithography to form a second layer wiring 4 having a pattern shape different from that of the first layer wiring 2. has been done.
第1図中、第2図と同一符号を付した部分は同一構成を
とる。In FIG. 1, parts with the same reference numerals as in FIG. 2 have the same configuration.
第2層目の配線層4上には5tO2を着膜して絶縁層1
1が形成される。この絶縁層11上には前記配線4と同
一のパターン形状を有するバイパス配線12が形成され
ている。配線4とバイパス配線12とは、絶縁層11に
穿孔されたコンタクト孔13を介して電気的に接続して
いる。このコンタクト孔13は、第1図に示すべく、急
峻な段差部4aを挾んでその両側の絶縁層11に形成し
、段差部4aを挟んでその上方側及び下方側の配線4と
、バイパス配線12とが接続できるようにしている。A film of 5tO2 is deposited on the second wiring layer 4 to form an insulating layer 1.
1 is formed. A bypass wiring 12 having the same pattern shape as the wiring 4 is formed on this insulating layer 11. The wiring 4 and the bypass wiring 12 are electrically connected through a contact hole 13 formed in the insulating layer 11. As shown in FIG. 1, the contact hole 13 is formed in the insulating layer 11 on both sides of the steep step 4a, and connects the wiring 4 above and below the step 4a to the bypass wiring. 12 can be connected.
次に、本実施例の半導体装置の製造工程について説明す
る。Next, the manufacturing process of the semiconductor device of this example will be explained.
シリコン基板1上に第1層目の配線21層間絶縁v!3
.第2層目の配線4を順次形成した第2図のような半導
体装置の配線4上の全面に、SiOを着膜して絶縁層1
1を形成する。絶縁層11の所定箇所にコンタクト孔1
3を穿孔する。コンタクト孔13の穿孔は、所定箇所に
開口部を有するレジストパターン(図示せず)を絶縁層
11上に形成した後、異方性エツチングを行い、その後
レジストパターンを除去して形成される。First layer wiring 21 interlayer insulation v! on silicon substrate 1! 3
.. An insulating layer 1 is formed by depositing SiO on the entire surface of the wiring 4 of the semiconductor device as shown in FIG. 2 in which the second layer wiring 4 is sequentially formed.
form 1. A contact hole 1 is formed in a predetermined location of the insulating layer 11.
Drill 3. Contact holes 13 are formed by forming a resist pattern (not shown) having openings at predetermined locations on insulating layer 11, performing anisotropic etching, and then removing the resist pattern.
コンタクト孔13が形成された絶縁層11上にアルミニ
ウムを着膜し、フォトリソ法により前記配線4と同じパ
ターン形状としたバイパス配線12を形成する。A film of aluminum is deposited on the insulating layer 11 in which the contact hole 13 is formed, and a bypass wiring 12 having the same pattern shape as the wiring 4 is formed by photolithography.
従って、断線が生じやすい段差部4aで配線4が切断さ
れても、電気信号は配線4.コンタクト孔13.バイパ
ス配線12.コンタクト孔13配線4と流れ、回路機能
を損なうことがない。Therefore, even if the wiring 4 is cut at the stepped portion 4a where disconnection is likely to occur, the electrical signal will not be transmitted to the wiring 4. Contact hole 13. Bypass wiring 12. The contact hole 13 flows with the wiring 4, so that the circuit function is not impaired.
本実施例では、二層配線について説明したが、三層以上
の多層配線についても適用することができる。In this embodiment, a two-layer wiring has been described, but the present invention can also be applied to a multilayer wiring of three or more layers.
(発明の効果)
上述したように本発明は、配線と同一のバタン形状を有
するバイパス配線を配線に接続して形成したので、配線
に断線が生じてもバイパス配線を迂回して電気信号が流
れ、半導体の回路機能が損なわれることがなく、半導体
の信頼性の向上を図ることができる。(Effects of the Invention) As described above, in the present invention, the bypass wiring having the same button shape as the wiring is connected to the wiring, so even if a disconnection occurs in the wiring, the electrical signal can bypass the bypass wiring and flow. Therefore, the circuit function of the semiconductor is not impaired, and the reliability of the semiconductor can be improved.
第1図は本発明実施例の半導体装置の断面説明図、第2
図は従来の半導体装置の断面説明図、第3図は同上の半
導体装置において断線が生じた場合の断面説明図である
。
・・・・・・シリコン基板
・・・・・・配線
・・・・・・層間絶縁膜
・・・・・・配線
・・・・・・絶縁層
・・・・・・バイパス配線
・・・・・・コンタクト孔FIG. 1 is a cross-sectional explanatory diagram of a semiconductor device according to an embodiment of the present invention, and FIG.
The figure is an explanatory cross-sectional view of a conventional semiconductor device, and FIG. 3 is an explanatory cross-sectional view when a disconnection occurs in the same semiconductor device. ...Silicon substrate...Wiring...Interlayer insulating film...Wiring...Insulating layer...Bypass wiring...・・・Contact hole
Claims (1)
同一のパターン形状を有するバイパス配線を形成し、配
線とバイパス配線とを前記絶縁層に穿孔されたコンタク
ト孔を介して電気的に接続したことを特徴とする半導体
装置。[Scope of Claims] In a semiconductor device in which wiring is formed on an interlayer insulating film, an insulating layer is formed on the wiring, a bypass wiring having the same pattern shape as the wiring is formed on the insulating layer, and the wiring is and a bypass wiring are electrically connected to each other through a contact hole drilled in the insulating layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19900788A JPH0249430A (en) | 1988-08-11 | 1988-08-11 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19900788A JPH0249430A (en) | 1988-08-11 | 1988-08-11 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0249430A true JPH0249430A (en) | 1990-02-19 |
Family
ID=16400556
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19900788A Pending JPH0249430A (en) | 1988-08-11 | 1988-08-11 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0249430A (en) |
-
1988
- 1988-08-11 JP JP19900788A patent/JPH0249430A/en active Pending
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