JPH0249574B2 - RONRIGEETOKAIRO - Google Patents

Description

[Detailed description of the invention]

The present invention relates to logic gate circuits, particularly TTL (transistor-transistor logic). In digital logic circuits, logic gates shown in FIGS. 1a and 1b are often used. These logic gates have two input terminals and one output terminal, and NAND the negation signal of their first input and the second input signal, or the first input signal.
It has an OR function with the negative signal of the second input. That is, if the logic of the first input terminal 1 is A, the logic of the second input terminal 2 is B, and the logic of the output terminal 3 is Y, then the logical formula is Y=〓・
B. In the case of FIG. 1b, Y=A+. Furthermore, the four logic states for the two inputs of these logic gates are as shown in the truth table shown in Table 1. Table 1 Truth Table Input 1 Input 2 Output 3 H L H L L H H H H H L H L Conventionally, the circuit has the above function and the threshold voltage of the circuit is the voltage of two PN junctions (approximately 1.4V ), and a PNP transistor is used in the input stage to reduce the current flowing to the input terminal (hereinafter abbreviated as low-level input current) when the input is at a low level.
The circuit shown in FIG. 2 is well known as a TTL circuit. In the figure, 1 is the first input terminal, 2 is the second input terminal, 3 is the output terminal, 4 is the output part of the inverter circuit 10 which inputs the input terminal 1, 5 is the power supply terminal, 6 is the ground terminal, 20 takes the input terminal 2 and the output 4 of the inverter circuit 10 as inputs.
A NAND circuit is shown. Also, Q ₁ , Q ₂ and Q ₃ are
Q ₄ , Q ₅ , Q ₆ , Q ₇ , Q ₈ and Q ₉ are input stage transistors, intermediate stage transistors and output stage transistors of the inverter circuit 10, respectively.
These are phase-dividing stage transistors and pull-down transistors. Note that here the transistors Q ₁ and Q ₄
As mentioned above, PNP transistors are used to reduce the low-level input current, and all transistors except transistors Q ₁ , Q ₄ and Q ₇ are short-keyed between the base and collector to prevent saturation. Barrier diode (SBD)
NPN clamped at is used. _D1 , _D2
and D ₃ indicate the level shift diode, speed-up SBD, and output level shift diode of the inverter circuit 10, respectively, and D ₄ ,
D ₅ and D ₆ respectively represent a level shift diode, speed up SBD, and input gate SBD of the NAND circuit 20. R ₁ to R ₉ are resistances,
Typical resistance values are shown in Table 2. Table 2 Resistance values of conventional circuits Resistor name Resistance value (kΩ) R ₁ 6 R ₂ 6 R ₃ 4 R 4 ₆ R _{5 4} R ₆ 0.05 R ₇ 5 R ₈ 1.5 R ₉ 3 This circuit is well known. Input 2
When is in a low level state (hereinafter abbreviated as “L”),
Input stage PNP transistors Q ₄ and SBDD ₅ conduct and there is no base drive current for phase-dividing stage transistor Q ₅ and transistor Q ₅ , output stage transistor
_Q8 is in a non-conducting state, on the other hand, off-buffer transistors _Q6 and _Q7 are in an active state, and the output terminal 3 is in a high level state (hereinafter abbreviated as "H"). On the other hand, when input terminal 2 is "H", transistors Q ₄ ,
SBD D ₅ is in a non-conducting state, and the operation of the phase-dividing stage transistor Q is determined by the state of the input terminal 1 and thus of the output 4 of the inverter circuit 10. That is,
In this case, when input terminal 1 is “H”, the input stage
PNP transistor Q ₁ and SBD D ₂ are non-conductive, and level shift diode D ₁ , intermediate stage transistor Q ₂ and output stage transistor Q ₃ are conductive. Therefore, the current flowing through resistor _R4 is diode
D ₄ and SBD D ₆ into the collector of transistor Q ₃ . Therefore, as in the case where the input terminal 2 is "L", the phase division stage transistor Q ₅ and the output stage transistor Q ₈ of the NAND circuit 20 are non-conductive, and the output terminal 3 becomes "H". Conversely, when the input terminal 1 is "L", the PNP transistor Q ₁ and SBD D ₂ are conductive, and the intermediate transistor Q ₂ and the output stage transistor Q ₃ are non-conductive, so that the resistance of the NAND circuit 20
The current flowing through R ₄ passes through diode D ₄ and becomes the base drive current of phase-dividing stage transistor Q ₅ . Therefore, the transistor _Q8 becomes conductive and the output terminal 3 becomes "L". However, in the conventional TTL circuit shown in FIG. 2, when input terminal 2 is "H", the level of the base of phase division stage transistor Q ₅ of NAND circuit 20 changes as the level of input terminal 1 changes. Then, the signal at the input terminal 1 passes through the PNP transistor Q ₁ of the inverter circuit 10, the diode D ₁ transistors Q ₂ and Q ₃ , and the input gate SBD D ₆ of the NAND circuit 20, and a number of other elements to the phase division stage transistor Q. ₅ , which increases the propagation delay time (hereinafter abbreviated as tpd) from input terminal 1 to the base of transistor Q ₅ and eventually to output terminal 3. For example, in the case of the conventional circuit shown in FIG. 2 having resistance values as shown in Table 2,
The turn-on time (hereinafter abbreviated as tpHL) from input terminal 2 to output terminal 3 is 7 ns, and the turn-off time (hereinafter abbreviated as tpLH) is a relatively small value of 8 ns. For up to
Conventional circuits were unsuitable for circuit switching because tpHL was 11ns and tpLH was 14ns. Furthermore, in the conventional circuit shown in FIG. 2, as mentioned above, the tpd from input terminal 1 to the base of phase division stage transistor _Q5 of the NAND circuit 20 is larger than the tPd from input terminal 2 to the base of transistor _Q5 . ,
When input terminals 1 and 2 both change from "L" to "H", output terminal 3 should originally maintain "H", but output section 4 of inverter circuit 10 changes from input terminal 1 to "H".
“H” → “L” according to the change from “L” to “H”
The phase division stage transistor
The base of Q ₅ becomes "H", and the transistor Q ₅ and eventually the output stage transistor Q ₈ are turned on and become "L" during that time. In other words, input terminals 1 and 2 of the conventional circuit shown in FIG.
When both change from “L” to “H”, tpd from input terminal 1 to the base of transistor Q5
[abbreviated as tpdHL (1-Q5B)] is 7ns, input terminal 2
tpd [tpdLH
(2-Q5B)] is 2 ns. At this time
The difference between tpdHL (1-Q5B) and tpdLH (2-Q5B) is
5ns, and “L” is applied to the base of Q5 for this time →
A pulse from “H” to “L” is generated, which causes the minimum response pulse width (3 ns) of the circuit from the base of transistor Q5 to output terminal 3, and the output terminal 3 changes from “H” to “L” to “ An abnormal pulse of "H" is generated. Furthermore, in the conventional TTL circuit, the inverted signal of the input terminal 1 is passed through the phase division stage transistor of the NAND circuit 20.
In order to transmit the Q ₅ 's base, a large number of circuit elements are required: 3 resistors, 4 diodes, and 3 transistors (10 in total), and the power consumption of the circuit is also high. As explained above, it has the same functions as those in Figure 1 a and b, and the threshold voltage of the circuit is the voltage of two stages of PN junctions, and as shown in Figure 2, it uses a PNP transistor in the input stage. conventional
TTL circuits have many drawbacks, including a large tpd of the longest path, a tendency to malfunction due to a difference in tpd from two inputs, a large number of circuit elements, and high power consumption. The present invention has been made in view of the above circumstances, and provides a logic system that improves the TPD of the circuit, the difference in propagation delay time from two input terminals, the number of circuit elements, and power consumption, and that requires less low-level input current. The purpose is to provide gate circuits. According to the present invention, a first input gate circuit includes a first PNP transistor having a base connected to a first input terminal, a collector connected to a ground terminal, and an emitter connected to a power supply terminal via a first resistor; 1
The base is connected to the output of the input gate circuit.
an inverter circuit consisting of a first output circuit including a 1NPN transistor; and a second inverter circuit including a second PNP transistor having a base connected to a second input, a collector connected to a ground terminal, and an emitter connected to a power supply terminal via a second resistor. An input gate circuit with a collector connected to the output terminal and an emitter connected to the ground terminal.
a second output circuit including a 2NPN transistor, an emitter connected to the base of the second NPN transistor, a collector connected to a power supply terminal via a third resistor, and a base connected to the output of the second input gate circuit and the inverter circuit; the second connected to the output of
In a logic gate circuit composed of a NAND circuit consisting of a phase division stage circuit including a 3NPN transistor, when the first input terminal is at a high level and the second input terminal is at a low level, a current flows to the second input terminal. In order to reduce this, there is obtained a logic gate circuit characterized in that a diode is added whose anode is connected to the emitter of the first PNP transistor of the inverter circuit and whose cathode is connected to the emitter of the second PNP transistor of the NAND circuit. The circuit of the present invention will be explained in detail below with reference to the drawings. FIG. 3 is a circuit connection diagram showing an embodiment of the circuit of the present invention. The difference from the conventional circuit shown in FIG. 2 is the output level shift diode D ₃ and the output stage transistor Q ₃ of the inverter circuit 10 of the conventional circuit. ，
Pull-up resistor R ₂ at the collector of intermediate stage transistor Q ₂ , base charge extraction resistor R ₃ of transistor Q ₃ and input gate of NAND circuit 20
Instead of removing SBD D ₆ , inverter circuit 1
A PN junction diode _D7 is connected between the emitter of the output stage transistor _Q2 and the ground terminal 6, and a PNP transistor whose base is connected to the first input terminal.
The reason is that a diode _D6 is inserted between the emitter of _Q1 and the emitter of PNP transistor _Q2 whose base is connected to the second input terminal. Diode D ₇ sets the threshold voltage of inverter circuit 10
It is a level shift diode to maintain the voltage of two stages of PN junction forward voltage, and also a diode.
For _D8 , input terminal 1 is “H” and input terminal 2 is “L”
In order to prevent the current flowing through the resistor R ₁ of the inverter circuit 10 from flowing out to the input terminal 2 through the diode D ₁ , the base-collector junction clamp SBD of the transistor Q ₂ , and the SBD D ₅ of the NAND circuit 20 when It will become clear from the following description that this is a diode. In Fig. 3, the elements that function in the same way as the conventional circuit are as follows:
The same symbols as in Figure 2 are given. However, transistor Q2 of the inverter circuit ₁₀ works as an intermediate stage transistor in the conventional circuit shown in FIG. 2, but in the circuit of the present invention shown in FIG.
Since the collector of Q ₂ becomes the output section of the inverter circuit 10, the transistor Q ₂ in FIG. 3 is called an output stage transistor. Further, typical values of each resistance are shown in Table 3. Table 3 Resistance values of the circuit of the present invention Resistance name Resistance value (kΩ) R ₁ 6 R ₄ 6 R ₅ 4 R ₆ 0.05 R ₇ 5 R ₈ 1.5 R ₉ 3 The operation of the circuit of the present invention will be described below. First, when input terminal 2 is “L”, the input
PNP transistor Q ₄ and SBD D ₅ conduct and the base potential of phase-dividing stage transistor Q ₅ , V _BQ5 , is
Regardless of the state of input terminal 1, V _BQ5 = V _IL2 + V _FD5 (1). However, V _IL2 and V _FD5 are input terminal 2, respectively.
Low level input voltage, SBD D ₅ indicates forward voltage. Normally V _FD5 is around 0.45V, and below 0.8V
For V _IL2 , V _BQ5 is approximately 1.25V or less, and phase divider stage transistor Q ₅ and output stage transistor Q ₈
The voltage is lower than the voltage (approximately 1.4 V) required to make the transistors conductive, transistors Q ₅ and Q ₈ become non-conductive, and the output terminal 3 becomes "H". Next, the case where input terminal 2 is "H" will be described. In this case the input PNP transistor Q ₄ , SBD
D ₅ is non-conducting, and the operation of the phase-dividing stage transistor Q ₅ is based on the input terminal 1 and hence the inverter circuit 10.
Determined by the state of the output section. That is, input terminal 1
When is “H”, PNP transistor _Q1 and
SBD D ₂ becomes non-conductive, and diode D ₁ and intermediate stage transistor Q ₂ become conductive. At this time, if the forward voltage of the level shift diode _D7 of the inverter circuit 10 is V _FD7 , and the collector-emitter voltage in the conductive state of the transistor _Q2 is V _CEQ2 , then
The collector potential of transistor Q ₂ V _CQ2 and hence
The base potential V _BQ5 of the phase division stage transistor Q ₅ of the NAND circuit 20 is V _BQ5 (V _CQ2 )=V _FD7 +V _CEQ2 (2). Normally V _FD7 and V _CEQ2 are approximately 0.7V, respectively.
Since it is 0.3V, substituting this value into equation (2) gives V _BQ5
becomes about 1.0V, transistors Q ₅ and Q ₈ become non-conductive, and the output terminal 3 becomes "H". Furthermore, input terminal 1 is “L” and input terminal 2 is “H”
When , the input PNP transistors Q ₁ and SBD D ₂ of the inverter circuit 10 are conductive, and conversely, the transistor Q ₂ is non-conductive, so the current flowing through the resistor R ₄ and the diode D ₄ of the NAND circuit 20 is phase-divided. The base of stage transistor Q ₅ is driven, and transistor Q ₅ and output stage transistor Q ₈ become conductive.
Therefore, in this case, the output terminal 3 becomes "L". From the above explanation, the circuit of the present invention has input terminals 1 and 2.
It can be seen that the logical operations shown in Table 1 are performed for all combinations. Next, the operation of diode _D8 , which is a feature of the circuit of the present invention, will be explained. Generally, a PNP transistor is used in the input stage to reduce the low-level input current and increase the fanout connected to the previous stage. However, in the circuit shown in Figure 3, if diode _D8 is not connected, input terminal 1 is "H",
When input terminal 2 is “L”, the low level input current I _IL2 flowing to input terminal 2 is I _IL2 = V _CC −V _FD1 −V _FSBDQ2 −V _FD5 −V _IL2 /R ₁
+V _CC -V _BEQ4 -V _IL2 /(1+βQ ₄ )·R ₄ (3) However, the meaning and typical values of each signal in the above equation are shown below.

[Table] Current amplification factor
Substituting the above typical values into equation (3), the first term on the right side becomes 500 μA and the second term 60 μA, and I _IL2 is almost dominated by the first term on the right side, and I _IL2 is 560 μA.
This greatly exceeds the standard low-level input current of 400μA for general low-power shot key TTL. However, according to the circuit of the present invention in which the diode _D8 is connected, when the input terminal 1 is "H" and the input terminal 2 is "L", the diode _D8 conducts, so that the current flowing through the resistor _R1 flows through the diode D. ₈ and flows through the emitter-collector of the conductive PNP transistor Q ₄ to the ground terminal 6, and hardly flows to the input terminal 2. That is, in this case, the low level input current I _IL2 of input terminal 2 is I _IL2 = V _CC −V _FD8 −V _BEQ4 −V _IL2 /(1+βQ ₄
)・R ₁ +V _CC −V _BEQ4 −V _IL2 /(1+βQ ₄ )・R ₄ …(4)
becomes. However, here, V _FD8 is the forward voltage of diode D ₈ , and when diode D ₈ is a PN junction diode, it is approximately 0.7V. Therefore, this value
Substituting into equation (4), the first term on the right side becomes approximately 50 μA, the second term approximately 60 μA, and _IIL2 becomes approximately 110 μA. This value is only about 1/5 of I _IL2 (approximately 560 μA) when diode D ₈ is not connected, and it can be seen that I _IL2 is significantly reduced due to the effect of diode D ₈ . Next, the propagation delay time (tpd) of the circuit of the present invention will be described. As previously explained, the signal at input terminal 1 is transmitted to the base of phase division stage transistor _Q5 of NAND circuit 20 only when input terminal 2 is "H", but in the case of the conventional circuit shown in FIG. ,
The input signal applied to the input terminal 1 passes through the input PNP transistor Q ₁ of the inverter circuit ₁₀ , the level shift diode D ₁ , the intermediate stage transistor Q ₂ , Output stage transistor Q ₃ and input gate SBD D ₆ of NAND circuit 20, total 5
The signal needs to propagate through two elements, and the propagation delay time from input terminal 1 to output terminal 3 is tpdLH
was 14ns, and tpdHL was 11ns, which were large values.
However, for tpdLH, output terminal 3 changes from “L” to “H”
tpdHL indicates tpd when changing from "H" to "L". On the other hand, in the circuit of the present invention, between the input terminal 1 and the base of the phase division stage transistor _Q5 ,
Input PNP transistor Q ₁ of the inverter circuit 10,
It requires only three elements, the level shift diode _D1 and the output stage transistor _Q2, and is advantageous for speeding up the circuit. In other words, in the case of the circuit of the present invention shown in FIG. 3 with resistance values as shown in Table 3, the propagation delay time from input terminal 1 to output terminal 3 is 10 ns for tpdLH and 8 ns for tpdHL.
, and the tpd is greatly improved compared to the conventional circuit. In addition, in the case of the circuit of the present invention, since tpd from input terminal 1 is small, there is almost no difference between tpd from input terminal 1 and tpd from input terminal 2, and input terminals 1 and 2 are both "L" →
When changing to "H", the abnormal phenomenon that occurs in the conventional circuit where the output terminal 3 changes from "H" to "L" to "H" does not occur at all. That is, when both input terminals 1 and 2 of the circuit of the present invention change from "L" to "H", tpd [tpdHL(1-
Q5B)] is 3 ns, and tpd (abbreviated as tpdLH (2-Q5B)) from input terminal 2 to the base of transistor Q5 is 2 ns. At this time, tpdHL(1−Q5B)
The difference between and tpdLH(2-Q5B) is only 1ns,
The value is less than the minimum response pulse width (3 ns) of the circuit from the base of transistor Q5 to output terminal 3.
Therefore, no abnormal phenomenon occurs at the output terminal 3. Furthermore, the circuit of the present invention improves the average power consumption of the entire circuit by about 20% compared to the conventional circuit. In the above explanation, the input PNP transistors Q ₁ and Q ₄ and the off-buffer downstream transistor are
We have described the case of transistors in which the base-collector of all transistors except _Q7 are SBD clamped, but by performing gold diffusion, it can also be applied to a circuit configured with transistors that do not have the base-collector clamped with SBD. It goes without saying that the circuit of the present invention is applicable. Further, the diode _D8 is not limited to a PN junction diode, but the same effect can be obtained even if it is a Schottky barrier diode. As described above, according to the present invention, it is possible to obtain a logic gate circuit with a small circuit propagation delay time, a small difference in propagation delay time from two input terminals, and a small circuit power consumption, and a small number of circuit elements. I can do it.

[Brief explanation of drawings]

1a and 1b are block diagrams of a digital logic gate to which the present invention is applied, and FIG. 2 is a block diagram of a conventional digital logic gate.
A circuit diagram showing a typical example of TTL, Figure 3 is the invention of the present invention.
A circuit connection diagram showing a typical example of TTL is shown. Explanation of symbols R ₁ to _{R 9} ... Resistor, Q ₁ to Q ₉ ... Transistor, D ₁ to _{D 8} ... Diode, 1, 2...
... Input terminal, 3 ... Output terminal, 4 ... Output part of inverter circuit 10, 5 ... Power supply terminal, 6 ... Ground terminal, 10 ... Inverter circuit, 20 ...
NAND circuit.

Claims (1)

[Claims] 1. A first input gate including a first PNP transistor whose base is connected to a first input terminal, whose collector is connected to a ground terminal, and whose emitter is connected to a power supply terminal via a first resistor, and whose output is the emitter of the first PNP transistor. a first diode having an anode connected to the output of the first input gate circuit; and a first diode having a base connected to the cathode of the first diode and an emitter connected to the anode of the second diode.
an inverter circuit consisting of a first output circuit including a 1NPN transistor, with the collector of the first NPN transistor as an output and the cathode of the second diode connected to a ground terminal; and a base connected to a second input terminal.
A second PNP whose collector is connected to the ground terminal and whose emitter is connected to the power supply terminal via a second resistor.
a second input gate circuit including a transistor and having an emitter of the second PNP transistor as an output; a second output circuit including a second NPN transistor having an emitter connected to a ground terminal; a base of the second NPN transistor having an emitter connected to the collector; is connected to the power supply terminal via a third resistor, and includes a third NPN transistor whose base is connected to the output of the inverter circuit and the anode of a third diode, and the cathode of the third diode is connected to the second input terminal. and a fourth diode, the anode of which is connected to the output of the second input gate circuit, and the cathode of which is connected to the base of the third NPN transistor.
In a logic gate circuit having a collector of a 2NPN transistor as an output terminal, an anode is connected to an emitter of a first PNP transistor of the inverter circuit;
A logic gate circuit comprising a fifth diode whose cathode is connected to the emitter of a second PNP transistor of a NAND circuit.