JPH0249732Y2 - - Google Patents

Info

Publication number
JPH0249732Y2
JPH0249732Y2 JP1982069197U JP6919782U JPH0249732Y2 JP H0249732 Y2 JPH0249732 Y2 JP H0249732Y2 JP 1982069197 U JP1982069197 U JP 1982069197U JP 6919782 U JP6919782 U JP 6919782U JP H0249732 Y2 JPH0249732 Y2 JP H0249732Y2
Authority
JP
Japan
Prior art keywords
semiconductor layer
semiconductor
diode
pellets
conductivity type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1982069197U
Other languages
Japanese (ja)
Other versions
JPS58173249U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1982069197U priority Critical patent/JPS58173249U/en
Publication of JPS58173249U publication Critical patent/JPS58173249U/en
Application granted granted Critical
Publication of JPH0249732Y2 publication Critical patent/JPH0249732Y2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/30Die-attach connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings

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  • Electrodes Of Semiconductors (AREA)

Description

【考案の詳細な説明】 本考案は、高圧ダイオードを形成する半導体ペ
レツトの構造に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of semiconductor pellets forming high voltage diodes.

従来の高圧ダイオードは一般に第1図に示すよ
うな構造である。すなわち、第1図に示されるよ
うに約千〜千数百Vの逆耐電圧を有するダイオー
ドペレツト1を複数個、この場合は3個直列に接
続して、ダイオードの逆耐電圧も約3千V以上と
している。また、5a,5bは、外部引出しリー
ドを有するヒートシンクでありダイオードペレツ
トと熱膨張係数の近いタングステンまたはモリブ
デン等で形成されており6はダイオードペレツト
を外部から電気的、機械的に保護するための封止
ガラスであり、ヒートシンクと同様にダイオード
ペレツトと熱膨張係数の近い硼ケイ酸ガラスで形
成されており、2はダイオードペレツト上に形成
された2酸化シリコンであり、3はダイオードペ
レツトのPN接合端部を保護するパツシベーシヨ
ンガラスであり、4はダイオードペレツト同志お
よびヒートシンクを接続するための接続メタルで
ある。
A conventional high voltage diode generally has a structure as shown in FIG. That is, as shown in FIG. 1, a plurality of diode pellets 1, in this case three, each having a reverse withstand voltage of about 1000 to 1000s of hundreds of volts are connected in series, so that the reverse withstand voltage of the diode is also about 3. It is said to be over 1,000V. Further, 5a and 5b are heat sinks having external leads, and are made of tungsten or molybdenum, etc., which have a coefficient of thermal expansion similar to that of the diode pellet, and 6 is for electrically and mechanically protecting the diode pellet from the outside. 2 is silicon dioxide formed on the diode pellet, and 3 is the sealing glass formed on the diode pellet. 4 is a passivation glass that protects the PN junction end of the plate, and 4 is a connecting metal for connecting the diode pellets and the heat sink.

次に組立工程を説明する。 Next, the assembly process will be explained.

第1に所望の逆電圧を満足する数のダイオード
ペレツト1を積層し、さらに上下にヒートシンク
5a,5bをおき、接続メタルとダイオードペレ
ツト1のシリコンとの共晶温度以上に温度を上
げ、ダイオードペレツト同志間および端部にヒー
トシンクを接続するマウント工程、第2にダイオ
ードペレツトを外部から電気的,機械的に保護す
るために封止ガラス6により封止する封止工程か
らなる。
First, a number of diode pellets 1 that satisfy the desired reverse voltage are stacked, heat sinks 5a and 5b are placed above and below, and the temperature is raised to a temperature higher than the eutectic temperature of the connecting metal and the silicon of the diode pellets 1. This process consists of a mounting process in which a heat sink is connected between the diode pellets and at their ends, and a second sealing process in which the diode pellets are sealed with a sealing glass 6 to electrically and mechanically protect them from the outside.

ここで第1図に示すように、従来のダイオード
ペレツト1は片主表面に2酸化シリコンを有して
いた。接続メタルは2酸化シリコンとは接着しな
いため2酸化シリコンの膜厚よりも厚くしなけれ
ば接続されなかつた。また該ペレツトの製造工程
で詳細に説明するが、パツシベーシヨンガラス3
を形成する時に、この2酸化シリコン上にも酸化
膜のピンホールやゴミ等の形成核のために極部的
にパツシベーシヨンガラスが形成されてしまうこ
とがあり、この場合この凸部のために接続面の平
行度が悪くなり隙間を生じ接続メタルの接着強度
が低下したり熱度疲労を生じるという不具合があ
つた。
As shown in FIG. 1, a conventional diode pellet 1 had silicon dioxide on one main surface. Since the connection metal does not adhere to silicon dioxide, the film must be thicker than the silicon dioxide for connection to occur. Also, as will be explained in detail in the manufacturing process of the pellets, the packaging glass 3
When forming silicon dioxide, passivation glass may be formed locally on this silicon dioxide due to formation nuclei such as pinholes and dust in the oxide film, and in this case, passivation glass may be formed locally on this silicon dioxide. As a result, the parallelism of the connecting surfaces deteriorates, creating gaps, resulting in problems such as a decrease in the adhesive strength of the connecting metals and thermal fatigue.

本考案は、かかる不具合を排除し、信頼性の高
い高圧ダイオードを得るためのダイオードペレツ
トの構造に関するものである。
The present invention relates to a diode pellet structure for eliminating such defects and obtaining a highly reliable high voltage diode.

本考案によれば、メサ型の半導体ペレツトが複
数個積層された高圧ダイオードにおいて、該半導
体ペレツトは、一導電型の半導体基板と、前記半
導体基板の一主面の中央部上に設けられた前記一
導電型の第1の半導体層と、前記第1の半導体層
上に設けられた他の導電型の第2の半導体層と、
前記第2の半導体層の表面の中央部上に設けられ
た前記他の導電型の第3の半導体層と、前記第2
の半導体層の前記表面の周辺部、前記第2の半導
体層の側面、前記第1の半導体層の側面及び前記
半導体基板の前記一主面の周辺部を覆つて設けら
れ、前記第3の半導体層よりも薄い膜厚を有する
パツシベーシヨン膜と、前記第3の半導体層上の
全面に前記第3の半導体層と直接接して設けられ
た接続金属とを有して形成されていることを特徴
とする高圧ダイオードが得られる。
According to the present invention, in a high-voltage diode in which a plurality of mesa-shaped semiconductor pellets are stacked, the semiconductor pellets include a semiconductor substrate of one conductivity type, and a semiconductor pellet provided on the central portion of one principal surface of the semiconductor substrate. a first semiconductor layer of one conductivity type; a second semiconductor layer of another conductivity type provided on the first semiconductor layer;
the third semiconductor layer of the other conductivity type provided on the center of the surface of the second semiconductor layer;
The third semiconductor layer is provided to cover a peripheral portion of the front surface of the semiconductor layer, a side surface of the second semiconductor layer, a side surface of the first semiconductor layer, and a peripheral portion of the one principal surface of the semiconductor substrate. A passivation film having a thickness thinner than that of the third semiconductor layer, and a connection metal provided on the entire surface of the third semiconductor layer in direct contact with the third semiconductor layer. A high voltage diode is obtained.

以下、図面により詳細に説明する。 A detailed explanation will be given below with reference to the drawings.

第2図5は従来のダイオードペレツトであり第
2図a〜e工程により製造される。第2図aは両
面に2酸化シリコンを有するPN接合形成済ウエ
ハを写真触刻法により各チツプに分離するための
溝形成部の2酸化シリコン膜を除去したものであ
る。
FIG. 25 shows a conventional diode pellet, which is manufactured by the steps a to e in FIG. 2. FIG. 2a shows a wafer with silicon dioxide formed on both sides, on which PN junctions have been formed, after which the silicon dioxide film in the groove-forming portions for separating each chip into chips has been removed by photolithography.

次に第2図bのごとく、硝酸と弗酸の混合シリ
コンエツチン液により2酸化シリコン膜をマスク
としてPN接合を分離すべくPN接合深さより深
く溝7を形成する。
Next, as shown in FIG. 2b, a trench 7 is formed deeper than the depth of the PN junction in order to separate the PN junction using a silicon dioxide film as a mask using a mixed silicon etching solution of nitric acid and hydrofluoric acid.

次に第2図cのごとく、ウエハをパツシベーシ
ヨンガラスの粉末を溶媒に懸濁させた液に浸漬
し、電界をかけ電気泳動法により2酸化シリコン
をマスクとしてパツシベーシヨンガラス粉末を溝
部のシリコン露出部のみに形成し、電気炉に入れ
粉末ガラスを溶融しパツシベーシヨンガラス膜3
を形成する。
Next, as shown in Figure 2c, the wafer is immersed in a solution in which passivation glass powder is suspended in a solvent, an electric field is applied, and the passivation glass powder is separated by electrophoresis using silicon dioxide as a mask. A passivation glass film 3 is formed only on the exposed silicon part of the groove and melted the powdered glass in an electric furnace.
form.

次に第2図dのごとく接続メタル形成個所の2
酸化シリコンを写真蝕刻法により除去し、第2図
eのごとく該部と裏面全面に接続メタルを蒸着法
により形成する。
Next, as shown in Figure 2 d, the connecting metal is formed at 2.
The silicon oxide is removed by photolithography, and a connecting metal is formed on this portion and the entire back surface by vapor deposition as shown in FIG. 2e.

次にウエハの溝中央部にレーザーまたはダイサ
ースクライブにより刻み目を入れ個々のペレツト
に分離しダイオードペレツト5を得ていた。
Next, a notch was made in the center of the groove of the wafer using a laser or a dicer scribe, and the pellet was separated into individual pellets to obtain diode pellets 5.

以上のごとく、従来の構造においては、接続メ
タルと2酸化シリコンが同一面上に存在するた
め、また第2図cの工程において2酸化シリコン
のピンホール、微細な2酸化シリコン表面の凹
凸、2酸化シリコン上のゴミ等により2酸化シリ
コン上にも極部的にパツシベーシヨンガラスが形
成されしまうという不具合が最終ペレツトにその
まま残つてしまいダイオードの組立工程で前述の
ごとき不具合を生じていた。
As described above, in the conventional structure, since the connection metal and the silicon dioxide exist on the same surface, and in the process shown in FIG. The defect that passivation glass is formed locally on the silicon dioxide due to dust on the silicon oxide remains as it is in the final pellet, causing the above-mentioned defect in the diode assembly process.

第4図a〜hにより本考案を説明する。第4図
aは従来の工程と同じであり、次に第4図bにお
いて所望する深さよりも浅く(第4図eにおいて
て形成するパツシベーシヨンガラス3の厚さより
少し厚い分だけ)溝を形成する。次に第4図cの
ごとく、写真蝕刻法により2酸化シリコン2aを
該2酸化シリコン下のP拡散層の表面積より小さ
く形成するため不用の2酸化シリコンを除去す
る。次に第4図dのごとく再度溝部をエツチング
し所望の深さの溝部を形成する。この時に追加さ
れた溝深さの分の段差8が形成される。該段差の
深さは前述の理由により次に形成されるパツシベ
ーシヨン膜厚よりも大きくなる。次に第4図eの
ごとく従来方法と同様にパツシベーシヨンガラス
3を形成する。この時段差部に形成されたパツシ
ベーシヨンガラス3は前述の理由によりP拡散層
の表面よりも低く形成される。次に第4図fのご
とく、写真蝕刻法により2酸化シリコンのすべて
と段差中央部から内側の部分のパツシベーシヨン
ガラスをも除去し、第4図gのごとく該部と裏面
全面に蒸着法により接続メタルを形成する。
The present invention will be explained with reference to FIGS. 4a to 4h. 4a is the same as the conventional process, and then, in FIG. 4b, the groove is made shallower than the desired depth (slightly thicker than the thickness of the passivation glass 3 formed in FIG. 4e). form. Next, as shown in FIG. 4c, unnecessary silicon dioxide is removed by photolithography to form silicon dioxide 2a smaller in surface area than the P diffusion layer under the silicon dioxide. Next, as shown in FIG. 4d, the groove is etched again to form a groove of a desired depth. A step 8 corresponding to the groove depth added at this time is formed. The depth of the step is larger than the thickness of the passivation film to be formed next for the reason mentioned above. Next, as shown in FIG. 4e, a passivation glass 3 is formed in the same manner as in the conventional method. At this time, the passivation glass 3 formed in the stepped portion is formed lower than the surface of the P diffusion layer for the reason described above. Next, as shown in Figure 4 f, all of the silicon dioxide and the passivation glass in the inner part from the center of the step are removed by photolithography, and vapor deposition is carried out on this area and the entire back surface as shown in Figure 4 g. The connecting metal is formed by the method.

次に従来と同様に溝中央部にレーザーまたはダ
イオースクライブにより刻み目を入れ個々のペレ
ツトに分離し第4図hに示すダイオードペレツト
を得る。
Next, in the same manner as in the prior art, a notch is made in the center of the groove by a laser or diode scribe, and the pellets are separated into individual pellets to obtain the diode pellets shown in FIG. 4h.

以上のごとく、本考案によるダイオードペレツ
トを用いることにより第3図のようにダイオード
ペレツトの主表面すなわち接着面には2酸化シリ
コンが存在せず、接着面はシリコンサブストレー
トのみであり、またパツシベーシヨンガラスもシ
リコン接着面よりも低いため、従来の高圧ダイオ
ードに生じていた前述のごとき不具合は発生せ
ず、信頼性の高い高圧ダイオードを得ることがで
きる。
As described above, by using the diode pellet of the present invention, silicon dioxide does not exist on the main surface of the diode pellet, that is, the adhesive surface, as shown in FIG. 3, and the adhesive surface is only the silicon substrate. Since the passivation glass is also lower than the silicon bonding surface, the above-mentioned problems that occur in conventional high-voltage diodes do not occur, and a highly reliable high-voltage diode can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の高圧ダイオードの断面図であ
り、第2図a〜fは該ダイオードペレツトの製造
工程を示す断面図である。第3図は本考案による
高圧ダイオードの断面図であり、第4図a〜hは
該ダイオードペレツトの製造工程を示す断面図で
ある。 なお、図において、1……ダイオードペレツ
ト、2a,2b……2酸化シリコン、3……パツ
シベーシヨンガラス膜、4……接続メタル、5
a,5b……ヒートシンク、6……封止ガラス、
7……PN接合分離溝、8……PN接合分離溝段
差、である。
FIG. 1 is a sectional view of a conventional high voltage diode, and FIGS. 2a to 2f are sectional views showing the manufacturing process of the diode pellet. FIG. 3 is a sectional view of a high voltage diode according to the present invention, and FIGS. 4a to 4h are sectional views showing the manufacturing process of the diode pellet. In the figure, 1... diode pellet, 2a, 2b... silicon dioxide, 3... passivation glass film, 4... connection metal, 5
a, 5b...heat sink, 6...sealing glass,
7...PN junction separation groove, 8...PN junction separation groove step.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] メサ型の半導体ペレツトが複数個積層された高
圧ダイオードにおいて、該半導体ペレツトは、一
導電型の半導体基板と、前記半導体基板の一主面
の中央部上に設けられた前記一導電型の第1の半
導体層と、前記第1の半導体層上に設けられた他
の導電型の第2の半導体層と、前記第2の半導体
層の表面の中央部上に設けられた前記他の導電型
の第3の半導体層と、前記第2の半導体層の前記
表面の周辺部、前記第2の半導体層の側面、前記
第1の半導体層の側面及び前記半導体基板の前記
一主面の周辺部を覆つて設けられ、前記第3の半
導体層よりも薄い膜厚を有するパツシベーシヨン
膜と、前記第3の半導体層上の全面に前記第3の
半導体層と直接接して設けられた接続金属とを有
して形成されていることを特徴とする高圧ダイオ
ード。
In a high-voltage diode in which a plurality of mesa-shaped semiconductor pellets are stacked, the semiconductor pellets include a semiconductor substrate of one conductivity type, and a first semiconductor pellet of one conductivity type provided on the center of one principal surface of the semiconductor substrate. a second semiconductor layer of another conductivity type provided on the first semiconductor layer, and a second semiconductor layer of the other conductivity type provided on the center portion of the surface of the second semiconductor layer. a third semiconductor layer, a peripheral portion of the front surface of the second semiconductor layer, a side surface of the second semiconductor layer, a side surface of the first semiconductor layer, and a peripheral portion of the one principal surface of the semiconductor substrate; A passivation film is provided to cover the third semiconductor layer and has a thickness thinner than the third semiconductor layer, and a connection metal is provided on the entire surface of the third semiconductor layer in direct contact with the third semiconductor layer. A high voltage diode characterized by being formed as follows.
JP1982069197U 1982-05-12 1982-05-12 high voltage diode Granted JPS58173249U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1982069197U JPS58173249U (en) 1982-05-12 1982-05-12 high voltage diode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1982069197U JPS58173249U (en) 1982-05-12 1982-05-12 high voltage diode

Publications (2)

Publication Number Publication Date
JPS58173249U JPS58173249U (en) 1983-11-19
JPH0249732Y2 true JPH0249732Y2 (en) 1990-12-27

Family

ID=30078934

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1982069197U Granted JPS58173249U (en) 1982-05-12 1982-05-12 high voltage diode

Country Status (1)

Country Link
JP (1) JPS58173249U (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5557571B2 (en) * 2010-03-29 2014-07-23 新電元工業株式会社 Diode module
US8530902B2 (en) * 2011-10-26 2013-09-10 General Electric Company System for transient voltage suppressors

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4995585A (en) * 1973-01-12 1974-09-10
JPS5832507B2 (en) * 1975-05-16 1983-07-13 三菱電機株式会社 Manufacturing method of semiconductor device
JPS5827347B2 (en) * 1975-08-26 1983-06-08 カブシキガイシヤ カタヤマカガクコウギヨウケンキユウシヨ The first year of the year
US4047196A (en) * 1976-08-24 1977-09-06 Rca Corporation High voltage semiconductor device having a novel edge contour

Also Published As

Publication number Publication date
JPS58173249U (en) 1983-11-19

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