JPH02500780A - display processor - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] This invention provides improvements that can be used to provide computer-generated displays. The present invention relates to a display processor.

Graphic images used in computer-generated displays are A video that maps each point along a rask scan of the display video space at regular intervals. Stored at address location in memory. Each addressed location in video memory is Contains digital words, at least some of which are in visual space. color pixels (continuous running encoding) of corresponding points in the In the configuration, the luminance, hue, and saturation of consecutive pixel values are encoded. Do).

Traditionally, there are many different ways to encode the brightness, hue, and saturation of color pixels. There is a method.

For example, the color pixel is the sum of the three primary colors of additive color mixture, i.e., red, green, and blue. Each red, green, and blue component signal that may be analyzed is encoded into n bits.

Generally, n is in the range of 5 to 8 (including 5 and 8). Coding is linear, logarithmic or according to some other function. red, green, and blue for these brightness It is also known to linearly encode different numbers p, q, r of bits based on their contribution. ing. An example of such encoding is 7 bits for green and 5 bits for red. Coat blue to 4 bits. Code the additive 3M colors into different numbers of bits For comprehensive processing of D (PROCEEDINGS 0FTHE 5ID), Vol, 26/2, 1 Mr. Cowlishaw (M, published on pages 101 to 107 of 985) F. Cowlishaw's paper “Fundamental conditions for imaging shallow water (Funda sental Require -5ents for Picture Pr estation) J.

Each color pixel is divided into a luminance-only primary and two luminance-only primaries. The primary color of only chrominance, which represents the whiteness of the cell, that is, the brightness, is actually does not correspond to any color, and together represents the difference between the actual color and the luminance-only primary color, In order to avoid quantization errors when adding the primary colors, the chrominance The number of bits in the primary color of only luminance is usually the same as the number of bits of the primary color of luminance only. The fewer the number of bits in a chrominance-only primary color, the lower the quality of the display. cause it to drop.

Arbitrary color values as addresses in a memory called colormap memory. This memory responds to these addresses by providing read outputs and and provides a drive signal to a color display device that produces the desired color to be displayed. Ru. Although memory operates as read-only memory, it It is equipped with a device for changing the color map used. Easily change color maps These memories have electrically erasable readout to enable It may be a dedicated memory or a random access memory.

Computer display systems allow compatibility between various video processing modes It is desirable to use computer-generated video as a component, thereby It is possible to create a composite display consisting of both images produced by child A problem that arises when trying to create a video display processor such as A pixel in camera-generated video is represented by a code that is 24 bits long. , such a pixel code represents the pixel of the graphic image being displayed on a computer-generated The problem is that the code is considerably longer in terms of bits than the code normally used for be.

<Summary of the invention> A display processor embodying the present invention includes first, second and third color map media. The 0 display using memory is provided from the output of three color map memories. generated from the three primary colors supplied. Bixel data is in pixel format. coded into several bit words per pixel, This few bits are reduced to fewer bit words per pixel format. By incrementing any originally coded pixel data with 0 Given. The address for the first colormap is the first of several bit words. generated from a selected portion of 1. How many addresses are there for the second color map? from a second selected portion of the bit word. third color pine The address for each bit word is generated from the third selected portion of each several bit word. It will be done. one of the first, second and third selected parts of each several bit word means are provided to make one different from the other at least part of the time .

In the attached drawings, 1, 2 and 3 are block diagrams of embodiments of a display processor including the present invention. Figure.

Figures 4, 5 and 6 show the pixel data possible with the display processor of Figure 2. A diagram showing the data formatting configuration, Figures 7, 8, 9 and 10 illustrate the visual effects possible with the display processor of Figure 3. Diagram illustrating cell data formatting configuration, 11 and 12 are blocks of a modified display processor including the present invention. figure, FIG. 13 shows the devices shown in FIGS. 1 and 2 arranged to operate in parallel or banked operation. A block of two display processors of the form of FIG. 3, FIG. 11 or FIG. Figure 14 is a display screen of Figure 1, Figure 2, Figure 3, Figure 11 or Figure 12. FIG. 2 is a block diagram of a display device that can be used with a processor.

The display processor in Figure 1 is a data storage device using disks or tapes. , digital random access memory (RAM), conventional data processing A small scale meter equipped with graphical acumen as well as a plotter, plot processor, and display device. A drawing processor is a data storage device that can be used to configure a calculator. Processes the graphical information supplied by the image data display processor. R indexed into the video storage device so that it is stored in a format convenient for The video data written to the AM part is organized in a bitmap format (bitmap format). ganization) and stored in RAM. i.e. displayed by the display device. For each component of the description of a pixel (vixel) in the image to be stored, each component is stored in memory. A location is provided. During the readout of the RAM image storage location, these Memory locations are addressed in rask scan order synchronized with the scan of the display screen. and provides pixel data to the display processor. RAM stores graphic information In addition to storing data for processing in a general data processor You can also do that. RAM is also used for general data processors, plot processors, and and/or store operational instructions for the display processor of FIG. Some of the RAM The intended usage is common to small computers, and this RAM will be referred to as the "computer main memory" below. It is called.

In the display processor of FIG. receive each description of the file. These words are bit mapped with respect to the stored video. selected from data supplied from the computer's main memory, which is organized into blocks. preferable The structure of computer main memory is video dynamic random access memory ( VRAM) uses integrated circuits. Such a circuit is a common random It is a dual port with an additional serial output port in addition to the access input/output port. Ru. This serial output port provides video access in the time required for regular random access. ・Side load the shift register with a complete line of samples. At the end. Once loaded, the shift register is accessed via regular random access. high speeds to transmit lines of video samples much faster than can be obtained clocked at a high frequency (rate).

The computer main memory output port is formed to have a width of 32 bits, for example. Each vixe A vixel decoder (vixel unwrap) (not shown in FIG. 1). This division is following instructions appropriate to the form of pixel description used to store data. The pixel description is 24 bits, with one byte for each of the 3M color components of the pixel. Contains tuto. Therefore, input latch 2 is provided with 24 bit storage locations. ing. There are 24 bits in the word representing each pixel fed to input latch 2. If there are fewer bits, the remaining bit positions are loaded as O's.

The 24-bit word held in latch 2 is stored in the first colormap memory 4. No. 2 color map memory 5. Read address for third color map memory 6 This is an input for the formatter (formatting device) 3 that generates it. color pine The memory 4.5.6 provides each color component signal, and these component signals are supplied to a display device (not shown) used to reproduce color images on a screen. It will be done. The color map is a RAM that operates as a read-only memory (ROM). It is desirable that these can be downloaded from the main memory of the computer to any desired location. loaded using the desired colormap data. Color map memory 4.5. 6 during field retrace of the video signal samples transmitted to the display device. It is convenient to perform this download. Computer main memory uses VRAM download from the serial output port of that memory is very This is done at a high frequency during the line trace as well. For example, if the main memory of a computer is a 32-bit wide serial Assuming you have an output port, the 8 bits of its output are used to address these memories during the write period of memory 4.5.6. It will be done. The other 24 bits are entered as write inputs to colormap memories 4, 5, and 6. Each is allocated to the provided byte width.

Colormap Memory 4.5.6 has separate read outputs and write inputs. Although shown as a double boat in the sense that A multiplex configuration is also possible so that RAM with a bus can be used. Ru. Colormap memory has separate read and write address inputs. Although it is shown as having power, each of the color map memory 4゜5.6 multiplexes both address sets through the same address bus It can also be configured to do so. The contents of the registers in Formatsuta 3 are calculated using a calculator. By downloading from main memory random access input/output ports programmed. Alternatively, read through the serial output port of the computer's main memory. The multiplex of computer main memory becomes more complex, so these registers The controller can also be programmed from its read output.

The first, second and third color map memories 4.5.6 each have a color display. The values of the green, red, and blue drive signals can be stored for direct supply to the device. child This allows the three colors to be additively mixed according to their contribution to the luminance. 0 to assign the number of bits in the output of the map memory, e.g. a value of 1 & is stored at 2 bits higher resolution than the red value and 3 bits higher resolution than the blue value. memorized in degrees. This makes the color display device appear more expensive overall than it appears. You can allocate the overall colormap memory capacity to give a higher resolution. Wear.

Generally, a computer handles graphic images, and a camera handles the graphics images. If you rarely or never work with footage that is ・Enable memory 4.5.6 to store red, green, and blue display drive signals. is a design choice. This means that these three additive primary colors are always positive values, Since it is a completely independent variable, it is possible to perform video calculations more easily. Depends on. Also, most display devices ultimately require red, green, and blue driving signals. Ru.

However, computers often need to handle images generated by cameras, In this case, the plotting processor uses only luminance information with full spatial resolution, and Receives pixel data with chrominance-only information at a specific spatial resolution. I have something to believe. That is, the response of the original digitized camera is Minance is sampled at full density in both the horizontal and vertical directions of the displayed image. chrominance, while chrominance is horizontal and/or vertical, preferably both. is subsampled at a coarser density. In computer main memory.

To store images in terms of luminance-only variables and chrominance-only variables. Therefore, the drawing processor can be simplified.

7 ohms to generate read addresses for color map memory 4, 5, 6. Execute pixel data in this format guided through ivy 3 , one of these memories stores the luminance-only variable, and one of the It is desirable to make each of the other two memories addressable in the coordinate system of stores each of the two chrominance-only variables, and the chrominance-only It is desirable to make this chrominance-only coordinate system addressable in the coordinate system of is, for example, two orthogonal chrominance-only representations of each chrominance-only primary color. It consists of the following ingredients. Or any set of chrominance coats as another example It may also consist of

The second colormap memory 5 stores luminance-only primary color values. 1st o and a third colormap memory 4.6 respectively store the first chrominance-only source. The color bond and the primary color bond with only the second chrominance are stored respectively. color map - The values of these primary colors read from memory 4.5.6 are not shown in Figure 1. matrixed circuits to generate red, blue, and green drive signals for color display devices do.

These signals can be combined to combine chrominance-only and luminance-only signals. The signals need to be re-stored at full spatial resolution by interpolation. Spatial interpolation It is only successfully implemented when the color is expressed in terms of three primary color components. If color Any of the map memories 4, 5.6 may be e.g. any chrominance code. If addressed by other items such as It should be between the readout and output of the colormap memory.

Assuming that spatial interpolation is performed in two directions (i.e. both horizontally and vertically) Then, it is best to adjust as follows. Computer main memory and pixel input A rate (frequency) buffer memory (not shown in Figure 1) is connected to The rate buffer memory is Color map notes related to adjacent lines of two trees of pixels based on interrelationships Provides re-read address. These consecutive read addresses Chrominance-only coordinates used to address memory 5 and 6 are temporarily stored in these bit positions of the pixel input latch 2 associated with the pixel input latch 2.

This is the four approaches required for two-way (e.g. bilinear) spatial interpolation. In order to identify the set of subsamples that form a group, Specify four consecutive readout outputs, 1 and 6. Spatial interpolation circuit (not shown in Figure 1) ) aligns the four subsamples in time, and is an image of the position of the full density sample or the above sub-samples resulting from interpolation. It is weighted according to its position in the field. One luminance only A primary color sample and a chrominance-only primary color sample obtained by interpolation of the other The delay difference between is compensated. In general, the total 3I main memory and memory of Formattuta 3 are The above compensation is performed in a rate buffer memory placed between cell input latch 2. It is best to

Serial output of VRAM that operates as computer main memory during line retrace period rate buffer with chrominance-only information downloaded from the boat. Preferably one that is configured to load memory, then the serial output port is free to supply only luminance-only information during the line retrace period. Can be done.

Colormap Memory 4.5.6 contains any of these Vs during the line retrace period. rewritten by data downloaded from the serial output port of RAM. In this embodiment of the invention, there is no competition for available time during the line retrace period. Designers must keep this fact in mind.

Interpolation of chrominance-only primaries read from colormap memories 4 and 6 color map memory 5 used as a luminance map. The address of the colormap memory 4.6 is required independent of the colormap memory 4.6. This is Kara The pattern of read addresses supplied to the color map memories 4 and 6 is Unlike the sampling pattern of the read address supplied to the block memory 5, Because there is.

Next, the configuration of the formatter 3 will be explained. Formattuta 3 is input color and punch 2 Readout for colormap memory 4.5.6 from pixel data held in Used to generate addresses. Each part of this pixel data is is selected as the basis for generating the read address of this data. This is done according to the first, second and third masks for the 24 bits.

The first 24-bit mask specifies the read address of the first colormap memory 4. A link specifying the position in the output of latch 2 to be selected as the basis for generating The position in the output of latch 2 that has a following rlJO group and is not selected as such. from the computer's main memory under the guidance of the data processor. Preloaded into mask register 11. Bits being output from mask register 11 The cut positions are each first input to rank 12 of the 24 AND gates; Each second input is a respective bit position of the output from input latch 2. and gate la The output of link 12 corresponds to the O in the first mask output of mask register 11. A value of 0 at all positions. The remaining at the rank 12 output of the AND gate The bit position is the first selected position of the output of input latch 2. and gate The output of rank 12 of aligns the first selected portion of the output of latch 2 It is supplied as an input to shifter 13.

The shifter 13 receives the 24 bits supplied as output from the rank 12 of the ant gate. Performs a barrel shift function where the cut is shifted in one of two ways.

The bits in the 24 bit positions of the output of shifter 13 are shifted in the direction of increasing weight. and the overflowed bit is shifted to an empty least significant bit position or In other words, the bits at the 24th bit position of the output of shifter 13 are shifted in the direction of decreasing weight. underflowed bits are shifted to the empty most significant bit position. . A shift in either direction will yield the same result as shifting enough bit positions. Therefore, if the shifter 13 always shifts in one direction, the shifter 13 should be The number of bit positions of the shift in the selected direction can be easily configured as 0. The shift control register 14 of the register 14 is preloaded, and the contents of the register 14 are updated. is programmably shifted by a positive binary number stored therein.

As each pixel is scanned, the first pre-address register 15 registers the shifter 13. Loaded from 8 bit positions of the output, which bit positions pass through the first mask. includes a first selected portion of the output of latch 2. The shifter 13 is Output of shifter 13 loading high order bit or first prefix address register 15 Even if the most significant 8-bit position of Even at the lowest of these 8 bit positions of the output, this first of the outputs of latch 2 Align selected parts according to convention. Prefix address register 15 is Store the first selected portion of the output of latch 2 and latch each of its bit positions. the first input to each OR gate in link 16; Or game in rank 16 The first index register 17 supplies the first Receive each bit position of the index. The first index is the computer main Preloaded from memory. The output of the or gate in rank 16 is the first color. This is the read address for the map memory 4.

The read address for the second color map memory 5 is determined by elements 11-17. 2 in a manner similar to the read address for the first colormap memory generated. 1 to 27. Read address for third color map memory 6 The response is the readout to the first colormap memory generated by elements 11-17. Similar to the output address, it is generated by elements 31-37.

The shifter 13.23.33 is configured as follows to shift according to the binary control signal. It is convenient to configure. Each of the shifters 13.23.33 has multiple component jitter are connected in cascade. The first component shifter is the bottom of the counter output, respectively. Select between no shift where the digit bit corresponds to 0.1 and shift by 1 bit position. each multiplexer. The second component shifters each have a counter output The second least significant bit of corresponds to 0.1 with no shift and a shift of 2 bit positions. Each has a multiplexer to choose between. Any number of ingredient chic The second shifter has a counter output whose least significant bit is 0. Schiff corresponding to 1 Each multiplexer has a selection between no bits and a shift of 2″LL bits. Ru. Therefore, the total shift amount obtained from all shifters 13, 23, 33 is It is the sum of the bit positions of the shifts of the bc-connected component shifters. Below in this statement In the section , as the value of the binary number used as each control signal increases, the shifter 13.2 3.33 is assumed to be shifted in the direction of increasing weight.

The display processor of FIG. 1 is designed to simplify its programming. It is possible to transform the formatter 3 of the sensor. Prefix address register (prefix Address register) 15.25.35 always align inputs in the same direction automatically using the information stored in the mask register. It is possible to perform alignment. According to this, the 1st, 2nd, and 3rd shift system Program for loading control data into shift control register 14.24.34 This eliminates the need for The display processor formatter 7 in FIG. 2 has such a modification. , which makes automatic preaddress alignment always increase in weight if necessary. It is. The display processor formatter 8 of FIG. If necessary, the automatic prefix address alignment should always be in the direction of decreasing weight. , more details about the display processor formatter 7.8 of FIGS. 2 and 3. After explaining the alignment process in more detail based on the operation of Formattuta 7.8. explain. All operations of Formattuta 3 are similar to Formattutu and Formattuta 8. These explanations cover the display process in Figure 1, as it can be applied in the same way. The possible actions of the server will become clear.

The display processor in Figure 2 uses data that completely represents a pixel using 24 bits or less. is loaded into input latch 2.

They occupy the most significant bit positions of the output. The remaining lower bits of the output of latch 2 The bit position should preferably be filled with O, with exactly 24 bits of pixels. The fully representative data is loaded into pixel input latch 2 without using O insertion. is coded.

The pixel data that should be the basis of the read address of the first color map memory 4 The data are always forced to be grouped into the eight most significant bits of the output of latch 2.

The first selection position of the output of latch 2 is limited to only 8 bits. This results in 2 The mask register 11 of Figure 1, which had a storage location of 4 bits, can be replaced with just 8 bits It can be replaced by a mask register 38 with a memory location.

Also, in order to select the first part of the output of latch 2, the 24 AND gates in FIG. It is possible to replace rank 12 of the gate with rank 39 of only 8 AND gates. Wear. The output of rank 39 of the AND gate is input to prefix address register 15. does not require a shifter to align with.

The pixel data to be the basis of the read address of the second color map memory 5 The data are always grouped into the 15 most significant bits of the output of latch 2. latch The selected portion of the output of 2 is limited to only 8 bits wide, but this byte The width is the pixel data that is the basis of the read address of the first color map memory 4. Only 16 bits, which does not match or overlap the byte width allocated to the data. To store the second mask in the mask register 41, which has a storage location for the is sufficient and can be used in place of the wider mask register 21 of FIG. Wear. Rank 42 of only 16 AND gates is replaced by 24 AND gates in Figure 1. It can be replaced with rank 22 of the root.

In addition, the shifter 43, which has an input capacity of only 16 bits, can be replaced with an input capacity of 24 bits. The shifter 23 shown in FIG. 1 can be replaced with the shifter 23 shown in FIG. Shifter 43 is out of latch 2. The second selected portion of the output is applied to the top bit to load the prefix address register 25. Alignment should be done to shift the barrel to the set position. A number of least significant bits with a constant number of bit positions in a barrel shift in the direction of is shifted in the direction of increasing weight, and the overflowing bits of higher weight are Inserted into empty lower weight bit positions. given by shifter 43 The number of bit positions included during barrel shifting is the count of clock counter 44. Specified by output. This count output also indicates that the other shifter 45 the first mask received as input from the mask register 41 at its output. Also specifies the number of bit positions to barrel shift towards the position weight. shifter 45 The most significant bit position is provided to a detector 46 and if the bit position is 0 Generates a shift signal. The shift signal is transferred as the count input of counter 44. sent. More specifically, detector 46 consists of a single-bit complementer; The output of the complementer is sampled by the clock of counter 44. Second prefix a Address register 25 is loaded from the eight most significant bit positions of the output of shifter 43. and the alignment of the second selected portion of the pixel data in latch 2 is weighted It is carried out in the direction of increasing.

The pixel data to be the basis of the read address of the third color map memory 6 The data is grouped anywhere in the 24 bits of input latch 2. Latch 2 output The third selected portion of Similarly, in response to the third mask (third mask signal) stored in the mask register 31, The answer is selected by rank 32 of 24 AND gates. Latch 2 output The third selected portion of is formatted as in formatter 3 in FIG. The tough shifter 33 adjusts the NFA in the direction of increasing weight. However, Fig. 2 In the formattuff of the display processor of The number of bit positions in the ft is specified by the count stored in counter 47. . This counter also specifies the number of bits and thereby the third macro of register 31. The contents of the disk are shifted at the output of the thick 48, similar to the shifter 33. Shifter 33 and 48 are weighted in their outputs as the count in counter 47 is incremented. It is shifted in the direction of increasing the brightness. The most significant bit of the output of shifter 48 is sent to detector 49. is supplied and generates a shift signal if that bit position is The signal is transferred to counter 47 as a count input. Third prefix address register Register 35 is loaded from the eight most significant bit positions of the output of shifter 33 and The position adjustment of the third selected portion of the pixel data in section 2 increases the weight. be.

In the formatter 8 of the display processor shown in FIG. The first, second . The position adjustment of the third prefix address is performed by the display process in Figure 2. In the case of Sa's 7-oh Matsu Tough, the weight increased, but in this case it was the opposite. The weight always decreases. The data processor in Figure 3 uses a 24-bit The data that completely describes the pixel below and below is loaded into input latch 2 and They occupy the least significant bits of the output. The remaining output of input latch 2 The higher bit positions should preferably be filled with 0s, as before, exactly 24 bits. Data that completely describes a pixel in a pixel without using zero insertion The 0th order loaded into input latch 2 is either the formatter 8 in Figure 3 or the former in Figure 2. I will explain the differences from Ivy 7.

The read address of the first color map memory 4 or the pixel data to be the basis The data are forced to be grouped at the eight least significant bit positions of the output of input latch 2. Ru.

The read address of the second color map memory 5 is the pixel data to be the basis. The data are grouped in the 16 least significant bit positions of the output of input latch 2.

The outputs of chics 43' and 45' indicate that the count contained in counter 44 is increasing. In response to this, other bit positions are shifted in the direction of decreasing weight. counter The count in 44 indicates that the detector 28 has a 0 in the least significant bit position of the output of the chic 45'. is increased when detected. The eight least significant bit positions of the output of chic 43' are the second Load the prefix address into register 25.

The outputs of shifters 33' and 48' increment the count contained in counter 47. In response, other bit positions are shifted in the direction of decreasing weight. counter 4 The count in 7 indicates that detector 29 detects a 0 in the least significant bit of the output of chic 48'. It will be increased when you put it out. The eight least significant bit positions of the output of thick 33' are the third prefix. Load the address into register 35.

The different pixel data formats are then formatted according to the formattuff in Figure 2. Explain how it is adjusted. These considerations allow for more flexible You can also learn how Formatsta 3 in Figure 1 is used. Ru. 4 to 6 show input data latch 2, mask register 38.41 ．． 31. Pixel data contained in prefix address registers 15.25.35 2 is a summary of the block diagram of FIG. 2 to illustrate the nature of the data. Figures 4 to 4 When considering Figure 6, assume that the first, second, and third indices are 0 values. Assuming that the contents of prefix address registers 15, 25, and 35 are respectively colored This corresponds to the read address of map memory 4.5.6.

Figure 4 shows 1, for example, 8-bit red (R), 8-bit green (G), and 8-bit blue (B). ) is used in computer main memory, the pixel data is How does it flow from latch 2 to prefix address register 15.25.35? It shows. Alternatively, Figure 4 shows 8 bits Y, 8 bits (RY), 8 bits (B-Y), or 8-bit Y, 8-bit I, 8-bit Q picture When cell description is used, pixel data is transferred from latch 2 to the prefix address. Think of it as showing how it flows into registers 15.25.35 You can also do it. Y is a luminance-only primary color, (RY), (B-Y), or 1. Q is the primary color of the first and second chrominance only. 3-byte pixel data Data input latch 2 is a 24-bit number ABCD EFGHJKLMNPQR5TU V WXYZ is filled, each character represents either l or 0, (mask ・The 8-bit first mask (first mask signal) stored in the register 38 is All are O, and the first 8 bits ABCD EFGH of the contents of latch 2 are rank 39. selected by the AND gate in the middle and inserted into the first prefix address register 15. Ru. The 16-bit second mask (stored in mask register 41) Consists of 8 O's in the top position followed by 8 1's in the lower positions . The middle 8-bit JKLM NPQR of the contents of latch 2 is the AND of rank 42. selected by the gate, shifted by the shifter 43, and then the second prefix Inserted into address register 25. (stored in mask register 31) ) The 24-bit third mask has 16 zeros in its upper positions and the following It consists of eight 1's in its lower position. 8 Least Significant Bits 5 of the Contents of Latch 2 TUV WXYZ is selected by the AND gate in rank 32, and shifter 33 and inserted into the third prefix address register 35.

In this mode of operation, the values of the first, second and third index are 0 and the color Each of the map memories 4.5.6 has a readout for those storage locations. and stores an output signal equal to the address. This is actually the prefix address register. The contents of data 15, 25, and 35 are transferred to the display device as a drive signal. Or, The value of the 1st, 2nd, and 3rd index is O, and the colormap memory is prefixed. response register 15.25.35 to provide nonlinear responsiveness to the contents of the response register 15.25.35. This processing is common in digital graphics video, for example. Calculator monitors designed to use non-gamma corrected video, as shown selected from broadcast television footage to match the footage for display on the screen. It can be used to remove unwanted gamma correction. Y, 1. Q: How does it work? The nonlinear response from Colormap Memory 4.5.6 is based on chrominance-only sources. Calculator to make color resolution higher near white than for saturated reds, greens, and blues Used to better represent images in generated images. color map me By independently addressing memory 4.5.6, computer programmers can freely choose generates a component video representing a camera-generated image or an image that simulates it. The color map memory 4 described above is used to perform linear or non-linear processing of the ．． 5.6 can be used. Independent addresses of memory 4, 5, 6 This allows these memories to be used for graphic image processing. Performs the above functions in addition to performing more general color mapping tasks be able to. False color by independent address of color map memory 4.5.6 can also be easily displayed.

Figure 5 shows pixel data input from pixel data latch 2 to the formatter. Indicating another method of circulating the prefix address letter star 15.25.35 in 7. The pixel data in latch 2 is stored in 16-bit format to protect the computer main memory. pixel data, padded with 8 consecutive 0s before being input into latch 2. is being processed. These 2 bytes of pixel data are 4 bits AB of the blue primary color. CD, 5-bit JKLMN with red primary color, and 7-bit 5TUVWXY with green primary color. It will be.

The 8-bit first mask (stored in mask register 38) signal) has four 1's as the most significant bits to select the blue information, followed by the red It has four O's as lower bits for masking information. Therefore, The four most significant bits ABCD of the contents of latch 2 are the AND gate in rank 39 The first bit is selected by is inserted into the prefix address register 15 of.

16-bit second mask (stored in mask register 41) ) is followed by four zeros as the most significant bits to mask the blue information. 5 1's to select red information and 7 to mask the following line information It has O. Shifter 43 is 0 at the output of rank 42 of the AND gate. 000 JKLMNOOO000017) Red information response JKLM N0OOoo Adjust the position to oo　oooo and output the first 8 bits of the shifter 43 output 0OO is inserted into the second prefix address register 25.

The 24-bit '3rd mask (stored in mask register 31) signal) has nine O's as the most significant bit to mask the blue and red information. , followed by seven 1's to select the line information and a 0 governing this. It has 8 bits. Shifter 33 outputs rank 32 of the AND gate. ooooo in.

000 0 STU VWXY 0000 0000 green information response 5 TUV WX Adjust the position to YO000000000ooooo, and set the first output of shifter 33. The second 8-bit 5TUV WXYO is inserted into the third prefix address register 35. Ru.

The pixel data of input latch 2 is combined with the blue information of the first 4 bits and the second 5 bits. It is possible to organize by the red information of the last 7 bits and the line information of the last 7 bits. and prefix address registers 15.25. :Data loaded at 15 can minimize the number of shift signals that must be generated to align the . This reduces the time required to reprogram the Formattuta 7. Can be done.

Figure 6 shows the pixels coated in Formattuta 7 or Colormap Address. - Shows how the data can be processed. 6 bit color Map read address AB　CDEF encodes 26 colors, and each color has a unique combination of hue, color saturation, and luminance. These 6 bits ・The color map read address contains 18 lower bits in pixel latch 2. Bad on the cut. If these 18 lower bits are 0, then the first mask the 2 least significant bits, the 10 least significant bits of the second mask, and the 10 least significant bits of the third mask. Whether the 18 least significant bits are l or 0 will be discussed further later in this specification. Vixel grapping (grabbing a vixel) of pixel input latch 2 only when called to execute! becomes the key. Apart from this, the first The two least significant bits of the mask or 0. The least significant bit on the lO side in the second mask is 0, If the 18 least significant bits in the third mask are 0, then the 18 least significant bits of the contents of latch 2 It doesn't matter whether the least significant bit is 1 or 0; at least one of these two states Either one should be satisfied and the existence of both is shown in FIG.

The first mask (stored in mask register 31) has 6 upper bits. 1. Since it has two O's as lower bits, the rank of the AND gate is 39. provides ABCD EFOO as an input to prefix address register 15. ( The second mask (stored in mask register 41) has six bits as the upper bits. 1. Since it has 10 0s as lower bits, the rank of the AND gate is 42. supplies ABCD EFOO00000000 to the shifter 43 as an input. No. 2 mask has 0 in its top position, so this input is the output of shifter 43. Prefix address register 25 does not require alignment to form the 8 The most significant bits ABCD are loaded with EFOO. (Mask register 31 The third mask (stored in Since it has 0 and 0, the rank 32 of the ant gate is input to the shifter 33. and supplies ABCD EFOO00oo oooo oooo oooo. child In the case of Load BCD with EFOO. Colormap memory 4.5.6 is as shown in Figure 6. is loaded with colormap data to operate with the read address. , this is the general process for loading these memories with colormap data. 26 possible color maps with 6-bit pixel data codes representing The address is continuous as the write address for color map RAM 4.5.6. and each primary color component drive signal to the display device associated with that address is It is written to RAM at a specific time. This is always done by the display processor shown in Figure 2. or during field retrace. computer owner V memory performs rapid download to rewrite RAM4,5.6 If you are using RAM, these colormap memories will be line retriggered. be rewritten in whole or in substantial part during the period of Included. If you have RAM 4.5.6 or a set of double balls, you can use it for color maps. The contents of these RAMs are also updated little by little during the line retrace period. Things can happen.

Assuming the same colormap read address is supplied to each of RAM 4.5.6 Then, the 8-bit color map read address is encoded into 26 colors. It can be used as pixel data for bits as pixel data to encode 2′″ colors I can do something. This is similar to the method of color mapping in the prior art.

However, the three 8-bit colormap read addresses are 2'' x 28 x It is possible to map 2a or 224 different colors. read ad 2(p″@*r You can map one color. Here, if p=q=r=m, then 2 It is possible to map 31 colors, and all 3 color maps have the same readout. When receiving an address, the map is 21 times larger than the conventional color mapping method. It is possible. However, these extra colors have a corresponding magnitude of luminance. All these extra Sometimes you don't actually need that color.

Next, how many different pixel formats can be created by Omatsuta 8 (see Figure 3)? Let's think about whether it's possible.

Formattuta 3 in Figure 1 operates in the same way as Formattuta in Figure 2. Not only this, but also the performance of the formatter 8 shown in Figure 3, as described below. It can also work the same way. Figures 7 to 1O are input pixel data. ・Latch 2, mask register 38.41.31, prefix address register 15 ．． 25. The blocks in Figure 3 are used to illustrate the nature of the pixel data contained in 35. This is a summary of the schematic diagram. When considering Figures 7 to 1O, the first ．． The second and third indexes are O values, so prefix address register 1 The contents of 5.25.35 are the readout addresses of color map readout memory 4.5, 6. Assume that each corresponds to FIG. 10 also shows index register 17. The nature of the index stored in 27.37 and the rank of ORGATE 16.26 ．． 36 output connections to the colormap memory 4.5,6. It shows the nature of the response.

Figure 7 shows pixel descriptions of, for example, 8-bit red, 8-bit green, and 8-bit blue. When the main memory of the computer is used, pixel data or data is formatted from latch 2. How it flows to prefix address register 15.25.35 in Matsuta 8. It shows. The same format of pixel data flow is 8 bits in the main 3I machine memory. 8-bit Y, 8-bit I, 8-bit Q, or 8-bit Y, 8-bit ( This also occurs when an 8-bit (B-Y) pixel description is used.

3-byte pixel data input latch 2 is a 24-bit number 5 TUV WXYZ Filled by JKLM NPQRABCDEFGH. Each of these characters is 1 or O (stored in mask register 38). The first mask of the latch is all 1, and the content of the lower 8 bits of latch 2 is ABCD EF. GH is used for insertion into the first prefix address register 15 in rank 39. selected by the gate. (stored in mask register 41) 16 The second mask of bits consists of eight ones in its most significant bit positions, followed by and eight 0's in the lower bit positions. Middle 8 bits of the contents of latch 2 JKLM NPQR is selected by the AND gate in rank 42, and is a chic 4 3' and inserted into the second prefix address register 25. ( The 24-bit third mask (stored in mask register 31) has its upper bits with 8 1's in the bit positions followed by 16 0's in the lower bit positions. There is. The 8 most significant bits of the contents of latch 2 5TUv WXYZ are of rank 32 selected by the AND gate of location address register 35.

In this mode of operation, the first, second and third indices are set to 0 and each color Map memory 4.5.6 has a read address for that storage location at that storage location. Store the output signal equal to . This boils down to Prefix Address Register 15.2 5. Transfer the contents of 35 to the display device as its drive signal. Unlike this, The 1st, 2nd, and 3rd indices are set to 0, and the colormap memory is pre-allocated. Programmed to respond non-linearly to the contents of address register 15.25.35. You may be

Figure 8 shows the input pixel data from pixel latch 2 to the front of formatter 8. Latch 2 shows an alternative method for flushing the location address register 15.25.35. pixel data is 16 bits pixel data to maintain computer main memory. data and is baded with 8 leading O's before being input into latch 2. . These 2 bytes of pixel data consist of 7 bits 5TU of the primary color green. VWXY, 5 bits JKLMN of the red primary color, and 4 bits A of the blue primary color It consists of BCD.

The 8-bit first mask (stored in mask register 38) masks the red information. Select four 0s as the most significant bits and the blue information following this to screen. It has 4 as the least significant bit (1 of i). Therefore, latch 2 The four least significant bits of the contents of ABCD are determined by the AND gate in rank 39. selected as the least significant bit with the most significant bit consisting of the preceding 4 O's. inserted into the first prefix address register 15.

A 16-bit second mask (stored in mask register 41) contains green information. 7 zeros as the most significant bits to mask and With 5 1's to mask the blue information and 4 0's to mask the blue information. There is. Sick 43' is 0000 00 at the output of rank 42 of the AND gate 0J KLMN 0000 red information responsiveness 0000 0000 000JKL KLMN is aligned with MN, and the final 8 bits of the output of chic 43' are 0OOJ. 2 is inserted into the prefix address register 25 of 2.

The 24-bit third mask (stored in mask register 31) consists of (0 and to select any eight most significant bits (shown as ) and the line information that follows. 7 zeros followed by 9 zeros to mask the red and blue information. ing. Shifter 33' is 0000 0000 at the output of rank 32 of the gate. 5TUV WXYo oooo oooo line information responsiveness.

ooo oooo oooo osTu Align to vwxy and shifter 33' The final 8 bits of the output of OSTUvwxy are stored in the third prefix address register 35. inserted.

Figure 9 shows the pixels encoded in the formatter 8 or colormap address. - Shows how the data can be processed. 6 bit color Map read address AB CDEF encodes 26 colors. Each color - has a unique combination of hue, color saturation, and luminance. These 6 bits The 18 upper bits in pixel latch 2 are used for the color map read address. Hit or bat. If these 18 most significant bits are 0, then the first mask 2 most significant bits, 10 most significant bits of the second mask, and 1 of the third mask Whether the eight most significant bits are 1 or O is determined by the pixel input latch 2. (the functionality of which is discussed further in this specification). Only important if called to do so. Apart from this, 2 in the first mask If the 18 most significant bits in the third mask are 0 and the 18 most significant bits in the third mask are 0, then - It is immaterial whether the 18 most significant bits of the contents of latch 2 are 1 or O. At least one of these different conditions must be satisfied, and both conditions must be satisfied. It is shown in FIG.

The first mask (stored in mask register 38) is It has 2 O's and 6 1's as lower bits, making it a rank 39 AND gate. provides 0OABCDEF as an input to prefix address register 15. ( The second mask (stored in the mask register 41) has 10 upper bits. 0 and 6 1's as lower bits, rank 42 of the ant gate is shifted 0000 0000 00AB CDEF is supplied to the data input terminal 43' as an input. No. 2 mask has a 1 in its least significant bit position so that the output of this input shift 43' , and prefix address register 25 does not require alignment to form The least significant bit of the 8 bits is loaded with 0OAB CDEF. (Mask Re The third mask (stored in register 31) has 18 O's as the upper bits and rank 32 of the AND gate is input to shifter 33'. And ooooooooooooooo.

0000 00AB Supply CDEF. In this case as well, alignment is not necessary; Thick 33' loads prefix register 35 with 0OAB CDEF.

Formatter 3 in Figure 1 needs to reload color map RAM 4.5.6. Provides exceptional flexibility in handling multiple pixel data modes It is equipped with This is a composite image using components drawn from separate video sources. Certain displays can easily occur on-the-fly, in real time. I can do it.

Much of this flexibility is also provided in each of the formatters 7.8 in Figures 20 and 3. Retained.

Here, we will consider the composite display imager. The first component image is habitually A linear color code, similar to the linear color code used with camera-generated video processing. It is explained in relation to This code sets the individual read addresses to RAM4, 5. ．． The second component image serves to supply the read address RAM 4.5.6 to the read address RAM 4.5. Any other color coats needed to feed 6 in parallel are described. The format of pixel data, which is a graphic image The first, second, and third masks are mask registers when proceeding from one format to another. Ta11.21.31. Or reloaded on 38.41.31. However, the first The 1st, 2nd, and 3rd indexes further address other component images. are index registers to address different parts of RAM 4.5.6. Reloaded on 17.27.37.

- As an example, the first component image may be the 16-bit pixel code described in connection with FIG. The second component video is the 6-bit format described with respect to Figure 6. ・FormatsuTough shown in Figure 2 operates using the pixel code format. Let's consider. In the prefix address, any one with 1 as the least significant bit The set of coats is also not generated, so it cannot be generated by either encoding scheme. All prefix addresses that can be stored are stored in RAMs 4.5 and 6 respectively. You cannot request more than half of the storage locations; this applies to each column of each coding system. This means that the RAM information is multiplexed in RAM.

The first half of the locations in each RAM 4.5, 6 are linear bits as described with respect to FIG. Allocated to store cross-court information. All these positions It has the address of the least significant bit or O. After each location in RAM 4.5.6 Half is arbitrarily coded color mapping information as described in connection with Figure 6. is assigned to remember. All positions are addresses whose least significant bit is 1. I have a response.

The input pixel flow is the 16-bit pixel code described in connection with FIG. When consisting of pixels representing the first component image using the format, register The prefix addresses in data 15.25 and 35 are related to the linear pixel code without modification. to RAM 4.5.6 to read the location where the color pixel data is stored. Provided as a read address. The least significant bit of the read address is 0 and addresses the first half of the RAM location. This is true for all bit positions. 1st, 2nd and 3rd in index register 17.27.37 of each This is done in response to the index of

The input bit stream is the 6-bit arbitrarily coded format described in connection with FIG. - The prefix address in the second configuration using matte is color mapping. RAM4. 5 and 6 must be corrected before being supplied as read addresses. in this case The fix is to force the least significant bit of the read address to be O, so the RA Address the second half of the M position. No. 1 in index register 17.27.37 The 1st, 2nd, and 3rd indices are set to 0000 and 0001, respectively, and the pixel data is Read any second half of RAM 4.5.6 when data is arbitrarily coded, e.g. That is, the prefix address in register Is, 25.35 is incremented by 1 and read out. Addresses are supplied to RAMs 4.5 and 6, and at these alternating storage locations the RAM is filled with colors. - Stores decoding information for any color coat according to the mapping principle do.

Actually, the first . 2nd and 3rd prefix address Since the two least significant bits of the bits are 0 in the pixel encoding method of Figure 6, The pixel coding scheme of FIGS. 5 and 6 is applied to colormap memories 4, 5. The additional pixel code occupies only 3/4 of the addressable storage locations in 6. The coding scheme contains a prefix address with 0 as its two least significant bits. As long as the index of 0000 0011 in index register 17.27.37 Adapting the above Bixel coating system by using Dex I can do it.

In another example of converting from one pixel format to another, The first component image has 16 pixels as mentioned in connection with FIG. using the second component image or the 6-bit pixel code described in connection with Figure 9. - Consider the formatter 8 in Figure 3 that operates to use the format. do.

Neither group of codes yields a prefix address with l as its most significant bit. stomach. All prefix addresses generated by either encoding scheme are RAM 4.

It is not possible to occupy more than 1/2 of the storage locations obtained in each of 5 and 6. ．． This means that each color map information for each coding system is multiplexed in RAM. means that it will be scanned.

Half of the locations of each RAM 4, 5, and 6 are located in the linear pixel code described with respect to FIG. The other half of each RAM location is allocated to store code information. stores the arbitrarily encoded color mapping information described with respect to FIG. It is allocated for. The first half of all RAM locations have the most significant bit set to O. The last half of every RAM location has the address of the most significant bit. I have it. The input pixel stream is in 16-bit pixel code format. When the register consists of pixels representing the first component image using Ta Is, 25. The prefix address in 35 is the bit that converts the color information into a linear code. Read to RAM4.5, 6 to read the location where the cell data is stored. It is supplied as an address without modification. Therefore, the most significant bit of the read address is 0, addressing the first half of the RAM locations. This is for all bit positions The first, second, and third indexes in index registers 17, 27, and 37 of This is done in response to

The input bit stream is in a 6-bit arbitrarily encoded format (Figure 9). When consisting of pixels representing the second component address used, register 15. The prefix addresses in 25 and 35 are supplied to RAM4.5 and 6 as read addresses. must be corrected before it is released. The correction in this case is to The digit bit is set to 1, thus addressing the second half of the RAM location. B When the cell data is arbitrarily encoded.

In registers 17, 27, 37 to read the second half of RAM 4, 5, 6 locations. The first, second, and third indexes are set to iooo and oooo, respectively. this If prefix addresses never have 1s in their most significant and second most significant bits, Additional pixel encoding schemes extend colormap memory 4, 5, and 6. It can be used without the need for programming or reprogramming. index register The first, second, and third indexes in stars 17, 27, and 37 are such additional codes. It will be 1100 0000 for the system.

In the formatter 8 of the display processor of FIG.

Colormap memories 4, 5, 6 to supply different sets of pixel coats The storage locations within are allocated to a range of width of 2 integer bundles. This is the first, second, third OR gate to combine the index of with the first, second, and third prefix addresses. Rank 16. is the restriction imposed by using 26, 36, R It is possible to allocate the AM position part to any range. or gate run If blocks 16, 26, and 35 are replaced with respective adders, the code range can be arbitrarily selected. Something will happen.

Each component image is either camera-generated or linearly coated pixel image. is a color component, but has a resolution greater than or equal to the resolution specified for one component video or the other component video. What if a color fordinate with high amplitude resolution is specified? Let's consider i&display video. Formata 3 in Figure 1 or Formata 3 in Figure 2. - Assuming Matsuta 7 is used, the pixels for resolving these two components - The data are coated as shown in Figures 4 and 5, respectively. mask position Combined and 1st. The alignment of the pixels passing through the second and third masks is towards the top Since the color map RAM 4.5.6 has the same function or the video of either component image is Also compatible with Xcel data. Composite display images can be constructed in real time, on the fly. I can accomplish something. Do I need to reload colormap memory 4.5.6? If we assume that the transitions do not occur between the scan lines of the display, then the changes between the component images The transition period will appear in the composite video.

In the formatter 3 in Fig. 1, linear coding is performed with different amplitude resolutions. The transition between the component images is determined by the first, second, and third maps for registers 11.21.31. 14.24.34; 2. The rotary process requires only a third shift control load. If both are executed in parallel in time to a certain extent, the above register rotor will become colored pine. This occurs much more rapidly than reloading RAM 4.5.6.

The formatter 7 in Fig. 2 uses linearly coated component images with different amplitude resolutions. The transition between the first . 2nd and 3rd square Loot the mask for transitions during Format Tough that only require a clout. It takes time to read and align, but that time is ．． It's much faster than loading 5.6. The high-speed alignment circuit is a display Make these transitions invisible during the ray. Apart from this, to increase the transition speed In addition, Ijii some form ivy (like Omatsu tuff in Figure 2) are bixelized. Connected in parallel between input latch 2 and colormap RAM 4.5.6 for banking The technique known as stagger may also be used to operate bankin data processors using slow alignment circuits. It may even work to make the above transitions invisible during display. Up It is also possible to use a combination of the techniques described below.

The formatter 8 in FIG. Second. The third prefix address towards the lowest RAM4,5 for pixels from two different video sources ．． Two sets of read addresses are generated for each of the 6 read addresses. Upper bit of pixel input latch 2 Expand pixel data that is short in length by entering 0 in the cut position. Then, the resulting set of short bit length read addresses can be used for longer bit length read addresses. There is no sub-subring of the pair of outgoing addresses, so the colormap memory 4.5.6 must be reloaded when moving from one component image to another. This causes the inconvenience of not having it. However, in order to eliminate these drawbacks, perform more complex formatting of data loaded into input latch 2 You can also do that.

This drawback of formats like 8 in Figure 3 is that they cannot be mapped to any video source. Color map readout address with 1 bit more resolution than required for You can also compensate by giving a response. Video from one video source to another converting one or more of its components to a source with varying degrees of amplitude resolution To avoid reloading colormaps, sometimes It is also possible to adopt the above-mentioned index system that multiplexes the storage location of Wear.

Index registers 17.27.37 are prefixed in FIGS. 1, 2, and 3. Shown as having the same number of bit positions as address registers 15.25.35. and there are a proportional number of or gates in rank Is, 26.36 do. Formatsuta 7 in Fig. 2 is connected to the or gate and the and the index register is the output of the prefix address register Is, 25.35. It can be arranged to process the second force only from the lower bit position of the force. It can be simplified as follows. Prefix address register 15.25.35 output The upper bit positions of the output are stored in RAM 4.5 as well as the upper parts of their read addresses. ．． 6 directly. The composition of the index for format data 8 in Figure 3 is also You can make it easier. OR gates and inputs supplying their respective first inputs. The index registers are read only from the upper part of their address. It can be arrayed to process. Therefore, the prefix address register Is , 25.35 lower bit positions are the same as the lower part of their read addresses. Provided directly to RAM 4.5.6. However, the format of M2S diagram 8 The rank Is in the middle is 26. If you reduce the number of or gates in the 36, the program This programming trick that interferes with programming tricks is a computer master memo. This is extremely effective in reducing the amount of video memory required during video processing, and the display screen shown in Figure 3. This is done more easily in the processor of FIG. 2 than in the processor.

FIG. 10 shows the display processor of FIG. 2, in particular the above programming triggers. It is designed to make it easier to understand how the process is carried out. be.

It is desirable to describe the pixels in terms of 8-bit primary color components as in the case of Figure 7. However, the upper bits of those primaries do not change as often as their lower bits. It is preferable to use the real - as an example, the two most significant bits of the first primary color component. Assume that AB does not change over a number of consecutive scanned pixels. Therefore, total Bit AB for these consecutive pixels stored in the video memory part of the computer's main memory. The two most significant bits of the second primary color component do not need to be repeated in the xel code. The cut JK changes relatively infrequently compared to the pixel scan rate, so JK is Assume that there is no need to iterate the code-bixel scan rate. Furthermore, the 3rd M The two most significant bits ST of the hull component change relatively infrequently compared to the pixel scan rate. , so it is assumed that there is no need to repeat the ST by pixel coating and pixel scan rate. Set.

Vixels introduced into pixel input latch 2 at pixel scan rate Take WXYZ LMNP QRCD EFGH. In other words, it changes relatively slowly. Bit A. B. J. K.

S. T is suppressed in the pixel code provided by the pixel scan rate. No. When there is a change in the two most significant bits AB of one primary color component, the updated bit AB is From computer main memory to the two most significant bit positions of first index register 17 It will be downloaded to . There is a change in the two most significant bits JK of the second primary color component. Then, the updated bit JK is transferred from the computer main memory to the second index register. data 27 is down-loaded into the two most significant bit positions of data 27. Two third primary color components When there is a change in the most significant bit ST of -Downloaded into the two most significant bit positions of register 37. index register 17. The six least significant bit positions of each of 27 and 37 are It has 0 maintained by .

From the perspective of simplifying display computer control, index registers The download of data 17, 27, and 37 is a short part of the line retrace period. is preferably configured to occur during the index register rot period. Yes. Once this is done, the pixel code for each successive line scan is How many of each of the primary color components can change during the box register load period? Whether the high order bit of Based on. This pixel code omission process However, the display processor in Figure 1 The code elision process can be pushed forward for all bit positions. .

Format the pixel code that is loaded into input pixel latch 2 In addition to the correct prefix 0 or the correct suffix 0, Assume that it is configured to include scattered O. Therefore, virtually the same color pine The ping function can be used in formatter 7 as well as in format 8, or in formatter 7. It is executed in the formatter 8 in the same way as in the formatter 7.

Mask registers 11 and 21 of formatter 3 in FIG.

31, and mask registers 38 of formatters 7, 8 of FIGS. 2 and 3. ．． 41. A load of 31 is typically calculated during part of the line retrace period. This is accomplished by downloading from the main memory. 7 Ohmatsuta 3, 7, 8 Loading index registers 17, 27, and 37 of is accomplished by downloading from computer main memory during the rest of the It will be done. Loading shift control registers 14, 24, and 34 of formatter 3 in FIG. is generally done in the same way. However, various operations during the line scanning period It is also possible to provide transitions between modes. This is because multiple registers are This can be done by having a plex with a flexible set of registers for each. between two registers of a certain set, for example two first mask registers lla, l Multiplexing between lb and lb is conveniently controlled as follows. Set- A reset flip-flop is connected between the first mask register Ila and llb. Control which multiplexer to select with . This futzbuf during each line retrace period the first mask register lla is reset to supply the first mask. selected. The output of colormaps 4, 5, and 6 is set flag, reset first and second flag states in response to respective states of the outputs of the RAM designated as Supplied to the decoder. Transferred from computer main memory to pixel input latch 2 1 to set RAM4, 5, and 6 to the set flag state. In some cases, the first decoder responds by setting a flip-flop and The multiplexer selects the first mask register llb to supply the first mask. Choose. The pixel code transferred from the computer main memory to the pixel input latch 2 When the code is one that puts the outputs of RAMs 4.5 and 6 into the reset flag state, .

The second decoder responds by resetting the flip-flop and demultiplexing. The server again selects the first mask register lla to supply the first mask. The same flip-flop is connected between the pair of second mask registers and between the pair of third mask registers. between index registers, between index registers that form a pair, between index registers that form a pair, and between second index registers that form a pair. control the selection between index registers, pairs of third index registers, etc. You can also do that. Easily design more complex multiplex configurations of registers Something will happen.

The display processor in FIG. 11 is a simplified version of the display processor in FIG. The formatter 18 in FIG.

24-bit third mask register 31. Rank 32 of 24 AND gates , shifters 33 and 48, most significant bit detector 49, counter 47, third prefix Dress register 35. 24 or gates rank 36, 3rd index The box register 37 is omitted. The third colormap register 6 is Receives the same read address as colormap register 4. computer main memory The serial output port provides a stream of input pixels and a 2-byte (Is bit) wide buffer. The shortened input latch 2' is loaded from this bus.

The display processor of FIG. 11 specifically stores the first colormap memory 4 or its storage location. accommodating each individual of a first chrominance-only primary color, such as I or (RY); A second color map memory 5 stores each luminance-only primary color Y in its storage location. A third color map memory 6 stores only the second chrominance at its storage location. It is adapted to operate by accommodating each of the primary colors. As a specific example, the first If the primary color of only chrominance is I, the primary color of only second chrominance is Q, If the primary color is only the first chrominance (RY), then the primary color is only the second chrominance. The color is (B-Y), the two color map memories 4 and 6 have address congestion. Is it possible to merge into a single colormap memory without modification? and the width of the read output is doubled by the number of bit positions.

This equivalence should be taken into account when interpreting the scope of the claims. Single total When a computer-generated figure is used, the color map memory 4.5.6 , part of the field retrace period or (usually) the line retrace period may be rerotted by the town rotor from computer main memory during some part of the time. It's coming.

Displays of characteristics generally associated with camera-generated images may also be processed. Y's A second colormap memory 5 for storing values is used during field retrace. It is preferable that the data be reloaded by downloading from the main memory of the computer. A first color map memory 4 and a third color map memory 4 for storing chrominance values. Memory 6 provides line retrace needed when tracing fields. During the field retrace period, down data from the main memory of the computer is Rerouted by the rotor. 3:4 aspect ratio, 480 effective lines, Displays with square pixels are designed for display devices with a rate of 30 frames per second. The luminance video bandwidth is 640 bits per line, which corresponds to 6M) Iz. Kusel exists. Chrominance is limited to 1.2MHz video bandwidth. Then, for chroma, there are only 128 pixels per line. This number of pixels corresponds to the number of colormap memories that receive the same read address in parallel. chrominance with a 7-bit read address as given by 4 and 6. It is also possible to specify a nonce-only color map.

Colormap memories 4 and 6 are time interleaved during any repeated trace period. Read addresses representing two adjacent scan lines supplied to this when the readout output of these memories can be spatially interpolated. Consider the rate at which buffering memory is loaded prior to zero display processing. or luminance pixels are assumed to be the same as the rate written to the display. , and assuming a line retrace period or a luma pixel period of 128 Ru. Rate buffering for every second line of each field in a two-field frame The 128 read addresses that need to be loaded into programming memory are There will be one line retrace period for this purpose. This applies to masks and and index registers from the random access port of computer main memory. Colormap memory, assuming it is updated during the field trace period. 4 and 6, resulting in abandoning alternate line retrace periods to rewrite 4 and 6. Ru. The rate at which colormap memories 4 and 6 are written also depends on the luminance Assume that the rate is the same as that written to the file or display. Color map memo If entries 4 and 6 have 128 (1 entry) in them, then It takes two scan line periods to completely rewrite them. This is one In general, substantial correlations are found between chrominance vixels over a range of two tree line widths. It is sufficient that the The line retrace period may be similar to some have no trace pixels, or a pair of consecutive line trace periods are the same. It is rare to have no lominance vixels. In this case, for a while The problem arises that the spatial resolution of chrominance must be sacrificed during .

When representations of a nature commonly associated with camera-generated images are processed, color is typically The read address supplied in parallel to map memories 4 and 6 consists of two groups of bits. a first linear encoding to be decoded by a colormap RAM, for example The first group representing the primary colors of chrominance only and the color map RAM6 A second group representing the second linearly coded chrominance-only primaries to be coded. Not included.

This means that the input pixel stream can be thought of as consisting of successive pixels. , each pixel in this case is the luminance-only source of the corresponding position in the image. Consists of a first group of bits representing a color value. The second group of bits in each pixel is Represents one of the two chrominance-only primary color values at the corresponding location in the image. , only the chrominance represented by the second group of bits in each pixel. The primary colors alternate in successive pixels. In other words, at a particular pixel, the bit The second group of pixels represents the primary color values of the first chrominance only; , the second group of bits represents the value of the second chrominance-only primary color and In the cell, the second group of bits represents the value of the first chrominance-only primary color, and so on. , so that only every other pixel is the first chrominance-only primary color. The intervening vixels represent the values of the second chrominance-only primary color.

Using the configuration shown in Figure 11, RAM 4 or the first chrominance-only primary color (e.g. For example, process a pixel containing 8 bits representing ■ or (RY)) and store it in RAM. 7 represents the second chrominance-only primary color (e.g., Q or (B-Y)) The above color map RAM 4 and It is possible to make a verse division multiplex by using 6 and 6. The life at that time This in the video space actually contains chrominance-only primary color information during the trace period. Determine the chrominance-only values for these vixels as accurately as possible.

Do not specify chrominance-only values for pixels that contain no information in the video space. chrominance value for that particular line retrace period, preferably is specified as an 8-bit read address for both color map memories 4 and 6. When setting color map memories 4 and 6 of the formattuff shown in Figure 2. at least as accurate as using an 8-bit read address for each Accuracy of the clock for the above specific line trace period within the chrominance amplitude range. This specifies the lominance value. In other words, the read access is equivalent to 16 bits. It attempts to replace the address capability with an 8-bit read address at most.

The read addresses supplied to color map memories 4 and 6 are chrominance values. Since these read addresses are not linear codes, these read addresses are stored in the color map memory 5. Compared to the read address supplied to the Assuming that the chrominance in the display processor of FIG. The spatial interpolation of the Rather than regarding the read addresses of memories 4 and 6, their color maps - Must be performed for the read output of memories 4 and 6.

The display processor in FIG. 12 is a simplified version of the 313th display processor. . The formatter 19 of the display processor in FIG. 12 has a 24-bit third mask. ・Register 3].

Rank 32 of 24 AND gates, shifters 33' and 48', least significant bit Detector 29, counter 47, third pre-address register 35.24 orage Rank 36. and the third index register 37 are omitted.

The operation is similar to that described with respect to FIG. The constraints on operation described above also apply to the display processor of FIG.

Obtained when colormap memory is reloaded during line retrace. The advantage of the color map operations shown in Figures 1, 2, and 3 is that It is even larger than in These are the serial output ports of the main memory of the computer. These 24-bit wide hashs contain all three color map memories 4, 5, and 6. This makes it easier to write in parallel during line retrace. Use this ability For example, it is possible to create a complex composite image (montage) on the display. I can do it.

Figure 13 shows a display processor of the same general form as the display processor in Figure 1.2.3.11.12. A pair of similar display processors 50, 60 operate in a banked mode of operation. banked According to the behavior.

The display processing speed is twice the speed when the display processor 50 or 60 is used alone. van In parallel operation, input data fed in series is sent to each of multiple data processing paths. The data is split multiplexed and processed individually after each pass has completed processing. Parallel streams of output data are time-division multiplexed into one stream of serial output data. The file is scanned and returned. According to this, the throughput rate of the system can be determined by The processing throughput rate is faster by a factor times equal to the number of individual data processing streams. can do.

The video data is directly stored in the double boat type RA M70, which operates as the computer's main memo. It is supplied from the column output port to the serial-to-parallel converter 71, and the serial-to-parallel converter 71 is Converts video data into 32-bit contiguous blocks on 32-bit bus 72. zero position adjuster 73 (each part of which is connected to the drawing processor 50 and the display processor 6) 0) sets the most significant bit of the output of the position adjuster 73 to Align data to correspond to the most significant bit of the file data. By control circuit 74 The data divider 76, which is a network of controlled multiplexers, has 32 Divide a block of bits into separate pixels. The length of the vixel cord is 2x , and X is in the range from O to 5 (including 0 and 5). The dovetail division is exclusive for all pixel codes. Each separate pixel is by the calculator that keeps the count of pixels or whether each vixel is an even number By including a bit in the data of each pixel above that indicates whether it is an odd number. Numbered modulo 2.

The pixel data or the pixel human-powered graphics of the display processors 50 and 60 therein. If the data does not have more bits than can be stored in switches 52 and 62, The pixel divider 76 loads consecutive even pixels into the pixel input latch 52 and Load the following odd pixels into pixel input latch 62, e.g., latch 5. 2 and 62 each have a capacity of 16 bits. Formattuta 57 and and 67 have short input and third mask ratios, and the rank of the AND gate is short. Formatsuta 7 in Figure 2 except that it is shorter, has a smaller counter, and has a smaller chic. Colormap memory 54,55,56 in 0 display processor 50 which is the same as is a zero display process that stores the blue, red, and green drive signals in digitized form, respectively. Color map memories 64, 65 and 66 in the processor 60 are each digitized. The blue, red, and green drive signals are memorized in the following format. Multiplexer 81.82.83 is Colormap memory 54.55.56 to digital-to-analog converter 84.8 5.86 and select the readout to each input of the digital-to-analog converter. respectively, when the display should be written in response to even pixel data. to analog blue, red, and green drive signals.

Also, the multiplexer 81.82.83 is connected to the color map memory 64.65.6. 6 to each input of DAC84, 8S, and 86, and each DAC should be written to the display in response to odd pixel data, respectively. convert to analog blue, red, and green drive signals.

The data associated with a pixel is collected by one of the pixel input columns 52.62. If the video data has more bits than the display processor are processed by running them in truly parallel manner. In this case, parallel operation is The operations are aligned in time rather than parallel operations with a duration offset of 1 pixel. skewed in time. Do not ignore the speed advantage of hanked motion. In general, this is satisfactory. Most small meters'J The L machine operates at twice the normal horizontal sweep rate when displaying graphics or text information. 0 graphics or text information, which doubles the horizontal resolution. The data is generally coded into 2-3 bits per pixel format. Ru. The large number of bits per pixel format is generally used for camera-generated images or computer simulation of such images. Almost without exception, these images are displayed at a normal horizontal sweep rate.

During true parallel operation, the concept of even or odd pixels is not used; Width resolution primary color data (i.e. blue and red) is routed through a display processor. , high amplitude resolution color data (i.e. green) is directed through a display processor. It will be done. Here, multiplexer 81 generates pre-drive signals for all pixels. Select the color map memory 54 read out to the input of the DA C84 to The select multiplexer 82 generates the red drive signal for all pixels. The color map memory 55 to be read out to the input of the DA C 85 is selected for this purpose.

Multiplexer 83 connects D to generate line drive signals for all pixels. A Select the colormap memory 66 to be read to the input of C86. true average Column operation is Y, 1. When applied to the operation of Q, a certain display processor processes Y. and another display processor processes I3 and Q.

Assuming the computer keeps pixel counts modulo 2, the first 3, the multiplexers 81, 82, 83 are controlled by the control circuit 74. It is shown as. Even and odd numbers of pixels are 1 of the data for each pixel. If the bit is coded, this bit will instead be sent to multiplexer 81.8Z. , 83.

Series-to-parallel converter 71. Vertical VC connection of position adjuster 73 and data divider 76 The proper operation of depends on the length of the pixel coat, which is 21 bits long, where m is a positive integer from 0 to 5 (inclusive). This will cause an even number of pixels to The cell code is adjusted to fit each 4 bytes (32 bits) of the serial-to-parallel converter 71. I'm doing it. Regarding the code length, the converter 71 is a straight line that shifts regularly. Using column input/parallel output registers and also using pixel input latches 52 and 62. This function is used to operate as a “pixel grabber” (a device that grabs pixels). By timing the loading of these pixel input latches 52 and 62. It is possible to provide more flexibility. The load is the most significant bit of the pixel code. The zero display process performed at each time in the most significant bit position of the output of converter 71 When banked operation of latches 50 and 60 is employed, latches 52 and 6 2 is a 0 display process that is loaded alternately with even and odd pixels, respectively. When latches 50 and 60 are operating in true parallel to each other, latches 52 and 62 are rotated in parallel for each pixel.

Figure 14 shows how the display processor described in relation to Figures 1.2 and 3.11.12 is used. This shows how it is connected to the display device. In particular, the connection to the picture tube 90 I will explain about it. The readout output from color map memory 4, 5.6 is In order to selectively lead through the interpolator 92 or avoid this spatial interpolator 92. Switch 91 is used for this purpose. Bankin as explained in Figure 13. When the color map memory readout map is used, the color map memory readout map is placed before switch 91. A multiplexer is provided. When this form of processing is performed, spatial interpolation Circuit 92 performs spatial interpolation after display processing so that the pixels are digitized samples. When written in pull format, it is convenient to perform spatial interpolation. Spatial interpolation This is preferably done in both vertical and horizontal directions of the image field. Transver with low-pass characteristics in both spatial dimensions Monkey filter is done. As explained earlier in this specification, the computer main It is convenient to use rate buffering memory between the memory and the display processor. be. According to this, the spatially adjacent pixel samples required by the spatial interpolator 92 are Each line to be fed to the display processor to generate a group of samples in succession. Alternately select samples from two adjacent lines of pixel samples. can be interleaved in time.

Digital-to-analog converters 93,94,95 are connected to color map memories 4,5. Three of the pixels represented in the form of digitized samples supplied from 6 Converting the parallel streams into each successive analog signal. Switch 96 The log signal is passed through the color matrix circuit 97 or is used to selectively guide the circuits around the network. Digital to analog converter If the analog signal from 93.94.95 is not blue, red, or green, switch 9. 6 directs these signals through a color matrix circuit 97 to produce blue, red, Convert to green traffic light. Conversely, the color matrix is Generally avoid multiplexing in digital debt is desirable.

Regarding the color matrix circuit 97, digital-to-analog converters 93.94. To simplify 95, we use positive numbers to represent digital chrominance-only primary color components. Washuka is desirable. In addition, these digital chrominance-only primary color components are The dynamic range available in the number of bit positions whose maximum amplitude represents it scaled in amplitude to more completely fill the Rahmap memory 4, 5.6 and digital-to-analog converter 93.94.9 5 can be preserved. If these measures are taken , I and Q, or (R-Y) and (B-Y), such as rominance only In order to return the primary color components to signal quantities, the color matrix circuit 97 This includes means for removing offsets in the primary color components of the These components are renormalized and combined with the luminance-only primary color component to create an additive color mixture of three primary color components. This is done before color is generated.

Blue and red amplified by video amplifiers 101, 102, and 103.

The green analog signal is supplied to the color picture tube 90 as a drive signal. video amplification It is desirable that the mutual conductance of the devices 101, 102, and 103 is linear. stomach.

After display processing, the spatial interpolator 92 can be removed if not needed, or The selection switch 91 can be replaced with a wired connection. color map ・One of the memories 4.5.6 always stores the primary color values of luminance only, the other The two colormap memories each store chrominance-only primary color values. The color matrix circuit 97 is always required. In that case select Without switch 95, circuit 97 is permanently connected.

Color map memories 4.5 and 6 always remember the values of additive color 3IIX colors. If there is, the color matrix circuit 97 can be removed and the 1 selection switch 91 Instead, digital-to-analog converters 93, 94, 95 and video amplifiers 101, 1 02.103 can be used.

Next, consider how to connect the computer main memory to the pixel input latch 2.2'. I understand. The main memory has a pixel input latch 2.2' with respect to the bit position (e.g. (for example, a 32-bit wide area bus). supply power. Parallel storage registers are provided at the outputs of two consecutive main memories. There is. The inputs of the parallel storage registers are multiplexed and the outputs of the parallel storage registers Power is also multiplexed. This multiplex is a contiguous controlled by a modular counting of accesses. Therefore, the penultimate lord The memory output and the last main memory output are organized as bitmaps in main memory. In consecutive 64-bit wide windows scanned along a scan line in pixel memory. are used at the same time. The shifter moves these temporally parallel data one pixel at a time. Shift so that the positions are aligned one by one.

Shifts are a modular count of accesses from main memory and bits per pixel coat. Controlled according to information about the number of positions. (bits per pixel code The masking process (controlled by information about the number of positions) In order to load l pixels at a time into either pixel 2 or 2', This is done to fill the bit position that has been lost with zero with zero.

In a more practical design, one computer main memory readout and preceding computations A parallel storage register is provided for read output of the main memory. According to this, average Easy to use with more complex input and output multiplexers for column storage registers can be executed. The pixels are then used to align the pixels. The NW integer can be narrower in terms of the number of bit position inputs, and The shift in position will be smaller.

As mentioned earlier in the specification, any output of colormap memory 4.5.6 When performing spatial interpolation of force, the Bixel Coefficient described in the above two bar graphs is used. The circuit that multiplexes the output is modified to include rate buffering memory. It's okay.

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Claims (55)

[Claims] (1) Address p bits (p is a positive integer) at the first read address during the read period. a first color map memory that can be accessed; a first prefix address for temporarily storing a first prefix address of p bits; register and the first read address from the first prefix address of the p bits. the means by which it occurs; Can be addressed with the second read address of q bits (q is a positive integer) during the read period a second colormap memory capable of a second prefix address register for temporarily storing a second address of q bits; Star and means for generating the second read address from the q-bit second prefix address; and, at least (p+q) bits wide, into which the data for each pixel is loaded serially a pixel input latch with From the contents of the pixel input latch above, the first number of bits from adjacent bit positions ( the first number is not greater than p; A first number of bits should be temporarily stored in said first prefix address register. the first prefix address as at least a part of the first prefix address; the first prefix address; means for supplying zero as all remainders of; the second number of bits from the adjacent slot bit position from the contents of the pixel input latch above; (the second number is not greater than q), which bit position is Which bit positions are included in the second number above, regardless of whether they are included in the first number above. means in the form of selecting whether the A second number of bits should be temporarily stored in the second prefix address register. and the second prefix address as at least a part of the second prefix address. the second prefix address; means for providing zeros as all remainders of the display processor. (2) Add r bits (r is a positive integer) at the third read address during the read period. a third color map memory that can be accessed; A third prefix address for temporarily storing a third prefix address of r bits. Generate a third read address from the register and the r-bit prefix address. means and From the contents of the above pixel input latch, the third number of bits from the adjacent bit position (the third number is not greater than r); Which bits are not included in the first number and second number, respectively? means in the form of selecting whether the target position should be included in the third number; A third number of bits should be temporarily stored in the third prefix address register. and the third prefix address as at least a part of the third prefix address. The third pre-fold address is supplied in register-aligned format. and means for supplying zeros as all remainders of the input latch. A display screen according to claim (1) having a width of at least (p+q+r) bits. Rocessa. (3) Said means for generating said first read address comprises a first read address having p bits. a first index register storing an index; The first index is temporarily stored in the first prefix address register. means for generating a first read address by combining with the first prefix address; A display processor according to claim (2). (4) The above-mentioned method for synthesizing the above-mentioned first index and first prefix address. a bit temporarily stored in said first prefix address register and said first prefix address register; 1 and each bit of the index register to obtain the above first read address. The display according to claim (3), consisting of the first rank of the or gate that generates the response. processor. (5) The means for generating the second derived address is a second derived address having q bits. a second index register storing an index of; temporarily stored in the second index and the second prefix address register. means for generating the second read address by combining the second prefix address and the second prefix address A display processor according to claim (3), comprising: (6) The means for synthesizing the second index and the second prefix address, The bits temporarily stored in the second prefix address register and the bits temporarily stored in the second prefix address register. Is it the second rank of OR gate that takes an OR with each bit of the index register? The display processor according to claim (5), comprising: (7) The means for generating the third read address includes a third read address having r bits. a third index register storing an index of; Temporarily stored in the third index and the third pre-fold address register. means for generating the third read address by combining the third prefix address and the third prefix address A display processor according to claim (5), comprising: (8) The means for synthesizing the third index and the third prefix address, The bits temporarily stored in the third prefix address register and the bits temporarily stored in the third prefix address register. From the third rank of the OR gate that takes an OR with each bit of the index register. A display processor according to claim (7). (9) The means for generating the first read address is configured to generate the first prefix address. The first input has a number of bits corresponding to the number of bits in all remaining parts of the a first index register storing the index; and the first index; and a first prefix address temporarily stored in the first prefix address register. 3. The display processor according to claim 2, further comprising means for synthesizing the. (10) The means for synthesizing the first index and the first prefix address is All remaining bits of the first prefix address and the first index an OR gate that generates the first read address by performing an OR operation with the bit of the first read address; A display processor according to claim 9, comprising a first rank of. (11) The means for generating the second read address is configured to generate the second prefix address. a second input with a number of bits corresponding to the number of bits in all remaining parts of the address. a second index register storing the index; and the second index; is the second prefix address temporarily stored in the second prefix address register. and means for generating the second read address by combining 9) The display processor as described. (12) The means for synthesizing the second index and the second prefix address is , the rest of all of the above of the second prefix address and the second index of the above A second OR gate that performs an OR with the bit to generate the second read address. The display processor according to claim 11, comprising a rank of: (13) The means for generating the third read address is configured to generate the third prefix address. A third element with a number of bits corresponding to the number of bits in all remaining parts of the a third index register that stores the index; and a third index register that stores the index; Combined with the third prefix address temporarily stored in the third prefix address register above. and generating the third read address. built-in display processor. (14) The means for synthesizing the third index with the third prefix address is configured to combine the third index with the third prefix address. All the remaining bits of the prefix address and the bits of the third index above The third gate of the OR gate generates the third read address by performing an OR with the third read address. 8. A display processor according to claim 7, wherein the display processor comprises a link. (15) The above aligned format has alignment in the direction of increasing weight. The display processor according to claim (2), which is a format. (16) The above aligned format has alignment in the direction of decreasing weight. The display processor according to claim (2), which is a format. (17) said method for selecting a first number of bits from the contents of said pixel input latch; The stage is always of the form that selects the most significant bit in the pixel input latch above. , a display processor according to claim (2). (18) said method for selecting a first number of bits from the contents of said pixel input latch; The stage is always of the type that selects the least significant bit in the pixel input latch. , a display processor according to claim (2). (19) Color picture tube, successive digital readings from said first, second and third colormap memories; The output stream is divided into three successive analogues, each representing the three primary color components of the additive color mixture. a digital-to-analog conversion means for converting the digital-to-analog signal into a digital-to-analog signal; amplified blue, red, and green signals in response to continuous analog signals provided by the first, second and third video amplifiers for coupling drive signals to the color picture tube; A display processor according to combined claim (2). (20) Continuous color maps read from the first, second and third color map memories. Digital analyzer for converting the digitized output stream into each analog signal A log conversion means, These analog signals are converted into analog signals representing each of the three additive primary color components. a display processor according to claim (2) combined with a color matrix circuit for converting Sessa. (21) Before conversion into each analog signal by the digital-to-analog conversion means is read from at least one of the first, second, and third color map memories. A display process according to claim (20), comprising means for applying spatial interpolation to the output sa. (22) a color picture tube; A series of signals supplied from said analog-to-digital conversion means to said video amplifier. Amplified blue, red, and green drive signals in response to analog signals are supplied to the color picture tube. first, second and third amplifiers for supplying display processor. (23) Consists of a combination of means for banked operation of multiple display processors A plurality of display processors according to claim (2). (24) Banked operation of paired display processors or paired display processors Claim (2) comprising means for selectively providing true parallel operation of the A companion display processor. (25) A third memory addressable by the first read address during reading. 2. A display processor as claimed in claim 1, including a rahmap memory. (26) The means for generating the first read address includes a first address having p bits. a first index register storing an index; temporarily stored in the first index and the first prefix address register. means for generating the first read address by combining the first prefix address and the first prefix address; The display processor according to claim (25), comprising: (27) The means for synthesizing the first index and the first prefix address is The bit temporarily stored in the first prefix address register and the first index The above first read address is generated by ORing with each bit of the box register. The display process according to claim (26), comprising a first rank of an or gate that Sa. (28) The means for generating the second read address is configured to generate a second read address having q bits. a second index register storing an index; temporarily stored in the second index and the second prefix address register. means for generating said second read address by combining said second prefix address with said second prefix address; The display processor according to claim (27), comprising: (29) The means for synthesizing the second index and the second prefix address is , the bit temporarily stored in said second prefix address register and said second prefix address register. The above second output address is obtained by ORing with each bit of the index register. A display screen according to claim (28), comprising a second rank of OR gates that occur. Rocessa. (30) The means for generating the second read address comprises a second read address having p bits. a second index register storing an index of 2; temporarily stored in the second index and the second prefix address register. and a means for synthesizing the second prefix address. Display processor. (31) The means for synthesizing the second index and the second prefix address is , the bit temporarily stored in said second prefix address register and said second The second rank of or gates that takes an or with each bit of the index register of A display processor according to claim 30, comprising: (32) The means for generating the first read address includes the first prefix address. The first input has a number of bits corresponding to the number of bits in all remaining parts of the address. a first index register storing the index; and the first index; is the first prefix address temporarily stored in the first prefix address register. 26. A display processor according to claim 25, comprising means for compositing. (33) The means for synthesizing the first index and the first prefix address is , all remaining bits of the first prefix address and the first input An or game that generates the first read address by performing an OR with the bit of the index. 33. A display processor according to claim 32, comprising a first rank of ports. (34) The means for generating the second read address is configured to generate the second prefix address. a second input with a number of bits corresponding to the number of bits in all remaining parts of the address. a second index register storing the index; and the second index; and a second prefix address temporarily stored in the second prefix address register. and means for generating the second read address by synthesizing the second read address. 32) The display processor as described. (35) The means for synthesizing the second index and the second prefix address is , all the remaining bits of the second prefix address and the second input An or game that generates the second read address by performing an OR with the bit of the index. 35. A display processor according to claim 34, comprising a second rank of ports. (36) The means for generating the second read address is configured to generate the second prefix address. a second input with a number of bits corresponding to the number of bits in all remaining parts of the address. a second index register storing the index; and the second index; and a second prefix address temporarily stored in the second prefix address register. and means for generating said second read address. 25) The display processor as described. (37) The means for synthesizing the second index and the second prefix address is , all the remaining bits of the second prefix address and the second index. The claims ( 36) The display processor as described. (38) The above alignment format is a file whose alignment is in the direction of increasing weight. 26. A display processor according to claim 25, which is a format. (39) The above alignment format is a file whose alignment is in the direction of decreasing weight. 26. A display processor according to claim 25, which is a format. (40) said method of selecting a first number of bits from the contents of said pixel input latch; The stage is of the form that always selects the most significant bit of the pixel input latch above. , a display processor according to claim (25). (41) said method for selecting a first number of bits from the contents of said pixel input latch; The stage is of the form that always selects the least significant bit of the pixel input latch. , a display processor according to claim (25). (42) Sequences read from the first, second and third colormap memories. A digital converter that converts the digitized readout output stream into each analog signal. analog conversion means; These analog signals are converted into analog signals each representing each of the three additive primary color components. according to claim (25), consisting of a combination with a color matrix circuit that converts Display processor. (43) Before conversion into each analog signal by the digital-to-analog conversion means from at least one of the first, second and third colormap memories. as claimed in claim (42), comprising means for applying spatial interpolation to the read output obtained by Display processor. (44) Color picture tube, in response to continuous analog signals supplied from the analog-to-digital conversion means. A second circuit for supplying amplified blue, red and green drive signals to the color picture tube. 1, a second video amplifier, and a third video amplifier. Rocessa. (45) In combination with means for providing banked operation of the plurality of display processors A plurality of display processors according to claim (25). (46) Banked operation of paired display processors or the paired display processors Claims (1) in combination with means for selectively providing true parallel operation of the 25) A pair of display processors as described. (47) first, second and third color map memories; and the first, second and third color map memories; a color display image in response to the output read from each of the third colormap memories; means for generating an image; means for providing pixel data encoded into a number of bit words; Determines the read address from a selected portion of bits in each word of pixel data. a means for generating a read address for the first color map memory; Selected portions of each word of pixel data that are from a selected portion of the bits in each word for the second colormap memory. means for generating a read address; The pixel data from which the read address for the first colormap memory is generated. a selected portion of the bits in each word of the data, and a minor second color map. in each word of pixel data for which the read address for the top memory is generated. Selection of bits in each word of pixel data that differ from the selected portion of bits A read address for the third color map memory is generated from the a display processor comprising: means; (48) Responding to the read output of the first, second and third color map memories. The means for generating a color display image is based on the first and third color map memo. The output read from the second color map memory and the output read from the second color map memory are The claimed invention includes means for adding or subtracting to combine the red, green and blue drive signals. A display processor according to range (47). (49) First, second and third colormap memories and some bits of memory. means for providing coded pixel data to the code; the first color from a selected portion of the bits in each word of pixel data; means for generating a read address for the mapped memory; The pixel data from which the read address for the first colormap memory is generated. Each word of pixel data differs from a selected portion of bits in each word of data. reading out a selected portion of the bits in the second colormap memory; a means for generating an address; and a means for generating an address for said second colormap memory; Selected portions of bits in each word of generated pixel data The third color map is extracted from selected portions of the bits in each word of cell data. means for generating a read address for the memory; outputs read from the first and third colormap memories and the second colormap memory; Red and green are synthesized by addition or subtraction processing with the readout output of the color map memory. , and means for generating a blue drive signal. (50) First, second and third colormap memories and some bits of memory; means for providing coded pixel data to the code; from a selected portion of the bits in each word of pixel data. means for generating a read address for the color map memory of No. 3; The pixel data from which the read address for the first colormap memory is generated. Each word of pixel data differs from a selected portion of bits in each word of data. reading out a selected portion of the bits in the second colormap memory; means for generating addresses and reading from said first and third color map memories; The output output and the readout output of the second color map memory are combined to create means for synthesizing by addition or subtraction processing to generate green and blue drive signals; A display processor. (51) Color map addressable with multiple (several m) bit read addresses memory and a plurality of each (the number mm is not more than n and at least sometimes less than n) ) means for generating a continuous pixel code having bits; The m bit positions of each pixel code are stored in the colormap memory. means for supplying the read address as m adjacent pit positions; 2n-m as the position of the remaining n-m bits of the map memory read address means for providing a selection of bit patterns; Programmably change said selected one of said 2n-m bit patterns. A display processor consisting of a combination of a means for converting (52) The m adjacent bit positions of the color map memory input address The position is the least significant bit position of the above color map memory input address, as claimed. A display processor according to range (51). (53) The m adjacent bit positions of the color map memory input address The position is the most significant bit position of the above color map memory input address, as claimed. A display processor according to range (51). (54) Color map addressable with multiple (number n) bit read addresses memory and from a series of consecutive pixel codes, each set extending from 0 to an upper value. means for generating any selected number of sets of pixel codes and the numbers associated with the generated pixel codes and the set to which they belong. and means for generating the read address for the color map memory, The numbers associated with each of the above pixel code sets are to generate read addresses for individual portions of the colormap memory above. The display processor selected. (55) During the read period, the read address of p bits (p is a positive integer) a first addressable colormap memory; Can be addressed by a read address of q bits (q is a positive integer) during the read period a second colormap memory capable of has a width of at least (p+q) bits into which the data for each pixel is loaded a pixel input latch and a first and second number from the contents of said pixel input latch; means for selecting bits of; The bits of said first and second numbers are stored in said first and second color map memories. and means for combining each as a read address, The bits of the pixel input latch included in the first number of bits are It is not affected by the pixel input latch bits included in the number of bits. A display processor.