JPH0250713B2 - - Google Patents
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- Publication number
- JPH0250713B2 JPH0250713B2 JP60125894A JP12589485A JPH0250713B2 JP H0250713 B2 JPH0250713 B2 JP H0250713B2 JP 60125894 A JP60125894 A JP 60125894A JP 12589485 A JP12589485 A JP 12589485A JP H0250713 B2 JPH0250713 B2 JP H0250713B2
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- JP
- Japan
- Prior art keywords
- current
- value
- converter
- transistor
- reference signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- Direct Current Feeding And Distribution (AREA)
- Dc-Dc Converters (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は基準値と出力制御値との差を増幅して
得られた値を電流基準信号とし、該電流基準信号
とスイツチング素子の毎導通時の電流積分値とを
一致するよう制御するDC−DCコンバータユニツ
トを複数台並列運転するDC−DCコンバータ装置
に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention uses a value obtained by amplifying the difference between a reference value and an output control value as a current reference signal, and uses the current reference signal and each conduction of a switching element as a current reference signal. The present invention relates to a DC-DC converter device in which a plurality of DC-DC converter units are operated in parallel to control the current integral value at the same time as the current integral value.
停電すると影響の大きなシステムの電源は並列
冗長運転されるが、並列運転中の1台が故障した
場合故障機を速やかに検出し並列運転より切り離
し、修理する必要がある。
The power supplies of systems that would be significantly affected by a power outage are operated in parallel and redundantly, but if one unit operating in parallel fails, it is necessary to promptly detect the faulty unit, disconnect it from parallel operation, and repair it.
従来、直流電圧を変換するDC−DCコンバータ
の並列運転での事故機の判別方法には、出力電流
の分担割合を比較する方法、出力整流ダイオード
の入出力電圧差を比較する方法等がある。 Conventionally, there are methods for determining the faulty aircraft when DC-DC converters that convert DC voltage are operated in parallel, such as comparing the sharing ratio of output current and comparing the input and output voltage difference of output rectifier diodes.
しかし、出力電流の分担割合を比較する方法は
電流検出用の変流器が必要で、しかも並列運転台
数の変更に対して追従する回路が必要であり複雑
であるという欠点がある。
However, the method of comparing the sharing ratio of output current requires a current transformer for current detection, and also requires a circuit to follow changes in the number of parallel operating units, and is complicated.
また、出力整流ダイオードの入出力電圧差を比
較する方法は、上記出力整流ダイオードに電流が
流れてさえいればダイオードの電圧降下は殆ど一
のため負荷分担割合に大きな不平衡が生じても出
力さえ供給していれば検出できないという欠点が
ある。 In addition, the method of comparing the input and output voltage difference of the output rectifier diode is based on the fact that as long as current flows through the output rectifier diode, the voltage drop across the diode is almost the same, so even if there is a large imbalance in the load sharing ratio, the output will not change. The disadvantage is that it cannot be detected if it is supplied.
本発明は以上の欠点を除去するために、基準値
と出力制御値との差を増幅して得られた値を電流
基準信号とし、該電流基準信号とスイツチング素
子の毎導通時の電流積分値とを一致するよう制御
するDC−DCコンバータユニツトを複数台並列冗
長運転するDC−DCコンバータ装置において、上
記DC−DCコンバータユニツト毎に上記スイツチ
ング素子の電流の和の平均値と上記電流基準信号
とを比較し、一定以上の差異が一定期間持続した
DC−DCコンバータユニツトを故障と判断し並列
運転より切り離す選択遮断回路を備えたことを特
徴とするDC−DCコンバータ装置を提供するもの
である。
In order to eliminate the above drawbacks, the present invention uses a value obtained by amplifying the difference between a reference value and an output control value as a current reference signal, and uses the current reference signal and a current integral value at each conduction of a switching element. In a DC-DC converter device in which multiple DC-DC converter units are operated redundantly in parallel, the average value of the sum of the currents of the switching elements and the current reference signal are determined for each DC-DC converter unit. compared, and a difference above a certain level persisted for a certain period of time.
The present invention provides a DC-DC converter device characterized by being equipped with a selective cutoff circuit that determines that a DC-DC converter unit is in failure and disconnects it from parallel operation.
第1図は本発明の一実施例を示す図である。同
図において、スイツチング素子であるトランジス
タ1,1′を駆動回路2,2′で駆動しスイツチン
グさせ直流電源3の電圧Eiを交流電圧に変換し、
トランス4で絶縁・変圧、整流回路5で整流、コ
ンデンサC1で平滑し、ダイオード6を介して負
荷7に電力を供給する。トランジスタ1,1′に
同時にオン期間を設けるとトランス4の巻数比を
1としたとき出力電圧は入力電圧より高くなるの
で昇圧モードという、逆に同時オフ期間を設ける
と出力電圧は入力電圧より低くなるので降圧モー
ドという。第2図は第1図の昇圧モード時の動作
波形図でありイはトランジスタ1ロはトランジス
タ1′ハはリアクトルLニはトランス4の2次の
夫々電流波形を示す。先ず時刻t1でトランジスタ
1,1′が同時にオンするとトランス4は短絡と
なり入力電圧は全てリアクトルLで負担する。リ
アクトルLの電流はEi/Lの傾きで上昇し各トラ
ンジスタに分流する。次に時刻t2でトランジスタ
1′がオフすると、リアクトルLの電流は全てト
ランジスタ1に流れ、トランス4は短絡を解かれ
2次側に電力を供給する。この時リアクトルの電
流は出力電圧をEpとすると(Ep−Ei)/Lの傾き
で下降する。時刻t3で再び同時オンとなると時刻
t1のときと同様にリアクトルLの電流は上昇す
る。時刻t4でトランジスタ1がオフすると時刻t2
のときと同様にトランジスタ1′の電流はリアク
トルLの電流が全て流れ負荷7に電力を供給す
る。尚、リアクトルLの2次側はダイオード8で
阻止され開放と等価である。この昇降圧コンバー
タの制御方法は、出力電圧を抵抗器R1,R2で降
圧し基準電源9の電圧との誤差電圧を誤差増幅器
10で増幅し、ホトカプラ等の信号絶縁伝達回路
11でコンバータ側へ電流基準信号として送り出
す。電流基準信号として送り出すのは電流分担が
均等にでき、並列運転台数に影響を受けないから
である。一方、トランジスタ1,1′の電流を変
流器12,12′で検出し変換回路13,13′で
電流源14,14′に変換した電流でコンデンサ
C2,C2′を充電しコンパレータ24,24′で電流
基準信号と比較し、該電流基準信号と一致した時
点でトランジスタ1,1′をオフするように制御
する。従つてトランジスタの電流をi(t)、トラ
ンジスタ電流を電流源に変換する変流比をN、電
流基準信号の電圧をEr、オン期間をτ、周期をT
とすると、コンデンサC2の電圧eC2は次式のよう
になる。
FIG. 1 is a diagram showing an embodiment of the present invention. In the figure, transistors 1 and 1', which are switching elements, are driven and switched by drive circuits 2 and 2' to convert voltage E i of a DC power source 3 into an AC voltage,
The transformer 4 insulates and transforms the voltage, the rectifier circuit 5 rectifies, the capacitor C1 smoothes, and the diode 6 supplies power to the load 7. If transistors 1 and 1' have simultaneous on periods, the output voltage will be higher than the input voltage when the turns ratio of transformer 4 is 1, so it is called boost mode. Conversely, if simultaneous off periods are provided, the output voltage will be lower than the input voltage. Therefore, it is called step-down mode. FIG. 2 is an operating waveform diagram in the step-up mode shown in FIG. First, at time t1, when transistors 1 and 1' are turned on simultaneously, transformer 4 is short-circuited and all input voltage is borne by reactor L. The current in the reactor L increases with a slope of E i /L and is divided into each transistor. Next, when the transistor 1' is turned off at time t2 , all the current in the reactor L flows to the transistor 1, and the transformer 4 is disconnected from the short circuit and supplies power to the secondary side. At this time, the current in the reactor decreases at a slope of (E p −E i )/L, where E p is the output voltage. When they turn on simultaneously again at time t 3 , the time
The current in the reactor L increases in the same way as at t1 . When transistor 1 turns off at time t 4 , time t 2
As in the case of , all of the current of the reactor L flows through the transistor 1' and supplies power to the load 7. Note that the secondary side of the reactor L is blocked by the diode 8 and is equivalent to being opened. This buck-boost converter control method involves stepping down the output voltage using resistors R 1 and R 2 , amplifying the error voltage with respect to the voltage of the reference power supply 9 using an error amplifier 10 , and using a signal isolation transmission circuit 11 such as a photocoupler on the converter side. as a current reference signal. The reason why it is sent as a current reference signal is that the current can be shared evenly and is not affected by the number of parallel operating units. On the other hand, the current of the transistors 1 and 1' is detected by the current transformers 12 and 12', and the converted current is converted to the current sources 14 and 14' by the conversion circuits 13 and 13'.
C 2 and C 2 ' are charged and compared with a current reference signal by comparators 24 and 24', and when they match the current reference signal, transistors 1 and 1' are controlled to be turned off. Therefore, the current of the transistor is i(t), the current transformation ratio for converting the transistor current into a current source is N, the voltage of the current reference signal is E r , the on period is τ, and the period is T
Then, the voltage e C2 of capacitor C 2 is as follows.
eC2=1/C2∫〓pi(t)/Ndt=Er
また、トランジスタ電流の平均値Iaは、オフ期
間の電流が零であるから
Ia=1/T∫T pi(t)dt=1/T∫〓pi(t)dt
となり、次式が導かれる。 e C2 = 1/C 2 ∫〓 p i(t)/Ndt=E r Also, the average value I a of the transistor current is I a = 1/T∫ T p i( t) dt=1/T∫〓 p i(t) dt, and the following equation is derived.
Er=Ia/NT1/C2 ……(1)
一方、コンデンサC3の電流eC3はトランジスタ
1,1′の電流i1,i1′を変流器12,12′で検出
し変換回路13,13′で電流源15,15′に変
換した電流を抵抗器R3,R4に流し、電流i1とi2の
平均値は等しく、コンデンサC3が充分に大きい
とすれば
eC3=1/T∫T pi1+i2/N(R3+R4)dt=
2×Ia/N(R3+R4)……(2)
となり、(1)式と(2)式の関係により異常を検出する
ことができる。 E r = I a /NT1/C 2 ... (1) On the other hand, the current e C3 of the capacitor C 3 is converted by detecting the currents i 1 and i 1 ' of the transistors 1 and 1 ' by the current transformers 12 and 12'. If the current converted by circuits 13 and 13' into current sources 15 and 15' flows through resistors R 3 and R 4 , and the average values of currents i 1 and i 2 are equal, and capacitor C 3 is sufficiently large, e C3 = 1/T∫ T p i 1 + i 2 /N (R 3 + R 4 )dt=
2×I a /N(R 3 +R 4 ) (2), and an abnormality can be detected by the relationship between equations (1) and (2).
正常時トランジスタ1,1′に流すべき電流の
平均値をIrとしたとき、トランジスタの電流が
(1−r)Irより小さくなるときに不足電流、(1
+r)Irより大きくなるときに過電流とし、夫々
コンパレータ16,17で検出すると次式が成り
立つ。 When the average value of the current that should flow through transistors 1 and 1' during normal operation is I r , when the current of the transistor becomes smaller than (1 - r) I r , there is an undercurrent, (1
+r) When it becomes larger than I r , it is considered an overcurrent, and when detected by the comparators 16 and 17, the following equation holds true.
2(1−r)Ir/N(R3+R4)=Er=Ir/N・T/C3…
…(3)
2(1+r)Ir/N・R4=Er=Ir/N・T/C3 ……(4)
(3)、(4)式より
R3=r/1−r2・T/C3 ……(5)
R4=T/2(1+r)C3 ……(6)
が求まる。従つて(5)、(6)式よりR3,R4を適当に
選ぶことにより、不平衡電流rを任意に変えるこ
とができ任意の不平衡で異常を検出できる。更に
(5)、(6)式にはIrは含まれないため負荷電流には影
響されず任意の負荷電流で検出することができる
ことがわかる。2(1-r)I r /N (R 3 + R 4 ) = E r =I r /N・T/C 3 ...
…(3) 2(1+r)I r /N・R 4 = E r =I r /N・T/C 3 …(4) From equations (3) and (4), R 3 = r/1−r 2・T/C 3 ...(5) R 4 =T/2(1+r)C 3 ...(6) is found. Therefore, by appropriately selecting R 3 and R 4 from equations (5) and (6), the unbalanced current r can be changed arbitrarily, and an abnormality can be detected at any unbalance. Furthermore
Since Ir is not included in equations (5) and (6), it can be seen that it is not affected by the load current and can be detected at any load current.
一方、前述した基準値と出力制御値との誤差値
を電流基準とし、トランジスタの毎導通時の電流
積分値に一致するように制御するコンバータを並
列運転した場合、基準値は並列運転台数に追従し
て変化する。例えば基準値を出力電圧基準とし出
力制御値を出力電圧としたコンバータをN台並列
運転し負荷に電力を供給しているとき1台切り離
すと、切り離す前の電流をそのまゝ負荷に供給す
ると負荷電流はN−1/Nとなり減少する。すると
出力電圧はN−1/Nに減少し出力電圧基準との差
が増加し誤差値(電流基準)が増加する。この誤
差値と各コンバータのトランジスタの毎導通時の
電流積分値を一致するよう制御するので各コンバ
ータのトランジスタの電流積分値は出力電圧基準
と出力電圧とが等しくなるまで増加する。逆に運
転台数が増えると負荷電流が増加し出力電圧が上
昇し電流基準が下がり各コンバータのトランジス
タの電流積分値が下がり出力電流基準と出力電圧
とが一致する。このように電流基準信号は並列運
転台数に追従するため並列運転台数に応じて不平
衡検出回路を操作することなく不平衡を検出でき
る。異常を検出後オア論理回路18を介し、時限
回路19で時限をとり、制御回路20へ異常信号
を送出しコンバータを停止すると同時にトリツプ
コイル21を駆動して入力ブレーカ22を遮断す
る。コンバータ23停止後他の正常なコンバータ
23′からの流れ込みはダイオード6で防ぐ。尚、
異常検出後時限をとるのは起動時や負荷急変時等
過渡的に負荷分担の不均衡が生じた時動作させな
いためである。 On the other hand, when converters are operated in parallel using the error value between the aforementioned reference value and output control value as the current reference and are controlled to match the current integral value at each conduction of the transistor, the reference value follows the number of units operated in parallel. and change. For example, when N converters are operated in parallel with the reference value as the output voltage reference and the output control value as the output voltage and power is supplied to the load, if one converter is disconnected, if the current before disconnection is supplied to the load as it is, the load The current becomes N-1/N and decreases. Then, the output voltage decreases to N-1/N, the difference from the output voltage reference increases, and the error value (current reference) increases. Since this error value is controlled to match the current integral value of the transistor of each converter at each conduction, the current integral value of the transistor of each converter increases until the output voltage reference and the output voltage become equal. Conversely, when the number of operating units increases, the load current increases, the output voltage increases, the current reference decreases, and the current integral value of the transistor of each converter decreases, so that the output current reference and the output voltage match. In this way, since the current reference signal follows the number of parallel operating units, unbalance can be detected without operating an unbalance detection circuit according to the number of parallel operating units. After detecting an abnormality, a time limit circuit 19 sets a time limit via an OR logic circuit 18, and sends an abnormality signal to a control circuit 20 to stop the converter and at the same time drive a trip coil 21 to shut off an input breaker 22. After converter 23 is stopped, diode 6 prevents inflow from other normal converters 23'. still,
The reason for setting a time limit after detecting an abnormality is to prevent operation when transient imbalances in load sharing occur, such as during startup or sudden changes in load.
一方、不均衡の割合は軽負荷や無負荷時も変ら
ないため不平衡の絶対量が小さくとも異常として
しまう。例えばr=0.2とし全負荷で100Aを基準
とすると全負荷時は20Aの過不足で故障である
が、50Aのときは10A,10Aのときは2A、1Aの
ときは0.2Aで故障となる。負荷変数が僅少であ
り、無負荷や軽負荷にならない場合はこれで良い
が、そうでない場合は部品のばらつき等によりあ
る程度の不平衡は生じるため軽負荷になると異常
でないのに遮断してしまうことがある。これを防
止するためには第3図に示すように検出値に絶対
値Jなる電流を加減すればよい。不足電流はJな
る電流を抵抗器R5に流してやれば良くR5=T/
2C2(1−r)とすればトランジスタ電流が正常
時よりrIr+J不足するときにコンパレータ16
は遷移する。逆に過電流はJだけ減らしてやれば
良くR4=T/2C2(1+r)とすればトランジス
タ電流が正常時よりrIr+J多くなつたときにコ
ンパレータ17は遷移する。 On the other hand, since the proportion of unbalance does not change even under light load or no load, it is considered abnormal even if the absolute amount of unbalance is small. For example, if r = 0.2 and the standard is 100A at full load, an excess or deficiency of 20A will cause a failure at full load, but a failure will occur at 10A at 50A, 2A at 10A, and 0.2A at 1A. This is fine if the load variable is small and the load will not become no-load or light-load, but if this is not the case, a certain degree of unbalance will occur due to variations in parts, etc., so if the load becomes light, the circuit may shut off even though it is not abnormal. There is. In order to prevent this, it is sufficient to add or subtract a current equal to the absolute value J to the detected value as shown in FIG. The insufficient current can be solved by passing a current J through the resistor R 5 R 5 = T/
2C 2 (1-r), when the transistor current is less than normal by rI r +J, the comparator 16
transitions. Conversely, if the overcurrent is reduced by J, then R 4 =T/2C 2 (1+r), the comparator 17 transitions when the transistor current becomes rI r +J higher than the normal state.
第4図は1石フオワード形コンバータに適用し
た実施例であり動作波形を第5図に示す。第5図
イはトランジスタ1の電流ロはリアクトルL′の電
流ハはトランス4の1次巻線電圧で時刻t1でトラ
ンジスタ1がオンするとトランス4の巻数比を1
とすると初期値Ipが流れ(Ei−Ep)/L′の傾きで
上昇し2次側のリアクトルL′に同電流が流れる。
時刻t2でトランジスタ1がオフするとトランジス
タの電流が遮断されリアクトルL′の電流はダイオ
ード25を介して流れEp/L′の傾きで減少する。
トランス4の励磁電流はダイオード8を介して直
流電源3に帰還され時刻t3で励磁はリセツトされ
る。時刻t4で再びトランジスタ1をオンさせ、こ
の動作を繰返す。このように動作するフオワード
形コンバータもプツシユプル形と同様な回路構成
で選択遮断ができる。コンデンサC2の電位は第
1図の実施例で述べたのと同じであり、コンデン
サC3の電位はトランジスタが1個であるので(2)
式を1/2にすれば良いので
R3=2r/(1−r)2・T/C2……(7)
R4=T/(1+r)C2 ……(8)
となり2石プツシユプル形と比べ抵抗値を2倍に
すれば良い。従つてフオワード形も同様に選択遮
断ができることが分る。 FIG. 4 shows an embodiment applied to a one-stone forward converter, and FIG. 5 shows operating waveforms. In Fig. 5A, the current of transistor 1 (L) is the current of reactor L' (C) is the primary winding voltage of transformer 4.When transistor 1 is turned on at time t1 , the turns ratio of transformer 4 is 1.
Then, the initial value I p rises at a slope of (E i -E p )/L', and the same current flows through the reactor L' on the secondary side.
When transistor 1 is turned off at time t2 , the current in the transistor is cut off, and the current in reactor L' flows through diode 25 and decreases with a slope of E p /L'.
The excitation current of the transformer 4 is fed back to the DC power supply 3 via the diode 8, and the excitation is reset at time t3 . At time t4 , transistor 1 is turned on again and this operation is repeated. A forward type converter that operates in this manner can also be selectively shut off using a circuit configuration similar to that of the push-pull type. The potential of capacitor C 2 is the same as described in the embodiment of Fig. 1, and the potential of capacitor C 3 is (2) since there is only one transistor.
The formula can be reduced to 1/2, so R 3 = 2r/(1-r) 2・T/C 2 ……(7) R 4 =T/(1+r)C 2 ……(8) So 2 stones pushupuru Just double the resistance value compared to the shape. Therefore, it can be seen that the forward type can also be selectively shut off.
第6図はフライバツク形コンバータに適用した
場合の一実施例であり、その動作波形を第7図に
示す。第7図のイはトランジスタ1の電流波形ロ
はトランス4の2次巻線の電流波形ハはトランス
4の1次巻線電圧を示す。トランス4の励磁イン
ダクタンスL″とし、時刻t1でトランジスタ1をオ
ンさせるとトランジスタ1の電流は初期値Ipより
Ei/Lの傾きで上昇し、時刻t2でトランジスタ1
をオフさせるとトランス4の1次電流は2次側に
移りEp/L″の傾きで減少する。時刻t3で再びトラ
ンジスタ1を点弧するとトランス4の2次電流は
1次へ移り時刻t1のときと同様にEi/L″の傾きで
上昇する。以上の動作を繰返す。このように動作
するフライバツク形コンバータはフオワード形と
全く同じで抵抗器R3,R4は(7)、(8)式と同じにな
る。 FIG. 6 shows an embodiment in which the present invention is applied to a flyback converter, and FIG. 7 shows its operating waveforms. In FIG. 7, A shows the current waveform of the transistor 1, B shows the current waveform of the secondary winding of the transformer 4, and C shows the voltage of the primary winding of the transformer 4. When the excitation inductance of transformer 4 is L'' and transistor 1 is turned on at time t 1 , the current of transistor 1 becomes smaller than the initial value I p .
It rises with a slope of E i /L, and at time t 2 transistor 1
When transistor 1 is turned off, the primary current of transformer 4 moves to the secondary side and decreases with a slope of E p /L''.When transistor 1 is turned on again at time t3 , the secondary current of transformer 4 moves to the primary side and decreases at time t3. As in the case of t 1 , it rises at a slope of E i /L''. Repeat the above operations. The flyback type converter that operates in this way is exactly the same as the forward type, and the resistors R 3 and R 4 are the same as in equations (7) and (8).
第8図は電流出力形プツシユプルコンバータに
適用した場合の一実施例であり、出力電流を電流
検出用抵抗器R6で電圧に変換し基準電源9の電
圧と比較し誤差増幅器10で増幅し各ユニツトコ
ンバータに電流基準信号として送り出す。動作は
電圧出力形プツシユプルコンデンサと同様であり
説明は省略する。 FIG. 8 shows an example in which the output current is applied to a current output type push-pull converter. The output current is converted to voltage by a current detection resistor R6 , compared with the voltage of a reference power supply 9, and amplified by an error amplifier 10. and sends it to each unit converter as a current reference signal. The operation is similar to that of a voltage output type push-pull capacitor, so the explanation will be omitted.
以上述べたように本発明は基準値と出力制御値
との差を増幅して得られた値を電流基準信号と
し、該電流基準信号とスイツチング素子の毎導通
時の電流積分値とを一致するよう制御するDC−
DCコンバータユニツトを複数台並列冗長運転す
るDC−DCコンバータ装置において、上記DC−
DCコンバータユニツト毎に上記スイツチング素
子の電流の和の平均値と上記電流基準信号とを比
較し、一定以上の差異が一定期間持続したDC−
DCコンバータユニツトを故障と判断し並列運転
より切り離す選択遮断回路を備えたことを特徴と
するDC−DCコンバータ装置である。本発明はこ
のような特徴を有するので、並列運転しているコ
ンバータの異常を新たな変流器を使用することな
く簡単な回路で、任意な設定値で検出でき、しか
も並列運転台数の変化に対して何ら切替回路など
の付加をしないで各ユニツトコンバータに対し同
一設定で分担電流の異常を検出できる。
As described above, the present invention amplifies the difference between the reference value and the output control value, uses the obtained value as the current reference signal, and matches the current reference signal with the current integral value at each conduction of the switching element. DC to control like
In a DC-DC converter device that operates multiple DC converter units in parallel and redundantly, the DC-
For each DC converter unit, compare the average value of the sum of the currents of the switching elements with the current reference signal, and if the DC-
This DC-DC converter device is characterized by being equipped with a selective cutoff circuit that determines that a DC converter unit has failed and disconnects it from parallel operation. Since the present invention has such features, it is possible to detect abnormalities in converters operating in parallel using a simple circuit without using a new current transformer, and at any setting value, and it is also possible to detect abnormalities in converters operating in parallel with any change in the number of converters operating in parallel. On the other hand, an abnormality in the shared current can be detected by using the same settings for each unit converter without adding any switching circuit or the like.
第1図乃至第8図は本発明の実施例を説明する
ための図である。
1,1′……トランジスタ、2,2′……駆動回
路、3……直流電源、4……トランス、5……整
流回路、6,8,25……ダイオード、7……負
荷、9……基準電源、10……誤差増幅器、11
……信号絶縁伝達回路、12,12′……変流器、
13,13′……変換回路、14,14′,15,
15′……電流源、16,17,24,24′……
コンパレータ、18……オア論理回路、19……
時限回路、20……制御回路、21……トリツプ
コイル、22……入力ブレーカ、23,23′…
…コンバータ、L,L′……リアクトル、R1〜R6
……抵抗器、C1,C2,C2′,C3……コンデンサ。
FIGS. 1 to 8 are diagrams for explaining embodiments of the present invention. 1, 1'... Transistor, 2, 2'... Drive circuit, 3... DC power supply, 4... Transformer, 5... Rectifier circuit, 6, 8, 25... Diode, 7... Load, 9... ... Reference power supply, 10 ... Error amplifier, 11
... Signal insulation transmission circuit, 12, 12' ... Current transformer,
13, 13'... Conversion circuit, 14, 14', 15,
15'... Current source, 16, 17, 24, 24'...
Comparator, 18...OR logic circuit, 19...
Time limit circuit, 20... Control circuit, 21... Trip coil, 22... Input breaker, 23, 23'...
...Converter, L, L'...Reactor, R 1 to R 6
...Resistor, C 1 , C 2 , C 2 ', C 3 ... Capacitor.
Claims (1)
た値を電流基準信号とし、該電流基準信号とスイ
ツチング素子の毎導通時の電流積分値とを一致す
るよう制御するDC−DCコンバータユニツトを複
数台並列冗長運転するDC−DCコンバータ装置に
おいて、上記DC−DCコンバータユニツト毎に上
記スイツチング素子の電流の和の平均値と上記電
流基準信号とを比較し、一定以上の差異が一定期
間持続したDC−DCコンバータユニツトを故障と
判断し並列運転より切り離す選択遮断回路を備え
たことを特徴とするDC−DCコンバータ装置。1. A DC-DC converter that uses a value obtained by amplifying the difference between a reference value and an output control value as a current reference signal, and controls the current reference signal and the current integral value at each conduction of a switching element to match. In a DC-DC converter device in which multiple units are operated redundantly in parallel, the average value of the sum of the currents of the switching elements for each DC-DC converter unit is compared with the current reference signal, and if a difference of more than a certain value is detected for a certain period of time. A DC-DC converter device characterized by being equipped with a selective cutoff circuit that determines that a sustained DC-DC converter unit has failed and disconnects it from parallel operation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60125894A JPS61285071A (en) | 1985-06-10 | 1985-06-10 | Dc/dc converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60125894A JPS61285071A (en) | 1985-06-10 | 1985-06-10 | Dc/dc converter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61285071A JPS61285071A (en) | 1986-12-15 |
| JPH0250713B2 true JPH0250713B2 (en) | 1990-11-05 |
Family
ID=14921539
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60125894A Granted JPS61285071A (en) | 1985-06-10 | 1985-06-10 | Dc/dc converter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61285071A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0681502B2 (en) * | 1988-07-14 | 1994-10-12 | 富士通電装株式会社 | Parallel operation protection circuit |
-
1985
- 1985-06-10 JP JP60125894A patent/JPS61285071A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61285071A (en) | 1986-12-15 |
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