JPH0250738A - Test system for check processing circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] 〔overview〕 At least a main unit equipped with a RAS mechanism.

and an external device, and based on control from the external device, controls the RAS mechanism and maintains the main device.

Regarding the test method for the check processing circuit of the RAS mechanism in the computer system being operated, the time required for checking the RAS mechanism is shortened, the check is completed within the maintenance time, and the normality of the RAS mechanism of the computer system is verified. means for simultaneously injecting a plurality of pieces of error data into a plurality of check processing circuits in the RAS mechanism for the purpose of increasing the number of errors;

The above RA operated based on the injected error data.
and means for simultaneously notifying the outside of the state of the plurality of check processing circuits in the S mechanism, and based on the error data injection means and the external notification means, the RAS mechanism provided in the main body device is configured to test a plurality of check processing circuits.

[Industrial application field]

The present invention is directed to a computer system that includes at least a main unit equipped with a RAS mechanism and an external device, and that controls the RAS mechanism based on control from the external device and maintains and operates the main unit. The present invention relates to a test method for a check processing circuit of a RAS mechanism.

With the recent trend toward online data processing, it has become increasingly important to ensure the normality of the so-called RAS mechanism provided in computer systems.

Therefore, in a computer system that is online, the test processing circuit for the check processing circuit that constitutes the RAS mechanism can be tested from the service processor (SVP) at the user's site during regular maintenance hours. You are required to be able to complete it completely.

However, with the recent diversification of data processing, the data processing mechanism of the main unit of a computer system has also become more complex, and the RAS mechanism has also become more diverse and complex, and its amount has also increased. The trend is for time to increase dramatically.

Under these circumstances, there is a need for a test method for the RAS mechanism that can effectively check all RAS mechanisms during the normal maintenance and operation period from the service processor (SVP) at the user. It's here.

[Prior art and problems to be solved by the invention] FIG. 3 is a diagram illustrating a test method for a conventional RAS mechanism.

Conventionally, the RAS mechanism provided in the main unit 2 of a computer system (-In boat fishing, it refers to an error reporting circuit 210b including a check processing circuit 210 and a retry circuit, but the retry circuit is not included here. ) 21, an external device of the computer system, such as the service processor (SVP) 1 shown in the figure, scans the scan-in (SCAN ) by means of the RAS
Error data is injected into the check processing circuit 210 that constitutes the mechanism 21.

Specifically, the flip-flop (FF) 210a corresponding to the error processing circuit 210 is set to a scan address (S
CAN ADRS) to inject error data.

In this state, after incrementing the clock of the main unit by a necessary number of steps using, for example, a clock increment mechanism, the check processing circuit 210 checks the flip-flop, FF, which has reported the error.
210b, this time scan out (SCAN 0UT
), a flip-flop (FF) 21 corresponding to all the check processing circuits 210 of the RAS mechanism 21 is used.
By repeating this for 0a and 0b, their normality was confirmed.

Generally, in order to test the check processing circuit of one point, it is necessary to give one error data, but since the error data may affect other test points, test the next test point. When performing a test, initialization processing of the logic group to be tested (this processing is called preprocessing), and processing to restore the logic circuit destroyed by injection of the error data to its original state (this processing is called preprocessing) are performed. (referred to as post-processing) is required.

Usually, the above-mentioned test for the RAS mechanism 21 is performed by
The above-mentioned method is used to perform the testing by starting a test program configured for each specific logic circuit group of the main device 2.

As mentioned above, as the internal mechanisms of modern computer systems become more complex, the proportion of the RAS mechanism 21 increases, and the execution time required for the above one point test also increases as the pre-processing and post-processing become complicated. In large computer systems, the problem has arisen that testing of the RAS mechanism cannot be completed within the regular maintenance time at the user's site.

The present invention has been made in view of the above-mentioned drawbacks of the conventional art.

Consists of a main device equipped with a RAS mechanism and an external device,
When testing the check processing circuit of the RAS mechanism in a computer system that controls the RAS mechanism and maintains and operates the main device based on control from the external device,
The purpose of the present invention is to provide a RAS mechanism testing method that reduces the time required to check the RAS mechanism, completes the test within the maintenance time at the user's site, and increases the normality of the RAS mechanism of a computer system. It is something to do.

[Means to solve the problem]

The above problems are solved by a test method for the RAS mechanism configured as follows.

At least a main unit equipped with a RAS mechanism.

and an external device, and based on control from the external device, controls the RAS mechanism and maintains the main device.

In an operating computer system, means for simultaneously injecting a plurality of pieces of error data into a plurality of check processing circuits in the RAS mechanism.

The above RA operated based on the injected error data.
and means for simultaneously notifying the outside of the state of the plurality of check processing circuits in the S mechanism, and based on the error data injection means and the external notification means, the RAS mechanism provided in the main body device is configured to test a plurality of check processing circuits.

[Effect]

That is, according to the present invention, the main unit includes at least a main unit including a RAS mechanism and an external device, for example, a service processor (SVP), and controls the RAS mechanism based on control from the external device, In computer systems that maintain and operate main devices, the RAS mechanism generally
Focusing on the fact that a specific logic circuit group is configured as a unit, the RAS for the specific logic circuit group is
Multiple flip-flops (FF) that make up the mechanism
For example, error data is simultaneously injected from the service processor (SVP), the number of clocks necessary to operate the logic circuit group is stepped, and a plurality of reporting flip-flops are reported based on the results. (F
The state of F) is taken out to the service processor (SVP).

To inject the above error data and retrieve the error report,
For example, a scan-in/out mechanism provided in a normal computer system is used, but in the present invention, a plurality of scan-in addresses, error data,
For example, the scan-out addresses are prepared as a table, and when testing the RAS mechanism of the logic circuit group, the table is used to correspond to each scan-in address for the plurality of scan-in points. After injecting the error data, as many clocks as necessary to operate the logic circuit group.

This can be achieved by incrementing the clock by the aforementioned clock incrementing mechanism and then sequentially extracting the reported error information according to the scan-out address of the table.

In this way, by testing multiple check processing circuits for each logic circuit group that has little logical connection to each other, preprocessing that was conventionally required every time a check processing circuit of one point was tested. Since the post-processing only needs to be performed once for the logic circuit group, and the pre-processing and post-processing are also short, the test time for the RAS mechanism can be significantly reduced. can get.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a diagram schematically showing an embodiment of the present invention,
FIG. 2 is a diagram schematically showing another embodiment of the present invention, in which error data is simultaneously injected into a plurality of check processing circuits 210 constituting the RAS mechanism 21, and the operation results are The means 12, 13 for ejection are the means necessary to carry out the invention.

Note that the same reference numerals refer to the same objects throughout the plan.

Hereinafter, the change processing circuit test method of the present invention will be explained with reference to FIGS. 1 and 2.

Even if the present invention is implemented, for example, the service processor (S
The basic operation of the scan-in/out mechanism 21 in the main unit 2 from VP) 1 is not particularly different from the conventional method, so it will be omitted here. The explanation will focus on the operation of testing multiple test points by simultaneously scanning in and out points.

As described above, a main unit of a computer system, for example, is composed of a plurality of logic circuit groups with relatively few logical connections.

The present invention focuses on the fact that the logic circuits of a computer system are configured in this way, and uses each logic circuit group that has little logical connection to each other as a unit, and configures a plurality of RAS mechanisms 21 of the logic circuit group. Check processing circuit 21
Flip-flop (FF) to be checked corresponding to 0
210a, and a report flip-flop (FF) 210b that stores the report results from each check processing circuit 210.
Scan-in address (SCAN) assigned to
INADRS), scanout address (SCAN
OUT ADRS) and the above scan-in address (
The error data to be injected into the flip-flop (FF) 210a specified by SCAN INADRS) is registered as a pair, for example, in Table 12.13.

The table 12.13 is stored in the service processor (SVP).
) 1 and a service processor (SVP) 1
An example in which the table 12 or 13 is registered by itself is shown in FIG. 1, and an example in which the tables 12 and 13 are provided in the main unit 2 and registered from the service processor (SVP) 1 is shown in FIG. Basically, it is the same in both cases.

If the scan-in addresses and scan-out addresses registered in Tables 12 and 13 above have order, for example, they may be configured as counters instead of in table format. It goes without saying that this is true.

Based on the scan-in address generating means 12a configured in this way, the error data 12b is transferred to a flip-flop (FF) designated by the scan-in address.
210a temporarily.

Thereafter, the number of clocks necessary for the logic circuit group to operate is stepped by a known clock stepping mechanism, for example.

As a result, a reporting flip-flop (FF) that stores the test results reported from each check processing circuit 210
The scan-out address generating means 13 that specifies 210b simultaneously reads the data to the service processor (SVP) and confirms its normality.

As described above, prior to the confirmation process of the check processing circuit 210, the logic circuit group and related logic circuit groups are initialized, that is, preprocessed, and the error data is incremented by several clocks. There is post-processing that restores the state of the logic circuit group and related logic circuit groups that have been adversely affected by setting the error data, but for setting the plurality of error data, Because the logic circuit group to be tested is conducted only once, and because the test is performed in group units where the logic circuit group to be tested is logically relatively closed to other logic circuit groups, there is no impact on other logic circuit groups. Also, there will be less
For example, when a test operation is performed with N error flags set simultaneously, the time required is substantially 17N compared to the conventional method.

As described above, the present invention comprises at least a main device equipped with a RAS mechanism and an external device, and controls the RAS mechanism based on control from the external device to maintain and operate the main device. To test the check processing circuit of the RAS mechanism in a computer system, the logic circuits constituting the main unit are divided into a plurality of groups with little logical connection to each other, and each logic circuit group is used as a unit. , For example, using a scan-in/out mechanism, a scan-in address that specifies a flip-flop (FF) to be checked is assigned to a plurality of check processing circuits that constitute the RAS mechanism in the logic circuit group. occurs, scans in error data for each one at a time, increments by the number of clocks necessary to operate the logic circuit group, and then stores the check results reported from each check processing circuit. The feature is that a scan-out address indicating a report flip-flop (FF) is generated and read at the same time to confirm the normality of the check processing circuit.

〔Effect of the invention〕

As described above in detail, the test method for the check processing circuit of the present invention includes at least a main unit equipped with a RAS mechanism and an external device, and based on the control from the external device, the test system for the check processing circuit of the present invention control, maintain the main unit,
In an operating computer system, a means for simultaneously injecting a plurality of pieces of error data into a plurality of check processing circuits in the RAS mechanism, and a means for injecting a plurality of pieces of error data into a plurality of check processing circuits in the RAS mechanism that operate based on the injected error data; means for notifying the outside of the state of a plurality of check processing circuits at once; Since this test is designed to test check processing circuits, for example, by testing a plurality of check processing circuits in each logic circuit group that has little logical connection with each other, conventionally, one point check processing circuit can be tested. The pre-processing and post-processing that were required each time a test is performed only need to be performed once for the logic circuit group, and
Since the pre-processing and post-processing also take a short time, the test time of the RAS mechanism can be significantly shortened.

[Brief explanation of the drawing]

FIG. 1 is a diagram schematically showing an embodiment of the present invention. FIG. 2 is a diagram schematically showing another embodiment of the present invention. FIG. 3 is a diagram explaining a test method for a conventional RAS mechanism. It is. In the drawing, 1 is a service processor (SVP) and 12 is a table. 12a is a scan-in address or scan-in address generating means. 12b is error data. 13 is a scan-out address or a scan-out address generating means. 2 is the main unit, and 21 is the RAS mechanism. 210 is a check processing circuit. 210a is a flip-flop (
FF), (RAS mechanism flip-flop (FF)
) 210b is a reporting flip-flop (FF). are shown respectively.

Claims (1)

[Claims] At least a main body device (2) equipped with a RAS mechanism (21)
) and an external device (1), and controls the RAS mechanism (21) based on control from the external device (1),
In a computer system that maintains and operates the main unit (2), a plurality of check processing circuits (
210), means (12) for injecting a plurality of pieces of error data at once; and the RA that operates based on the injected error data.
The plurality of check processing circuits (21) in the S mechanism (21)
0) to the outside at once, the error data injection means (12) and the external notification means (1
3), the R provided in the main unit (2)
A plurality of check processing circuits (210) of the AS mechanism (21)
) is a check processing circuit test method characterized by testing.