JPH0251027B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an unlocking device that outputs an unlocking signal when a combination of operation signals from a plurality of operation switches matches a preset code.

In this type of unlocking device, when the operation signal is output from the operation switch, the power supply of the control circuit,
A structure is being used in which a lamp or the like for illuminating a part of the operation switch is driven. However, with such a configuration, the operation switch often malfunctions and the operation signal remains output, and if this condition continues for a long time, the power consumption becomes large. In particular, when power is obtained from a battery, such as in an automobile, there is a problem of so-called battery build-up.

The present invention has been made in view of the above circumstances, and its purpose is to eliminate the risk of wasting power consumption even if the operating switch breaks down, and to prevent battery build-up even when the power source is obtained from a battery. To provide an unlocking device which can be unlocked by using the remaining operation switches which are not broken and which are not broken.

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.
This will be explained according to the diagram.

In FIG. 1, reference numeral 1 denotes a keyboard serving as a signal input means attached to the door of an automobile (not shown), and this keyboard has a plurality of, for example, three operation switches 2.
a, 2b, 2c, and operation switches 2a, 2
One end of each of the wires b, 2c is connected to a ground terminal, and the other end is connected to a detection line 3a, 3b, 3c, respectively. Moreover, these detection lines 3a, 3b, 3c are
The negative terminal is connected to the grounded positive terminal +V _B of the battery through resistors 4 and 4, respectively, and
They are connected to a ground terminal via capacitors 5, . . . for eliminating chattering, respectively. Therefore, detection line 3
The signals a, 3b, and 3c are always at high level, but become low level when operation switches 2a, 2b, and 2c are turned on, and these low level signals are used as operation signals Sa, Sb, and Sc. shall be. 6
1 is a prohibition circuit which is a prohibition means, and this includes Schmitt trigger circuits 8a, 8b, 8 for waveform shaping, respectively, between the detection lines 3a, 3b, 3c and the ground terminal.
c and capacitors 9a, 9b, 9c and resistor 1
0a, 10b, 10c are connected in series to form three differentiating circuits corresponding to each operation signal Sa, Sb, Sc, and capacitors 9a, 9b, 9c are connected.
and common connection points A ₁ , A ₂ , A ₃ between each of the resistors 10a, 10b, and 10c (i.e., the output terminals of the above-mentioned differentiating circuits)
Diodes 11a, 11b, 11c for negative differential pulse removal are connected between the terminal and the ground terminal, and the common connection points A ₁ , A ₂ , A ₃ and the output lines 12a, 12
Schmitt trigger circuits 13a, 13b, and 13c for waveform shaping are connected between the waveforms b and 12c, respectively. Therefore, positive pulse-shaped secondary signals S'a, S'b, and S'c corresponding to the operation signals Sa, Sb, and Sc are outputted to the output lines 12a, 12b, and 12c, respectively. Now,
Reference numeral 14 denotes a control circuit including a microcomputer, which will be described below. 15
are secondary signals from output lines 12a, 12b, 12c
A first cryptographic matching circuit receiving S′a, S′b, S′c, 1
6 is a storage circuit that stores preset combination signals, and the first code matching circuit 15 stores secondary signals S'a, S' when the operating switches 2a, 2b, 2c are turned on. b, S′c are received and the combination is compared with the combination code in the memory circuit 16, and when they match, in other words, the operation switches 2a, 2
When b and 2c are turned on in accordance with the order of the above combination codes, an unlocking signal So is output. 17 is a secondary signal from output lines 12a, 12b, 12c
The second circuit receives S′a, S′b, and S′c by rotating the OR circuit 18.
This is a code verification circuit with the configuration described below. That is, 19 is a D flip-flop which receives the output from the OR circuit 18 at its data input terminal D, and the oscillator 2 at its clock terminal ck.
An oscillation pulse Po (see FIG. 2a) from 0 is input. The oscillator 20 has an oscillation period of, for example, 1
Hz, and its output is the oscillation pulse
Po is also given to the clock terminal ck of the decimal Johnson counter 21. This counter 21 has a configuration in which the output of one of the ten output terminals Q ₀ to Q ₉ becomes high level in sequence according to the number of pulses applied to the clock terminal ck, and a pulse is applied to the reset terminal R. When applied, the output terminal _Q0 is reset to a state in which a high level signal is output. Of the ten output terminals Q ₀ to Q ₉ of the counter 21, for example, four output terminals Q ₁ , Q ₅ , Q ₇ , Q ₈ are connected to each input terminal of the OR circuit 23 via the switch section 22. According to the counting operation of the counter 21, the OR circuit 23 outputs a high level for 1 second, a low level period of 3 seconds, a high level again for 1 second, and a low level for another 1 second, and then 2 seconds. Time series cipher T with high level per second
(See Figure 2b) is output. Further, the high level signal output from the highest output terminal _Q9 of the counter 21 becomes the unlocking signal _S1 . On the other hand, 24 is D
This is an exclusive CR circuit which receives as input the output from the output terminal Q of the flip-flop 19 and the time series code T from the OR circuit 23, and its output terminal is connected to the reset terminal R of the counter 21 via the integrating circuit 25. There is. Further, 26 is a drive circuit which receives the unlock signal S ₀ from the first code verification circuit 15 and the unlock signal S ₁ from the second code verification circuit 17 via the OR circuit 27; Signal S ₀ , S ₁
When either of these is received, the electromagnetic solenoid is energized to unlock the door lock mechanism (both not shown).

Next, the operation of the above configuration will be explained. Now, when the operating switches 2a, 2b, and 2c are turned on in the order that matches the combination code stored in the memory circuit 16, the first code verification circuit 15 outputs the unlock signal _S0 as described above. The drive circuit 26 receives this unlock signal _S0 via the OR circuit 27 and unlocks the door lock mechanism. Therefore, on the keyboard 1, for example, the operation switch 2
If a failure occurs in which a is short-circuited and does not recover, the operation signal Sa continues to be output, but at this time a certain period of time corresponding to the time constant of the differentiating circuit consisting of the capacitor 9a and the resistor 10a has elapsed. Then, the secondary signal S'a disappears and the output from the operating switch 2a becomes invalid. Therefore, even if the configuration is such that the load is driven, such as by turning on the lamp for illuminating the keyboard 1 for a predetermined period of time in response to the output of the secondary signals S'a, S'b, and S'c, the operation switches 2a, The lamp will not be turned on for an unintentionally long time due to a failure of 2b and 2c, and so-called battery build-up can be prevented. Also, in this way, the operation switch 2
If even one of a, 2b, and 2c fails, it becomes impossible to unlock the door lock mechanism using the combination code, but in such a case, the door lock mechanism can be unlocked using the time series code T. That is,
Now, if the operation switch 2a is out of order, if one of the other normal operation switches 2b and 2c, for example operation switch 2c, is turned on at a time interval that matches the time series code T, the second code verification is performed. The circuit 17 performs the following operations. At time _t1 in Figure 2, the operation switch 2c is turned on and a secondary signal S'c (see Figure 2 e) is output, which is D
When applied to the data input terminal D of the flip-flop 19, the D flip-flop 19 outputs a high level signal (see FIG. 2c) in synchronization with the input of the oscillation pulse _P0 to its clock input terminal ck. At this time, the oscillation pulse _P0 is applied to the clock terminal ck of the counter 21, and the counter 21 outputs a high level signal (see FIG. _2b ) from its output terminal Q1. For this reason, the exclusive OR circuit 24 receives signals of the same level to both its input terminals and outputs a low level signal, so that no pulse is applied to the reset terminal R of the counter 21 and the counter 21 Continue counting oscillation pulses P ₀ . During the period in which the counter 21 outputs a high-level signal from its output terminals Q ₂ to Q ₄ , the high-level signal is not input to the exclusive OR circuit 24 by the switch section 22 , and furthermore, during this period, the high-level signal is not inputted to the exclusive OR circuit 24 . Since the operation switch 2c is not turned on based on the series code T, the D flip-flop 19 does not output a high level signal, and therefore, the exclusive OR circuit 24 receives the same level signal (low level) at both input terminals. The counter 21 then outputs a low level signal, and the counter 21 continues counting without being reset. At time _t2 when a high level signal is output from the output terminal _Q5 of the counter 21, when the operation switch 2c is turned on based on the time series code T, a high level signal is output from the D flip-flop 19 as described above. Since the same level signal is input to both input terminals of the exclusive OR circuit 24, the exclusive OR circuit 24 is maintained in a state where it outputs a low level signal, and the counting operation of the counter 21 is executed. . The exclusive OR circuit 24 operates at subsequent times t ₃ ,
Even when the operation switch 2c is turned on based on the time series code T at _t4 , the low level signal output state is maintained, and when the counter 21 reaches time _t5 without being reset in this way, its maximum value is output. An unlocking signal _S1 is output from the upper output terminal _Q9 , and the drive circuit 26 receiving this unlocking signal _S1 unlocks the door lock mechanism. In this embodiment, since the output from the exclusive OR circuit 24 is applied to the reset terminal R of the counter 21 via the integrating circuit 25, the timing at which the high level signal is output from the D flip-flop 19 is Even if a high level signal is output from the exclusive OR circuit 24 for a short period of time at a time deviated from the timing at which the high level signal is output from the OR circuit 23, the output of the integrating circuit 25 is Unless the high level signal continues for a predetermined period of time, it will not become high level, so that the counter 21 will not be reset inadvertently. That is, the operation switch 2a,
It is practically difficult to turn on 2b and 2c at the timing according to the time series code T, and
A high level signal with a small pulse width may be unnecessarily output from the OR circuit 24, but the integration circuit 25
acts as a so-called whisker removal circuit that removes these unnecessary signals. If the operation switch 2c is turned on at an interval that does not match the time series code T, at that point, signals of different levels are input to both input terminals of the exclusive OR circuit 24, and the exclusive OR circuit 24
A high level signal is now output from the OR circuit 24, and the counter 21 receives the high level signal at its reset terminal R via the integrating circuit 25 and is reset. Therefore, the output terminal Q ₉ of the counter 21
Since the unlock signal _S1 is not outputted from the door, there is no possibility that the door lock mechanism will be unlocked by someone who does not know the time series code T. In the above embodiment, the first code verification circuit 15 and the second code verification circuit 17 are configured to be selectively enabled by a switch, or the operation switches 2a, 2
A configuration may also be provided in which a changeover switch mechanism is provided that detects a failure of the codes b and 2c and automatically activates the second code checking circuit 17.

According to the present invention, as is clear from the above description, a signal input means that has a plurality of operation switches and generates operation signals by operating the switch, and a combination of operation signals from the signal input means are set in advance. The unlocking device is equipped with a control circuit that outputs an unlocking signal when the combination code matches the one entered, and there is no risk of wasting power even if the operation switch fails, and the power is obtained from a battery. It has the excellent effect of not causing battery failure even when the operation switch is broken and it becomes impossible to unlock the lock using the combinational code. It is also possible to have the effect of enabling locking.

[Brief explanation of drawings]

FIG. 1 is an electrical configuration diagram showing an embodiment of the present invention, and FIG. 2 is a time chart for explaining the operation of the embodiment. In the figure, 1 is a keyboard (signal input means), 2a
Reference numerals 2c to 2c are operation switches, 14 is a control circuit, and 6 is an inhibition circuit (inhibition means).

Claims (1)

[Claims] 1. A signal input means that has a plurality of operation switches and generates operation signals when operated, and outputs an unlock signal when the combination of operation signals from the signal input means matches a preset combination code. A control circuit is provided with a prohibition means for disabling the output from the operation switch when the operation signal output state of the operation switch continues for a certain period of time or more, and the control circuit is An unlocking device characterized in that the unlocking device is configured to output an unlocking signal even when at least one of the switches is operated at a time interval that matches a preset time series code.