JPH0251069A - Logic analyzer - Google Patents

Abstract

PURPOSE:To increase an amount of information with the same memory capacity by providing a control code substitution circuit to compress a data with a part of a logic data replaced by a control code. CONSTITUTION:A logic data inputted into an input terminal 101 is inputted into a differentiation circuit 103 and a control code substitution circuit 105. The circuit 103 generates a differentiation signal of an input signal to be stored into a memory circuit 107 to judge whether a data has a changing point or not. Then, the results of the judgement is fed to the circuit 105 as differentiation signal and when it has the changing point, the signal is sent to a circuit 107 as intact. When no changing point exists, the circuit 103 waits for a signal with a changing point to come, measures a waiting time and sends a control code for meaning a signal value at the moment to the circuit 107. When the control code is substituted in the circuit 107, it is decoded with a control decoding circuit 109 and when there is no control code, an instruction is provided to an output device 111 without delay. Thus, decoding data in compression enables an increase in information volume with the same memory capacity.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of observing waveforms using a digital storage method, and particularly to an improvement of a logic analyzer.

(Prior Art) An example of a four-thick analyzer according to the prior art is shown in FIG. In FIG. 3, 301 is an input terminal, 303 is a memory circuit, and 305 is an output device.

In FIG. 3, a storage circuit 303 is used to store and hold signals to be stored as logic data. A signal to be stored is input as data to a storage circuit 303 through a signal line 302. The stored data is
Output device 305 via signal line 304 according to output request
sent to. An example of the displayed waveform of the output device 305 is shown in FIG.

(Problem to be Solved by the Invention) The conventional logic analyzer described above detects a change point in the logic data on the input signal line, regardless of whether there is a change point in the logic data on the input signal line that inputs the logic data. Since the logic data on the input signal line is input to the storage circuit 303 and stored regardless of whether it exists or not, there is a drawback that the amount of information decreases significantly if there is no change for a long time.

An object of the present invention is to use a differentiating circuit to determine whether or not there is a change point in the logic data before inputting it to a storage circuit, and to substitute a control code when the logic data changes using the differential signal output from the differentiating circuit. A logic analyzer configured to eliminate the above drawback and prevent a decrease in the amount of information by storing the output as data and decoding the control code in the data output by the storage circuit in response to an output request. Our goal is to provide the following.

(Means for Solving Problem 1) A logic analyzer according to the present invention includes a storage circuit, a differentiation circuit, a control code substitution circuit, and a control code decoding circuit.

The memory circuit is for inputting and storing logic data.

The differentiation circuit is for generating a differentiation signal of an input signal to be stored in the storage circuit.

The control code substitution circuit is for adding a control code to an input signal using a differential signal.

The control code decoding circuit decodes and outputs the control code added to the logic data read from the storage circuit in accordance with an output request.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the logic analyzer according to the present invention. The logic analyzer according to the present invention includes a differentiation circuit 103, a control code assignment circuit 105,
It is composed of a memory circuit 107, a control code decoding circuit 109, and an output device 111. Logic data input to the input terminal 101 is input to the differentiation circuit 103 and the control code substitution circuit 105 through the signal line 102. The differentiation circuit 103 determines whether or not there is a change point in the data, and sends the determination result as a differential signal to the control code assignment circuit 105 via the signal line 104.

FIG. 2 shows the output device 11 of the logic analyzer shown in FIG.
FIG. 1 is an explanatory diagram showing an example of an output waveform displayed on FIG.

The control code substitution circuit 105 inputs the signal on the signal line 102 to the storage circuit 107 if the signal on the signal line 104 has a changing point, but it inputs the signal on the signal line 102 to the storage circuit 107 when there is no changing point. If so, do not input it as is to the memory circuit 107, but measure the time until the signal arrives when there is a change point (see @t# in Figure 2), and then
The value of the signal on the number string 102 and the code representing time t are sent to the storage circuit 107.

When logic data is output from the storage circuit 107 in response to an output request, if the control code is not included, the control code decoding circuit 109 sends the data as is to the output device 111; The control code is decoded and a command is given to the output device 111.

(See the pulse waveform in Fig. 2.) (Effects of the Invention) As explained above, the present invention can compress data by replacing part of the logic data with control codes, and can maintain the same storage capacity. However, it has the effect of increasing the amount of information.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of a logic analyzer according to the present invention. FIG. 2 is an explanatory diagram showing display waveforms of the output device of FIG. 1. FIG. 3 is a block diagram showing an example of a logic analyzer according to the prior art. FIG. 4 is an explanatory diagram showing an example of a display waveform of the output device of FIG. 3. 101.301--Input terminal 103--Differentiating circuit 105--Control code assignment circuit 107.303--Storage circuit 109--Control code decoding circuit 111.305--Output device 102.104, 106,108. ! 10,302゜3
04...Signal line patent applicant NEC Corporation

Claims (1)

[Claims] a memory circuit for inputting and storing logic data;
a differentiation circuit for generating a differential signal of an input signal to be stored in the storage circuit; a control code substitution circuit for adding a control code to the input signal according to the differential signal; and a control code substitution circuit for adding a control code to the input signal according to the output request. 1. A logic analyzer comprising: a control code decoding circuit for decoding and outputting the control code added to the logic data read from the logic data.