JPH0251318B2 - - Google Patents

Info

Publication number
JPH0251318B2
JPH0251318B2 JP56197501A JP19750181A JPH0251318B2 JP H0251318 B2 JPH0251318 B2 JP H0251318B2 JP 56197501 A JP56197501 A JP 56197501A JP 19750181 A JP19750181 A JP 19750181A JP H0251318 B2 JPH0251318 B2 JP H0251318B2
Authority
JP
Japan
Prior art keywords
circuit
transistor
intermediate frequency
video
base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP56197501A
Other languages
Japanese (ja)
Other versions
JPS5897979A (en
Inventor
Akio Yokoyama
Hiroki Kinugawa
Mitsuo Nanbae
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP56197501A priority Critical patent/JPS5897979A/en
Publication of JPS5897979A publication Critical patent/JPS5897979A/en
Publication of JPH0251318B2 publication Critical patent/JPH0251318B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/14Picture signal circuitry for video frequency region
    • H04N5/16Circuitry for reinsertion of DC and slowly varying components of signal; Circuitry for preservation of black or white level

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Television Receiver Circuits (AREA)

Description

【発明の詳細な説明】 産業上の利用分野 本発明は映像信号の白レベル調整回路に関する
ものである。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a white level adjustment circuit for video signals.

第1図は従来の白レベル調整回路である。以下
図に従つて説明する。中間周波増幅回路1を経
て、検波回路2で検波された映像信号は映像増幅
回路に加えられるが、検波された映像信号、映像
増幅回路の増幅率には必ずバラツキをもつている
ため、白レベルは各々異なつてくる。したがつて
これらを調整するため白レベル調整が必要となる
が、従来、かかる白レベル調整の方式として、第
1図のように、映像増幅回路3の電源端子4に可
変抵抗5を介して固定電圧源6を加え、これによ
り同映像増幅回路3の直流レベルを調整しようと
するものが広く使用されていた。これはAM変調
された中間周波信号が負極性であるときは、白レ
ベルは映像増幅回路の直流レベルとほとんど同じ
となるためである。しかし一方映像増幅回路3の
信号出力は映像出力端子7を経て駆動回路へ行く
と同時に中間周波増幅利得調整(IFAGC)回路
8にも加えられる。この時同回路の動作機能とし
て、ピークAGC方式の場合、映像信号出力のピ
ーク値と上記IFAGC回路8の基準電圧源9の所
定電圧Vrefとを比較し、その差を検出して、フ
イルタ回路10を通して上記中間周波増幅回路1
に帰還制御がかけられる。しかして、この方式で
は、白レベル調整時に基準電圧Vrefが変化しな
いようにするため、通常、上記IFAGC増幅回路
用電源9は映像増幅回路3の電圧Vccの固定電圧
電源6と別電源にしておく必要があり、固定電圧
源11が必要となる。とりわけ、映像増幅回路と
IFAGC回路を同一チツプ内にIC化する場合にお
いては、別々の固定電圧源が必要となると、電源
回路が複雑さに加えて、それ用の端子も各別に必
要となり、きわめて不都合である。
FIG. 1 shows a conventional white level adjustment circuit. This will be explained below with reference to the figures. The video signal detected by the detection circuit 2 after passing through the intermediate frequency amplification circuit 1 is applied to the video amplification circuit, but since there is always variation in the amplification factor of the detected video signal and the video amplification circuit, the white level will be different for each. Therefore, white level adjustment is required to adjust these. Conventionally, as shown in FIG. A system in which a voltage source 6 is added to adjust the DC level of the video amplification circuit 3 has been widely used. This is because when the AM modulated intermediate frequency signal has negative polarity, the white level is almost the same as the DC level of the video amplification circuit. However, on the other hand, the signal output of the video amplification circuit 3 is sent to the drive circuit via the video output terminal 7 and is also applied to the intermediate frequency amplification gain adjustment (IFAGC) circuit 8 at the same time. At this time, the operating function of the circuit is to compare the peak value of the video signal output and the predetermined voltage Vref of the reference voltage source 9 of the IFAGC circuit 8, and detect the difference, in the case of the peak AGC method. through the above intermediate frequency amplification circuit 1
Feedback control is applied to However, in this method, in order to prevent the reference voltage Vref from changing when adjusting the white level, the power supply 9 for the IFAGC amplifier circuit is normally provided separately from the fixed voltage power supply 6 of the voltage Vcc of the video amplifier circuit 3. Therefore, a fixed voltage source 11 is required. In particular, video amplification circuits and
When integrating the IFAGC circuit into an IC on the same chip, if separate fixed voltage sources are required, the power supply circuit will be complicated and separate terminals will be required for each, which is extremely inconvenient.

本発明はかかる困難を克服するものであり以下
に、第2図に示す実施例により、本発明を詳述す
る。第2図において中間周波で変調され増幅され
た映像中間周波信号はトランジスタT1、抵抗R1
よりなるエミツタフオロワを通じてトランジスタ
T2,T3のベースに加えられる。
The present invention overcomes these difficulties and will be described in detail below with reference to an embodiment shown in FIG. In Fig. 2, the video intermediate frequency signal modulated and amplified at the intermediate frequency is transmitted through the transistor T 1 and the resistor R 1 .
Transistor through emitter follower
Added to the base of T 2 and T 3 .

この時、映像中間周波信号は、通常、数十MHz
であるので、上記トランジスタT3のベースへの
入力信号は抵抗R2と寄生容量C2で構成されるフ
イルタによつて平滑された直流信号となる。一
方、トランジスタT2のベースへは抵抗R3とコン
デンサC1よりなる高域フイルタによつて上記映
像中間周波信号がそのまま加えられる。トランジ
スタT2、定電流源12、コンデンサC3からなる
検波回路により検波されて、復調され、これがト
ランジスタT4のベースに加えられ、さらに、こ
の検波された信号は、トランジスタT4と抵抗R6
よりなるエミツタフオロワを通してトランジスタ
T6のベースに加えられる。一方、上記トランジ
スタT3側の平滑された直流分信号はトランジス
タT5と抵抗R7よりなるエミツタフオロワを通し
てトランジスタT7のベースに加えられる。この
時R8=R9=R、可変電流源14の電流をIoとす
ると、R>KT/qIoのとき、このトランジスタT6お よび同T7による差動増幅回路の利得はR10/2Rとな ることはよく知られ、Ioによつてこの差動増幅回
路の利得は影響をあまりうけない。また、上記可
変電流源14の電流Ioは、Vcc−1/2・IoR10
の関係をもつて、トランジスタT7のコレクタ直
流電位を与え、これは、そのまま、トランジスタ
T8のベースに加えられて映像信号の白レベルを
決定するものである。そして映像信号は、上述の
差動増幅回路ならびに、トランジスタT8と抵抗11
よりなる出力回路を通して、出力端子7に導かれ
る。
At this time, the video intermediate frequency signal is usually several tens of MHz.
Therefore, the input signal to the base of the transistor T3 becomes a DC signal smoothed by a filter composed of a resistor R2 and a parasitic capacitor C2 . On the other hand, the video intermediate frequency signal is directly applied to the base of the transistor T2 by a high-pass filter consisting of a resistor R3 and a capacitor C1 . The signal is detected and demodulated by a detection circuit consisting of a transistor T 2 , a constant current source 12 , and a capacitor C 3 , and is applied to the base of a transistor T 4 .
Transistor through emitter follower
Added to T 6 base. On the other hand, the smoothed DC signal on the side of the transistor T3 is applied to the base of the transistor T7 through an emitter follower consisting of a transistor T5 and a resistor R7 . At this time, when R 8 = R 9 = R and the current of the variable current source 14 is Io, when R>KT/qIo, the gain of the differential amplifier circuit using transistors T 6 and T 7 is R 10 /2R. It is well known that the gain of this differential amplifier circuit is not affected much by Io. Further, the current Io of the variable current source 14 is Vcc-1/2・IoR 10
gives the collector DC potential of transistor T7 with the relationship, and this directly applies to the transistor
It is added to the base of T8 to determine the white level of the video signal. The video signal is transmitted through the differential amplifier circuit described above, as well as transistor T8 and resistor 11.
The signal is guided to the output terminal 7 through an output circuit consisting of the following.

したがつてこの回路構成によれば、白レベルの
調整は可変電流源14の電流Ioを変えることによ
つて可能になり、ビデオ回路の利得に影響を及ぼ
さない。
Therefore, with this circuit configuration, the white level can be adjusted by changing the current Io of the variable current source 14 without affecting the gain of the video circuit.

一方、出力端子7の映像信号のピーク値は
IFAGC回路8の基準電圧回路9で得られる基準
電圧Vrefと比較されるが、この基準電圧Vrefは
上述の可変電流源14の電流Ioと無関係に決める
ことができるため、Ioを変えてもVrefは変化し
ない。したがつて本実施例回路では第1図の従来
回路のように、固定電圧源を2つ設けなくても、
電源6のただ一つで十分となる。
On the other hand, the peak value of the video signal at output terminal 7 is
It is compared with the reference voltage Vref obtained by the reference voltage circuit 9 of the IFAGC circuit 8, but since this reference voltage Vref can be determined independently of the current Io of the variable current source 14 described above, even if Io is changed, Vref is It does not change. Therefore, in this example circuit, unlike the conventional circuit shown in FIG. 1, there is no need to provide two fixed voltage sources.
Only one power source 6 is sufficient.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の白レベル調整回路図、第2図は
本発明の一実施例における白レベル調整回路であ
る。 1……映像信号中間周波増幅回路、2……検波
回路、3……映像増幅回路、4,7……外部端
子、5……可変抵抗、6……電源、8……中間周
波増幅利得調整回路、9……基準電源回路、10
……フイルター、T1〜T8……トランジスタ、R1
〜R11……抵抗。
FIG. 1 is a conventional white level adjustment circuit diagram, and FIG. 2 is a white level adjustment circuit according to an embodiment of the present invention. 1... Video signal intermediate frequency amplification circuit, 2... Detection circuit, 3... Video amplification circuit, 4, 7... External terminal, 5... Variable resistor, 6... Power supply, 8... Intermediate frequency amplification gain adjustment Circuit, 9...Reference power supply circuit, 10
...Filter, T 1 to T 8 ...Transistor, R 1
~R 11 ...Resistance.

Claims (1)

【特許請求の範囲】[Claims] 1 映像中間周波検波信号がベースに印加される
第1のトランジスタと、映像中間周波出力の平均
電圧がベースに印加されコレクタが第1の抵抗を
介して電源に接続された第2のトランジスタのエ
ミツタ間を第2および第3の抵抗の直列体を介し
て接続し、さらに前記抵抗の直列接続点に可変電
流源を接続して構成した差動増幅器と、前記第2
のトランジスタのコレクタにベースが接続され、
エミツタに出力端子が付設されたエミツタフオロ
ワ・トランジスタを備えてなり、前記エミツタフ
オロワ・トランジスタのエミツタを中間周波増幅
利得調整回路の基準電圧と比較される信号入力端
に結合したことを特徴とする白レベル調整回路。
1 The emitters of a first transistor to which a video intermediate frequency detection signal is applied to the base, and a second transistor to which the average voltage of the video intermediate frequency output is applied to the base and whose collector is connected to the power supply via the first resistor. a differential amplifier configured by connecting a second and a third resistor in series through a series connection point of the resistors, and further connecting a variable current source to the series connection point of the resistors;
The base is connected to the collector of the transistor,
White level adjustment comprising an emitter follower transistor having an output terminal attached to its emitter, the emitter of the emitter follower transistor being coupled to a signal input terminal to be compared with a reference voltage of an intermediate frequency amplification gain adjustment circuit. circuit.
JP56197501A 1981-12-07 1981-12-07 White level adjustment circuit Granted JPS5897979A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56197501A JPS5897979A (en) 1981-12-07 1981-12-07 White level adjustment circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56197501A JPS5897979A (en) 1981-12-07 1981-12-07 White level adjustment circuit

Publications (2)

Publication Number Publication Date
JPS5897979A JPS5897979A (en) 1983-06-10
JPH0251318B2 true JPH0251318B2 (en) 1990-11-07

Family

ID=16375517

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56197501A Granted JPS5897979A (en) 1981-12-07 1981-12-07 White level adjustment circuit

Country Status (1)

Country Link
JP (1) JPS5897979A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0640926U (en) * 1992-11-06 1994-05-31 株式会社吉井商会 Eye mirror

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0640926U (en) * 1992-11-06 1994-05-31 株式会社吉井商会 Eye mirror

Also Published As

Publication number Publication date
JPS5897979A (en) 1983-06-10

Similar Documents

Publication Publication Date Title
JP3135283B2 (en) Signal processing circuit device for absolute value detection
JPS631833B2 (en)
US4463319A (en) Operational amplifier circuit
JPH0251318B2 (en)
US6114909A (en) Differential amplifier for correcting offsets at inputs using low capacitance capacitor
JP2623954B2 (en) Variable gain amplifier
JPS5949728B2 (en) variable impedance circuit
JPH0326565B2 (en)
JPH05235660A (en) Noise detection circuit
JPH0724807Y2 (en) DC amplifier circuit
JP3088138B2 (en) Detection circuit
JPH026696Y2 (en)
JPS6153907B2 (en)
JPH062337Y2 (en) ALC circuit
JP2722769B2 (en) Gain control circuit
JPH0221775Y2 (en)
JPS6113403B2 (en)
JPS6246326Y2 (en)
JPH063469B2 (en) Bipolar voltage detection circuit
KR910007623Y1 (en) Circuit for balancing the levels of output signals of audio stereo system
JPS61295701A (en) Differential amplifier circuit type detector
JPH021608Y2 (en)
JPH0117847Y2 (en)
JP2725388B2 (en) Video signal average level detection circuit
JPH0345568B2 (en)