JPS5897979A - White level adjustment circuit - Google Patents

White level adjustment circuit

Info

Publication number
JPS5897979A
JPS5897979A JP56197501A JP19750181A JPS5897979A JP S5897979 A JPS5897979 A JP S5897979A JP 56197501 A JP56197501 A JP 56197501A JP 19750181 A JP19750181 A JP 19750181A JP S5897979 A JPS5897979 A JP S5897979A
Authority
JP
Japan
Prior art keywords
circuit
signal
intermediate frequency
video
white level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56197501A
Other languages
Japanese (ja)
Other versions
JPH0251318B2 (en
Inventor
Akio Yokoyama
明夫 横山
Hiroki Kinugawa
衣川 宏樹
Mitsuo Nanbae
難波江 光男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP56197501A priority Critical patent/JPS5897979A/en
Publication of JPS5897979A publication Critical patent/JPS5897979A/en
Publication of JPH0251318B2 publication Critical patent/JPH0251318B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/14—Picture signal circuitry for video frequency region
    • H04N5/16—Circuitry for reinsertion of DC and slowly varying components of signal; Circuitry for preservation of black or white level

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Television Receiver Circuits (AREA)

Abstract

PURPOSE:To control the output level of a differential amplifier and to prevent an adjustment of a white level from exerting an influence upon the gain of a video circuit by composing a detecting and amplifying circuit connecting to a video signal intermediate frequency circuit and a circuit for amplifying a DC signal component and a detection signal and a constant current source. CONSTITUTION:A video intermediate frequency signal from a video signal intermediate frequency amplifying circuit 1 is applied to bases of transistors (TRs) T2 and T3 through the emitter follower composed of a TR T1 and a resistance R1. At this time, the signal applied to the TR T3 is smoothed by the filter of a resistance R2 and a capacitance C2 into a DC signal, and the signal applied to the TR T2 is made into an intermediate frequency signal. The TR T2, a constant current source 12, and a capacitor C3 constitute a detecting circuit, whose detection signal is applied to a TR T4. The DC signal applied to the TR T3 is applied to the base of a TR T7 through an emitter follower TR T5. Then, DC levels of outputs of the TRs T6 and T7 constituting a differential amplifier are controlled to prevent an adjustment of a white level from exerting an influence upon the gain of an intermediate frequency amplification gain adjusting circuit 8.

Description

【発明の詳細な説明】 本発明は映像信号の白レベル調整回路に関するものであ
る。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a white level adjustment circuit for a video signal.

第1図は従来の白レベル調整回路である。以下図に従っ
て説明する。中間周波増幅回路1を径て、検波回路2で
検波された映像信号は映像増幅回路に加えられるが、検
波された映1象信号、映像増幅回路の増幅率には必ずバ
ラツキをもっているため、白レベルは各々異なってくる
。したがってこれらを調整するため白レベル調整が必要
となるが、従来、かかる白レベル調整の方式として、第
1図のように、映像増幅回路3の電源端子4に可変抵抗
6を介して固定電圧源6を加え、これにより同映像増幅
回路3の直流レベルを調整しようとするものが広く使用
されていた。これはAM変調された中間周波信号が負極
性であるときは、白レベルは映像増幅回路の直流レベル
とほとんど同じとなるためである。しかし一方映像増幅
回路3の信号出力は映像出力端子7を径で駆動回路へ行
くと同時に中間周波増幅利得調整(IFAGC)回路8
にも加えられる。この時同回路の動作機能として、ピー
クAGC方式の場合、映像信号出力のピーク値と上記I
FAGC回路8の基準電圧源9の所定電圧Vr e f
とを比較し、その差を検出して、フィルタ回路10を通
して上記中間周波増幅回路1に帰還制御がかけられる。
FIG. 1 shows a conventional white level adjustment circuit. The explanation will be given below according to the figures. The video signal detected by the detection circuit 2 passes through the intermediate frequency amplification circuit 1 and is applied to the video amplification circuit, but since there are always variations in the detected video signal and the amplification factor of the video amplification circuit, Each level is different. Therefore, white level adjustment is required to adjust these. Conventionally, as a method for such white level adjustment, as shown in FIG. 6 to adjust the DC level of the video amplification circuit 3 was widely used. This is because when the AM modulated intermediate frequency signal has negative polarity, the white level is almost the same as the DC level of the video amplification circuit. However, on the other hand, the signal output of the video amplification circuit 3 is sent to the drive circuit via the video output terminal 7 at the same time as the intermediate frequency amplification gain adjustment (IFAGC) circuit 8.
It can also be added to At this time, the operating function of the circuit is the peak value of the video signal output and the above I in the case of the peak AGC method.
Predetermined voltage Vr e f of the reference voltage source 9 of the FAGC circuit 8
The difference is detected and feedback control is applied to the intermediate frequency amplification circuit 1 through the filter circuit 10.

しかして、この方式でば、白レベル調整時に基準電圧V
refが変化しないようにするため、通常、上記IFA
GC増幅回路用電源9は映像増幅回路3の電源6と別電
源にしておく必要があり、固定電圧源11が必要となる
。とりわけ、映像増幅回路とIFAGC回路を同一チッ
プ内にIC化する場合においては、別々の固定電圧源が
必要となると、電源回路が複雑さに加えて、それ用の端
子も各別に必要となり、きわめて不都合である。
However, with this method, when adjusting the white level, the reference voltage V
In order to prevent the ref from changing, the above IFA is usually
The power supply 9 for the GC amplifier circuit needs to be a separate power supply from the power supply 6 of the video amplifier circuit 3, and a fixed voltage source 11 is required. In particular, when integrating a video amplification circuit and an IFAGC circuit into the same chip, separate fixed voltage sources are required, which adds to the complexity of the power supply circuit and requires separate terminals for each, which is extremely time consuming. It's inconvenient.

本発明はかかる困難を克服するものであシ以下に、第2
図に示す実施例により、本発明を詳述する。第2図にお
いて中間周波で変調され増幅された映1象中間周波信号
はトランジスタT1、抵抗R1よりなるエミッタ7オロ
ワを通じてトランジスタT2T3のベースに加えられる
。
The present invention overcomes such difficulties.
The invention will be explained in detail by means of embodiments shown in the figures. In FIG. 2, an image intermediate frequency signal modulated at an intermediate frequency and amplified is applied to the base of a transistor T2T3 through an emitter 7 lower comprising a transistor T1 and a resistor R1.

コノ時、上記トランジスタT3のベースへの久方信号は
抵抗R2と寄生容量C2で構成されるフィルタによって
平滑された直流信号となる。一方トランジスタT2のベ
ースへは抵抗R3とコンデンサC1よりなる高域フィル
タによって上記映像中間周波信号がそのまま加えられる
。トランジスタT2、定電流源12、コンデンサC3か
らなる検波回路により検波され(トランジスタT4のベ
ースに加えられ、さらに、検波された信号は、トランジ
スタT4 と抵抗R6よりなるエミッタフォロアを通し
てトランジスタT6のベースに加えられる。一方、上記
トランジスタテ3側の平滑された直流分信号はトランジ
スタT6と抵抗R7よりなるエミッタ7オロアを通して
トランジスタT7のベースに加えられる。この時とはよ
く知られ、工0によってこつ差動増幅回路の利得は影響
をあまりうけない。まだ、上記電流源13のtfiIo
はトランジスタT7のコレクタ直流電位を与え、これは
映像信号の白レベルを決定するものである。そして映像
信号は、上述の差動増幅回路ならびに、トランジスタT
8と抵抗R11よりなる出力回路を通して、出力端子7
に導かれる。
At this time, the signal sent to the base of the transistor T3 becomes a DC signal smoothed by a filter composed of a resistor R2 and a parasitic capacitor C2. On the other hand, the video intermediate frequency signal is directly applied to the base of the transistor T2 by a high-pass filter consisting of a resistor R3 and a capacitor C1. The signal is detected by a detection circuit consisting of a transistor T2, a constant current source 12, and a capacitor C3 (applied to the base of a transistor T4, and the detected signal is applied to the base of a transistor T6 through an emitter follower consisting of a transistor T4 and a resistor R6. On the other hand, the smoothed DC signal on the side of the transistor T3 is applied to the base of the transistor T7 through the emitter and the lower of the transistor T6 and the resistor R7. The gain of the amplifier circuit is not affected much.
gives the collector DC potential of the transistor T7, which determines the white level of the video signal. Then, the video signal is transmitted to the differential amplifier circuit and the transistor T.
8 and a resistor R11, the output terminal 7
guided by.

したがってこの回路構成によ・れば、白レベルの調整は
ビデオ回路の利得に影響を及ぼさない。
Therefore, according to this circuit configuration, adjustment of the white level does not affect the gain of the video circuit.

−力出力端子7のPIJJ信号のピーク値はIFAGC
回路8の基準電圧回路9で得られる基準電圧Vrefと
比較されるが、この基準電圧Vref  は−上述の可
変電流源工0と無関係に決めることができるため、工0
を変えてもVrefは変化しない。したがって本実施例
回路では第1図の従来回路ように、固定電圧源を2つ設
けなくても、電源6のただ−っで十分となる。
-The peak value of the PIJJ signal at power output terminal 7 is IFAGC.
It is compared with the reference voltage Vref obtained by the reference voltage circuit 9 of the circuit 8, but since this reference voltage Vref can be determined independently of the variable current source 0 described above, the
Even if Vref is changed, Vref does not change. Therefore, in the circuit of this embodiment, only one power supply 6 is sufficient without providing two fixed voltage sources as in the conventional circuit shown in FIG.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の白レベル調整回路図、第2図は本発明の
一実施例における白レベル調整回路図である。 1 ・・・・・・映像信号中間周波増幅回路、2・・・
1検波回路、3・・・・・・映像増幅回路、4,7・・
・・・・外部端子、6・・・山可変抵抗、6・・・・・
・電源、8・・・・・・中間周波増幅利得調整回路、9
・・・・・・基準電源回路、10・・・・・・フィルタ
ー、T1〜T8・・・・・・トランジスタ、R1−R1
11,””抵抗。
FIG. 1 is a conventional white level adjustment circuit diagram, and FIG. 2 is a white level adjustment circuit diagram according to an embodiment of the present invention. 1...Video signal intermediate frequency amplification circuit, 2...
1 detection circuit, 3... video amplification circuit, 4, 7...
...External terminal, 6...Mountain variable resistor, 6...
・Power supply, 8...Intermediate frequency amplification gain adjustment circuit, 9
...Reference power supply circuit, 10...Filter, T1-T8...Transistor, R1-R1
11,””Resistance.

Claims (1)

【特許請求の範囲】[Claims] 第1および第2のトランジスタよりなる差動増幅回路の
上記第1のトランジスタに映像検波信号を入力するとと
もに、映r象中間周波変調信号の平滑化で得られる直流
レベル信号により定電流回路の電流を制御して、同定電
流回路の信号レベルを上記第2のトランジスタに入力し
て、該差動増幅回路から出力の直流レベルを制御するこ
とを特徴とする白レベル調整回路。
A video detection signal is input to the first transistor of the differential amplifier circuit consisting of the first and second transistors, and a DC level signal obtained by smoothing the video intermediate frequency modulation signal is used to control the current of the constant current circuit. 2. A white level adjustment circuit, characterized in that the white level adjustment circuit controls the DC level of the output from the differential amplifier circuit by inputting the signal level of the identification current circuit to the second transistor.
JP56197501A 1981-12-07 1981-12-07 White level adjustment circuit Granted JPS5897979A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56197501A JPS5897979A (en) 1981-12-07 1981-12-07 White level adjustment circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56197501A JPS5897979A (en) 1981-12-07 1981-12-07 White level adjustment circuit

Publications (2)

Publication Number Publication Date
JPS5897979A true JPS5897979A (en) 1983-06-10
JPH0251318B2 JPH0251318B2 (en) 1990-11-07

Family

ID=16375517

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56197501A Granted JPS5897979A (en) 1981-12-07 1981-12-07 White level adjustment circuit

Country Status (1)

Country Link
JP (1) JPS5897979A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0640926U (en) * 1992-11-06 1994-05-31 株式会社吉井商会 Eye mirror

Also Published As

Publication number Publication date
JPH0251318B2 (en) 1990-11-07

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