JPH0252453A - Manufacture of dielectric isolation substrate - Google Patents

Abstract

PURPOSE:To prevent a shape of a deep separation island from being deformed and the dimensional accuracy of a shallow separation island from being deteriorated by a method wherein, after a U-shaped groove has been formed in a semiconductor substrate by using a first mask, a diffusion layer is formed and a V-shaped groove is formed in the semiconductor substrate by making use of the diffusion layer and a second mask as masks. CONSTITUTION:A region to be used as a shallow separation island in a semiconductor substrate 11 is etched by making use of a first mask composed of a patterned oxide film as a mask; U-shaped grooves 13 are formed. Then, ions of boron or the like are implanted into the substrate 11; an annealing operation is executed; a P-type diffusion layer 14 is formed on the bottom of the U-shaped grooves 13. In succession, the mask 12 is removed; after that, the semiconductor substrate 11 is oxidized again; an oxide film with a film thickness of about 1mum is formed; a mask 15 is formed in flat parts in regions to be used as deep separation islands. After that, an anisotropic etching operation is executed by making use of the mask 15 and the diffusion layer 14 as masks; V-shaped grooves 16 are formed in the substrate 11. After that, the mask 15 is removed in the same manner as in a conventional method; a separation insulating film 17 is formed; then, a supporter layer 18 is formed on it. Accordingly, it is not required to form a resist film in a recessed part; it is possible to prevent the dimensional accuracy from being deteriorated by a thick resist film in the shallow separation island.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a dielectric isolation substrate in which isolation islands of different depths are formed in a semiconductor substrate.

(Prior Art) Conventionally, in a semiconductor device having a dielectric isolation structure, when a high breakdown voltage element and a low breakdown voltage element are mounted together on the same dielectric isolation substrate, the separation island is divided depending on the characteristics of the internal elements. Attempts have been made to optimize the depth. For example, the isolation island where a high breakdown voltage element is formed is made deep according to the depletion layer width during reverse bias, and the isolation island where a low breakdown voltage element is formed is a vertical NPN.
The depth of each isolation island is varied, such as by making it shallower in order to cover a smaller collector resistance of a transistor.

In order to mix high-voltage and low-voltage semiconductor elements on the same substrate, there is a method for manufacturing a dielectric isolation substrate having isolation islands of different depths, for example, as described in Japanese Patent Laid-Open No.
105340@ There was something described in the official gazette. below,
The manufacturing method will be explained using figures.

FIGS. 2(a) to 2(f) are manufacturing process diagrams showing the conventional method for manufacturing a dielectric isolation substrate described in the above-mentioned document.

First, in FIG. 2(a), a semiconductor substrate 1 made of single crystal silicon having a (100) plane orientation is oxidized, and a pattern of an oxide film 2 is formed on the main surface by ordinary photolithography and etching. Next, as shown in FIG. 2(b), the semiconductor substrate 1 is anisotropically etched using the oxide film 2 as a mask to form the four parts 3.

Next, after removing the oxide film 2, the semiconductor substrate 1 is oxidized again as shown in FIG. . Thereafter, as shown in FIG. 2(d), anisotropic etching is performed again using the oxide film 4 as a mask to form a square-shaped groove 5.

Subsequently, after removing the oxide film 4, an isolation insulating film 6 is formed on the main surface including the V-shaped groove 5 of the semiconductor substrate 1, as shown in FIG. A support layer 7 made of silicon or the like is formed.

Thereafter, as shown in FIG. 2(f), the back side of the semiconductor substrate 1 is removed by polishing or the like until the tips of the V-shaped grooves 5 are exposed. As a result, isolation islands with different depths, that is, deep isolation islands 8 and shallow isolation islands 9, are formed in the isolation insulating film 6 and the support layer 7.
Dielectrically isolated substrates are obtained that are separated from each other via the .

(Problems to be Solved by the Invention) However, in the method for manufacturing a dielectric isolation substrate described above, there are problems in that the shape of the deep isolation islands 8 is distorted and the dimensional accuracy of the shallow isolation islands 9 is deteriorated, and it is difficult to solve these problems. It was difficult.

The process that causes the above problem will be explained with reference to FIGS. 3(a) and 3(b). Figures 3(a) and 3(b) are explanatory diagrams of the above-mentioned problem, where (a) corresponds to the process in Figure 2(C), and Figure 3(b) corresponds to the process in Figure 2(d). This corresponds to the process of

First, in FIG. 3(a), when patterning the oxide film 4, a resist film 10 is formed on the oxide film 4.
This resist film 10 becomes thinner at the stepped portion A of the four portions 3, and cannot sufficiently cover the oxide film 4. Therefore, when the oxide film 4 is etched next, the PE oxide film 4 remaining in the vicinity of the stepped portion A is also removed.

Therefore, in the next anisotropic etching process, the third
As shown in Figure (b), the stepped portion A is etched, resulting in a deformation B of the deep separation island 8.

Furthermore, as shown in FIG. 3 (a), the resist film 10 tends to be thickly formed in the recess 3 due to the presence of the stepped portion A, which may deteriorate the photolithographic accuracy. This causes the problem of deterioration.

If such deformation B and dimensional accuracy of the isolation islands 8 and 9 occur, the electrical characteristics of the semiconductor elements formed on the isolation islands 8 and 9 will be seriously affected.

The present invention provides an I! This is what we offer in six ways.

(Means for Solving the Problems) In order to solve the above problems, the present invention provides a method for manufacturing a dielectric isolation substrate in which isolation islands of different depths are formed in a semiconductor substrate. After forming a first mask and forming a U-shaped groove in the semiconductor substrate by etching using the first mask, and implanting impurity ions using the first mask as a shield, annealing is performed. forming a diffusion layer at the bottom of the U-shaped groove by forming a patterned second mask on the main surface after removing the first mask; forming a V-shaped groove in the semiconductor substrate by etching using the layer as a mask; forming an isolation insulating film over the entire main surface; and then forming a support layer on the isolation insulating film; The steps of removing the back side of the substrate until the tips of the V-shaped grooves are exposed and forming isolation islands of different depths on the back side are sequentially performed.

(Function) According to the present invention, since the method for manufacturing a dielectric isolation substrate is configured as described above, a U-shaped groove and a diffusion layer are formed in the semiconductor substrate using the first mask, and the diffusion layer and the diffusion layer are formed. 1. By forming a V-shaped groove using the second mask as a mask. There is no need to form a resist film in the recesses in the conventional manufacturing method. Therefore, it is possible to prevent deterioration in dimensional accuracy caused by a thick resist film on shallow isolation islands.

In addition, forming the U-shaped groove and the diffusion layer and using the diffusion layer as a mask eliminates the need to form a resist film at the four step portions in the conventional manufacturing method, and eliminates the need for forming a resist film at the four stepped portions in the conventional manufacturing method. It works to prevent the shape from deforming.

Therefore, it is possible to form a separation island having a predetermined shape and commercial accuracy, and the above-mentioned problem can be solved.

(Example) FIGS. 1(a) to 1(q) are manufacturing process diagrams showing a method for manufacturing a dielectric isolation substrate in an example of the present invention. The manufacturing method will be described below according to the manufacturing steps shown in the figures.

First, in Figure 1(a), d3 is an N-type (100
A semiconductor substrate 11 made of single-crystal silicon having a surface orientation of ) is oxidized, and a first mask 12 made of a patterned oxide film is formed on its main surface. This first mask 12 is formed by ordinary photolithography and etching, and has a film thickness of about 1 μm.

Next, as shown in FIG. 1(b), etching is performed using the first mask 12 as a mask in a region of the semiconductor substrate 11 that is to become a shallow isolation island, to form a 0-shaped groove 13 with a depth of about 20 μm. do.

At this time, anisotropic etching in which the etching rate ratio of the (100) plane, which is the main surface of the semiconductor substrate 11, and the (111) plane, which is the side wall of the 0-shaped groove 13, is different is not performed, but reactive ion etching or HNO3HF etching is performed. - Perform etching using a CH5COOH-based etching solution. At this time, it is desirable that the bottom surface of the 0-shaped groove 13 be formed to have a shape that is a vertical projection of the open pattern of the first mask 12, or a size larger than that. By doing this, it is possible to form shallow isolated islands with higher precision.

Next, as shown in FIG. 1C, using the first mask 12 again as a mask, P-type impurities such as boron are ion-implanted into the semiconductor substrate 11 and annealed to form a A P swelling diffusion layer 14 having a concentration of 0 cm -3 or more is formed.

Subsequently, as shown in FIG. 1(d), after removing the first mask 12, the semiconductor substrate 11 is oxidized again to form an oxide film with a thickness of about 1 μm, and this is patterned by ordinary photorin etching. Then, the second mask 15 is formed only on the flat portion of the region that is to become a deep isolation island.

Thereafter, as shown in FIG. 1(e), anisotropic etching is performed using the second mask 15 and the P expansion diffusion layer 14 as masks to form a V-shaped groove 16 in the semiconductor substrate 11. At this time, if, for example, a KOH aqueous solution is used as the anisotropic etching solution, the high concentration P swelling diffusion layer 14 serves as an etching mask.

Next, if the J, urchin, and P swelling diffusion layer 14 shown in FIG.
Remove with OH-based etching solution. Thereafter, the second mask 15 is removed using a method similar to the conventional manufacturing method, and an isolation insulating film 17 having a thickness of about 1 to 2 μm is formed on the main surface of the semiconductor substrate 11 including the V-shaped groove 16. Next, the isolation insulating film 17
A support layer 18 made of polycrystalline silicon or the like is formed thereon.

At this time, the thickness of the support layer 18 is made to be approximately the same as that of the semiconductor substrate 11.

Finally, as shown in FIG. 1(g), the back side of the semiconductor substrate 11 is removed by polishing or the like until the tips of the grooves 16 are exposed. As a result, the deep isolation island 19 and the shallow isolation island 20 are separated from each other via the isolation insulating film 17 and the support layer 18, and a desired dielectric isolation substrate is obtained.

As described above, in this embodiment, after the 0-shaped groove 13 is formed in the region that will become the shallow isolation island 20, the 0-shaped groove 13 is
The first mask 12 used for forming 3 is used again as a mask for ion implantation, and the P expansion diffusion layer 14 is formed.

Further, a second mask 15 is formed by photolithography only in the region that will become the deep isolation island 19. Therefore, it is not necessary to form a resist film on the four step portions or on the inner surface of the recess as in the prior art. Therefore, it is possible to reliably prevent the deformation of the deep separation islands 19 and the deterioration of the dimensional accuracy of the shallow separation islands 20.

Note that the present invention is not limited to the illustrated embodiment, and various modifications are possible. For example, the polarities of the N-type semiconductor substrate 11 and the P-swelled diffusion layer 14 may be changed, or the combination threads and shapes of the isolation islands 19 and 20 may be changed. In addition, the materials, film thicknesses, processing methods, etc. exemplified in the examples may be changed as necessary.
Alternatively, modifications such as adding other steps to part of the manufacturing process are also possible.

(Effects of the Invention) As described in detail above, according to the present invention, after forming a U-shaped groove in a semiconductor substrate using the first mask, forming a diffusion layer using the first mask again, The diffusion layer and the second
Since the V-shaped groove is formed in the semiconductor substrate using the mask as a mask, it is not necessary to form a resist film on the stepped portion of the recess or the inner surface of the recess as in the conventional manufacturing method.

. Therefore, it is possible to reliably prevent deformation of the deep isolation islands and deterioration of the dimensional accuracy of the shallow isolation islands. Therefore, it is possible to form a semiconductor element on a highly precise isolation island having a predetermined shape, and its electrical characteristics can be significantly improved.

[Brief explanation of the drawing]

FIGS. 1(a) to 1(g) show a method for manufacturing a dielectric isolation substrate in an embodiment of the present invention.V manufacturing process diagrams, FIGS. 2(a) to
(f) is a manufacturing process diagram showing a conventional method for manufacturing a dielectric valve@substrate, and FIG. 3(a). (b) is an explanatory diagram of problems in the conventional manufacturing method. DESCRIPTION OF SYMBOLS 11... Semiconductor substrate, 12... First mask, 13... U-shaped groove, 14...
P swelling diffusion layer, 15...Second mask, 16...
... V-shaped groove, 17 ... Isolation insulating film, 18
......Support layer, 19.20...minute 11
island.

Claims (1)

[Claims] A method for manufacturing a dielectric isolation substrate in which isolation islands of different depths are formed in a semiconductor substrate, comprising: forming a patterned first mask on the main surface of the semiconductor substrate; forming a U-shaped groove in the semiconductor substrate by etching using the first mask; and implanting impurity ions using the first mask as a shield, and then annealing to form a diffusion layer at the bottom of the U-shaped groove. After removing the first mask, forming a patterned second mask on the main surface, and etching using the second mask and the diffusion layer as a mask to form a V-shaped groove in the semiconductor substrate. After forming an isolation insulating film over the entire main surface, forming a support layer on the isolation insulating film, and exposing the tip of the V-shaped groove on the back side of the semiconductor substrate. Remove until
and forming isolation islands of different depths on the back surface side.