JPH0252544A - Fsk modulator - Google Patents

Abstract

PURPOSE:To avoid the production of a discontinuous point of an FSK signal at a change point of a PCM data by storing a sinusoidal wave signal to a ROM 9 and changing a speed reading the storage data of the ROM depending on the PCM data. CONSTITUTION:When the PCM data is logical '0', a selector 3 gives an output signal of the 1st frequency divider 6 frequency-dividing the frequency (f) of an oscillator 5 by f/K to a counter 8, and the data of the sinusoidal wave signal being the result of division of one period stored in a ROM 9 at a speed of f/K by 2M equally is read in order. Moreover, when the PCM data is logical 1, an output signal of the 2nd frequency divider 7 frequency-dividing the frequency (f) of the oscillator 5 by f/L is fed to the counter 8 and the data of the ROM 9 is read in order at a speed of f/L. When the PCM data is changed in this way, the operating speed of the counter 8 is changed and the data read from the ROM 9 is changed continuously, then no discontinuous point is generated at the analog signal output of a D/A conversion circuit 10. Thus, no discontinuous point of the FSK signal is caused at the change point of the PCM data.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to an FSK modulation device in which the frequency of a carrier wave is changed according to PCM data.

[Conventional technology]

Conventionally, there has been a device of this type as shown in FIG. Third
In the figure, (l) is the first oscillator that oscillates at the first carrier frequency, (2) is the second oscillator that oscillates at the second carrier frequency, and (3) is one of the two input signals according to the selection signal. A selector that selects and outputs one of the
(3a) H selection signal input terminal of the above selector (3);
(sb) is the first input signal terminal of the selector (3), (3c) is the second input signal terminal of the selector (3), (Sd) U is the output signal terminal of the selector (31).

(4) is filtered out.

The conventional FSK modulation device is configured as described above, and the selection signal terminal (3a) of the selector (3) has “0#” or “1#”.
PCM data is input. Selector (3) is PCM
When data "0" is input, the signal of the 10th frequency divider (1) input to the first input terminal (5b) is transferred to the output terminal (
3d). Furthermore, when PCM data @1'' is input, the signal of the second oscillator (2) input to the second input terminal (3c) is output to the output terminal (3d).

The signals between the PCM data and the output terminal (3d) of the selector (3) are as shown in FIG. 4, and an FSX signal whose carrier frequency changes depending on the PCM data is obtained.

FSX obtained at output terminal (3d) of selector (3)
Since the first oscillator (1) and the second oscillator each oscillate independently, the signal is Discontinuities occur. Filter (4) f'i smoothes this discontinuity.

[Problem to be solved by the invention]

Since the conventional FSK modulation device is configured as described above, it is impossible to avoid the occurrence of discontinuous points in the FSK signal at the change points of the PCM data, so the filter (4)
If the carrier frequency changes,
The problem was that the characteristics of the filter had to be changed accordingly.

This invention was made to solve the above-mentioned problems, and is an FSX modulation system in which discontinuities in the FSK signal do not occur at changing points of PCM data without using a filter.
The purpose is to obtain.

[Means to solve the problem]

The FSK modulation device according to the present invention includes first and 20th frequency dividers that divide the output signal of a single excavator with different frequency division ratios, and divides the first or second frequency divider according to PCM data. The output signal of the frequency generator is selected and supplied to the counter, and the count value of this counter is used as the ROM address signal to read out the data stored in the ROM, and the data stored in the ROM is read out.
This is converted into an analog signal by the A conversion circuit.

[Effect]

ROM1j, P storing the sine wave signal in this invention
Depending on the CM data, only the reading speed of the stored data changes, but the order in which the stored data is read does not change.
No discontinuity point occurs in the output signal even at the change point of the PCM data.

〔Example〕

FIG. 1 is a diagram showing one embodiment of the present invention.

In FIG. 1, (3) and (3a) to (3d) are exactly the same as the conventional device described above. +51 is the frequency f
(C) is the first frequency divider that divides the clock signal by 1/K, (7) is the second frequency divider that divides the clock signal by 1/L, (8) is a counter that counts the clock signal from 1 to 2;
′! ROMaG stored in order converts a digital signal with a quantization number of N bits into an analog signal [)/A
It is a conversion circuit.

In the F S Ki adjustment device modulated as described above, the clock signal output from the 9th oscillator (5) is divided into 1/K by the 10th frequency divider (6), and the frequency is divided by 1/K by the 10th frequency divider (6).
7), and are respectively supplied to the first input signal terminal (3b) and the second input signal terminal (3c) of the selector (3). The selector (3) selects the first input terminal (3b) or the second input terminal (
3c) is selected and supplied to the counter (8). Counter f81 counts this clock signal from 1 to 2, and the count value of counter (8) is R.
OM +41) address signal input.

As shown in Figure 2, the memory contents of ROM +91 are as follows: One address is 360 degrees, with the address as the time axis of the sine wave signal.
/2, and the stored data is the amplitude of a sine wave quantized by zN bits, and each small value is 1. The maximum value is 2. The digital signal read from the ROM +1 is converted into an analog signal No. 43 by the D/A conversion circuit 01.

When the PCM data is 101, the selector (3) supplies a clock signal obtained by dividing the frequency f of the oscillator (5) by 17K to the counter (8). The counter (8) sequentially reads data from the ROM (91) at a speed of f/.

Since ROM+91 stores the data of a sine wave signal obtained by dividing one cycle into two equal parts, at this time ROM(9)
The frequency of the sine wave signal read from is f/(K・2
).

Similarly, when the PCM data is 1#, the frequency of the sine wave signal read from ROM +91 is r/(L・2
).

PCM data is @0" to @1" or 1" to '"0
”, the counter (8) indicates that the frequency of the supplied clock signal changes from f/K to r/L or from f/L to f/
K, and the operating speed of the counter changes. However, the count value of the counter (8) changes continuously, and the ROM (
Since the data read from 91 also changes continuously,
No discontinuity point occurs in the analog signal output of the D/A conversion circuit αG. Therefore, without using a filter, FSK signal discontinuities do not occur at changing points of PCM data.
An SK modulator is obtained.

Note that in the above embodiment, the counter 181i! 1, 2.・・・
・I showed something that counts up to 2.

22-1. ...It may be something that counts down to 1.

〔Effect of the invention〕

As described above, according to the present invention, a sine wave signal is stored in a ROM, and the speed at which data stored in this ROM is read is total P.
The PC was configured to change the cm data.
A discontinuous point of the FSK signal does not occur at a change point of M data.

Further, since no discontinuous points occur in the FSK signal, there is an effect that a filter is not required.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of this invention, FIG. 2 is a diagram showing the storage contents of a ROM of this invention, and FIG. 3 is a diagram showing a conventional FSK.
FIG. 4 is a diagram showing input and output signals of a selector of a conventional FSK modulation device. In the figure, tllt'! (2) is the second oscillator, (3) is the selector, (5a) is the selection signal input terminal of the selector (3), (3b) is the selector (
3), the first input signal terminal (5c) is the selector (
3) second input signal terminal. (3d) is the output signal terminal of the selector (3), and (4) is a filter. (5) is excavation 3. (61 is the first frequency dividing circuit, (7) is the second frequency dividing circuit, (81 is the counter, (91t! RO
M, Qllt'i, D/A conversion circuit. Note that the same reference numerals in each figure indicate the same or corresponding parts. Figure 2 Figure 3

Claims (1)

[Claims] an oscillator that oscillates at a frequency f; a first frequency divider that divides the output signal of the oscillator into 1/K; and a second frequency divider that divides the output signal of the oscillator into 1/L; A selector that selects and outputs either the first or second frequency divider signal according to the transmitted PCM data, and an M that counts from 1 to 2^M according to the signal output from the selector.
a bit counter, a ROM in which one period of a sine wave is divided into 2^M equal parts by using the count value of the counter as an address signal input, and the value of the sine wave at each dividing point is stored as a quantization number N bits; An FSK modulation device comprising a D/A conversion circuit that converts stored data into an analog signal.