JPH0252861B2 - - Google Patents

Info

Publication number
JPH0252861B2
JPH0252861B2 JP59099680A JP9968084A JPH0252861B2 JP H0252861 B2 JPH0252861 B2 JP H0252861B2 JP 59099680 A JP59099680 A JP 59099680A JP 9968084 A JP9968084 A JP 9968084A JP H0252861 B2 JPH0252861 B2 JP H0252861B2
Authority
JP
Japan
Prior art keywords
multilayer
inorganic material
alumina
thermal conductivity
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59099680A
Other languages
Japanese (ja)
Other versions
JPS60245154A (en
Inventor
Hirozo Yokoyama
Yoshihiko Imanaka
Kazuaki Kurihara
Kishio Yokochi
Hiromi Ogawa
Nobuo Kamehara
Koichi Niwa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP59099680A priority Critical patent/JPS60245154A/en
Publication of JPS60245154A publication Critical patent/JPS60245154A/en
Publication of JPH0252861B2 publication Critical patent/JPH0252861B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69Insulating materials thereof
    • H10W70/692Ceramics or glasses
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01Manufacture or treatment
    • H10W70/05Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers

Landscapes

  • Die Bonding (AREA)

Description

【発明の詳細な説明】[Detailed description of the invention]

a 発明の技術分野 本発明は、半導体装置実装用多層基板、より詳
しく述べるならば、特に、IC、LSIなどの半導体
チツプを複数個搭載する多層セラミツク回路基板
に関するものである。 b 技術の背景 半導体装置(例えば、LSI)は、近年、高性
能・高集積化されてきているとはいえ、複数の
LSIチツプでもつてひとつのシステム(あるいは
ユニツト)を構成する場合に、従来の実装方法で
はひとつのチツプを有するDIP形パツケージを複
数個プリント基板に取り付けていた。しかしなが
ら、この実装方法ではチツプ間を接続する配線や
負荷による遅延時間が問題となり、より高密度実
装する方法が提案された。例えば、合成樹脂材料
を用いた多層回路基板に複数チツプを搭載する方
法であり、この場合には、チツプの発熱が問題と
なつて、合成樹脂基板は耐熱が不十分であり、熱
伝導率が小さく、そして熱膨張係数がチツプの半
導体材料と違つているなどの問題がある。一方、
多層セラミツク回路基板は合成樹脂製のものより
も耐熱性および熱伝導性が良く、かつ熱膨張係数
がチツプ半導体に近いので、各種の提案がなされ
ている(例えば、田村敬;「マルチチツプパツケ
ージ用セラミツク多層基板」、電子材料、Vol.21,
No.11,1982年11月号、(株)工業調査会、pp.64−69,
74,参照)。 c 従来技術と問題点 多層セラミツク回路基板をアルミナとガラスと
の混合物の焼成によつて構成する場合に、アルミ
ナの割合が高いと焼成温度も高くなり、配線導体
にモリブデン又はタングステンなどの高融点金属
材料を用いなければならない。しかしながら、こ
れら高融点金属材料では電気抵抗が比較的高いの
で、銅、金、銀あるいはいずれかの合金などの高
導電性金属材料を使用することが望ましい。ま
た、アルミナは誘電率が8〜9.5と高く信号の伝
導遅延につながるので、誘電率のより小さい材料
の割合を高めた混合物を使用するのが望ましい。
そこで、アルミナと比べると融点が低くかつ誘電
率が低いガラスの割合を高めて、焼成温度をこれ
ら高導電性金属材料の融点(銅の融点1083℃、金
の融点1063℃、銀の融点961℃)よりも低くし、
かつ誘電率を下げた多層セラミツク基板が提案さ
れていた。この場合には、アルミナおよびほうけ
い酸ガラス等からなる基体と銅等の高導電性材料
との焼成基板である。この焼成基板では焼成温度
が700ないし900℃と比較的低く設定されており、
バインダー抜きが十分に行なわれないので回路基
板の絶縁耐圧が低くなる欠点があつた。また、セ
ラミツク基板の放熱効率をもつと高めるために、
基板の熱伝導率の向上が求められている。 d 発明の目的 本発明の目的は、十分なバインダー抜きを行な
うことができて絶縁耐圧が向上され、かつ熱伝導
率が高められた半導体装置実装用多層基板である
多層セラミツク回路基板を提供することである。 e 発明の構成 上述の目的は、高導電性金属配線層を有し、ほ
うけい酸ガラスと、アルミナと、熱伝導率がこれ
らよりも高くかつ融点が比較的高い無機材料との
混合物焼成体からなる半導体装置実装用多層基板
によつて達成される。 高導電性金属配線層は、銅、金、銀又はこれら
金属のいずれかの合金であることが好ましい。 また、熱伝導率が高くかつ融点が比較的高い無
機材料には、ベリリア(BeO)、炭化ケイ素
(SiC)又はダイヤモンド(C)の粉体が好まし
い。 混合物を焼成する温度は、バインダー抜きを十
分に行なうために、従来より高く上述の金属配線
層の融点よりも少し低い温度であるのが好まし
く、そうなるようにほうけい酸ガラスと、アルミ
ナと、ベリリア、炭化ケイ素又はダイヤモンドと
の混合割合を、ほうけい酸ガラス:25〜55wt%
(好ましくは30〜35wt%);アルミナ:50〜5wt%
(好ましくは40〜30wt%);およびベリリア、炭
化ケイ素又はダイヤモンド:25〜55wt%(好ま
しくは30〜35wt%)とするのが望ましい。 炭化ケイ素およびダイヤモンドを用いる場合に
は、さらに、基板の機械的強度、特に、硬度を向
上させる利点がある。 f 実施例 以下、本発明を下記実施例によつてより詳細に
説明する。 実施例 1 アルミナ粉末、ほうけい酸ガラス粉末およびベ
リリア粉末をポリエチレンポツトに入れ、さらに
溶剤、可塑剤、樹脂のバインダーを加えて48時間
ボールミリングしてスラリーとした。このスラリ
ーの組成を第1表に示す。
a. Technical Field of the Invention The present invention relates to a multilayer substrate for mounting semiconductor devices, and more specifically, to a multilayer ceramic circuit board on which a plurality of semiconductor chips such as ICs and LSIs are mounted. b. Background of the technology Although semiconductor devices (such as LSI) have become more sophisticated and highly integrated in recent years,
When configuring a system (or unit) using LSI chips, the conventional mounting method was to attach multiple DIP packages each containing one chip to a printed circuit board. However, with this mounting method, there was a problem with the delay time caused by the wiring and loads that connect the chips, and a method for higher-density mounting was proposed. For example, there is a method of mounting multiple chips on a multilayer circuit board using a synthetic resin material. It has problems such as being small and having a different coefficient of thermal expansion than the semiconductor material of the chip. on the other hand,
Multilayer ceramic circuit boards have better heat resistance and thermal conductivity than those made of synthetic resin, and have a thermal expansion coefficient close to that of chip semiconductors, so various proposals have been made (for example, Takashi Tamura's "For Multi-Chip Packages"). "Ceramic multilayer substrate", Electronic Materials, Vol.21,
No. 11, November 1982, Industrial Research Association Co., Ltd., pp. 64-69,
74, see). c. Prior art and problems When constructing a multilayer ceramic circuit board by firing a mixture of alumina and glass, if the proportion of alumina is high, the firing temperature will also be high; material must be used. However, since these high melting point metal materials have relatively high electrical resistance, it is desirable to use highly conductive metal materials such as copper, gold, silver, or an alloy of any of them. Further, since alumina has a high dielectric constant of 8 to 9.5, which leads to a delay in signal conduction, it is desirable to use a mixture containing a higher proportion of a material with a lower dielectric constant.
Therefore, we increased the proportion of glass, which has a lower melting point and dielectric constant than alumina, to lower the firing temperature to the melting points of these highly conductive metal materials (copper melting point 1083°C, gold melting point 1063°C, silver melting point 961°C). ),
A multilayer ceramic substrate with a lower dielectric constant has been proposed. In this case, it is a fired substrate made of a base made of alumina, borosilicate glass, etc., and a highly conductive material such as copper. For this fired substrate, the firing temperature is set relatively low at 700 to 900°C.
The drawback was that the dielectric strength of the circuit board was low because the binder was not removed sufficiently. In addition, in order to increase the heat dissipation efficiency of the ceramic substrate,
There is a need to improve the thermal conductivity of substrates. d. Purpose of the Invention The purpose of the present invention is to provide a multilayer ceramic circuit board, which is a multilayer board for mounting semiconductor devices, which can perform sufficient binder removal, has improved dielectric strength, and has increased thermal conductivity. It is. e.Structure of the Invention The above-mentioned object has a highly conductive metal wiring layer and is made from a fired mixture of borosilicate glass, alumina, and an inorganic material having a higher thermal conductivity than these and a relatively high melting point. This is achieved by a multilayer substrate for mounting semiconductor devices. The highly conductive metal wiring layer is preferably made of copper, gold, silver, or an alloy of any of these metals. Further, as the inorganic material having high thermal conductivity and a relatively high melting point, beryllia (BeO), silicon carbide (SiC), or diamond (C) powder is preferable. The temperature at which the mixture is fired is preferably higher than conventional temperatures and slightly lower than the melting point of the above-mentioned metal wiring layer in order to sufficiently remove the binder. Mixing ratio with beryllia, silicon carbide or diamond: borosilicate glass: 25-55wt%
(preferably 30-35wt%); Alumina: 50-5wt%
(preferably 40 to 30 wt%); and beryllia, silicon carbide, or diamond: 25 to 55 wt% (preferably 30 to 35 wt%). The use of silicon carbide and diamond also has the advantage of improving the mechanical strength, particularly the hardness, of the substrate. f Examples Hereinafter, the present invention will be explained in more detail with reference to the following examples. Example 1 Alumina powder, borosilicate glass powder, and beryllia powder were placed in a polyethylene pot, and a solvent, a plasticizer, and a resin binder were added, and the mixture was ball-milled for 48 hours to form a slurry. The composition of this slurry is shown in Table 1.

【表】【table】

【表】 このスラリーをドクターブレード法によつて厚
さ0.34mmのグリーンシートに成形した。このグリ
ーンシートを所定形状に切断し、バイヤホール形
成の打抜きを行つた。粘度を300〜1000P(ポア
ズ)に調整した銅ペーストをスクリーン印刷法で
もつて、まずバイヤホールに充填し、次に信号層
あるいは電源層となる導体配線パターンをグリー
ンシート上に形成した。このようなグリーンシー
トを積層して、130℃に加熱しながら30分間
30MPaの加圧でラミネートした。積層した未焼
成基板を銅ペーストが酸化しないように窒素雰囲
気中にて焼成した。焼成は、まず樹脂バインダー
抜きを行なうために810℃の温度で10時間、水
(7%のH2O)を含有した窒素雰囲気中で加熱
し、次に酸素濃度を5ppm以下にした窒素雰囲気
中で1000℃の温度で10時間加熱することによつて
行なつた。酸素濃度はできるだけ低くしたほうが
良いが、市販の窒素ガスには2〜3ppmの酸素が
含有されていることなどから多少存在するも、こ
の程度であれば実際上は問題ない。 このようにして作られた多層セラミツク回路基
板は、その焼成密度が98.5%以上と高く、誘電率
が5.2と低いので回路基板の伝送遅延は80PS/cm
と小さく、そして樹脂バインダーの炭素残渣が
30ppmと少ないので高い絶縁耐圧を示した。ま
た、熱伝導率は0.133Cal/cm・sec・degであり、
比較例としてのアルミナ50wt%とほうけい酸ガ
ラス50wt%との混合物焼結基板の場合である
0.011Cal/cm・sec・degよりも大きい。 実施例 2 実施例1でのベリリア粉末の代わりに窒化ケイ
素粉末を用いて第2表のスラリー組成として、実
施例1と同じ工程で銅ペーストの導体パターンを
有するグリーンシートを形成した。
[Table] This slurry was formed into a green sheet with a thickness of 0.34 mm by the doctor blade method. This green sheet was cut into a predetermined shape and punched to form a via hole. Copper paste with a viscosity adjusted to 300 to 1000 P (poise) was applied by screen printing and filled into the via holes, and then a conductive wiring pattern that would become the signal layer or power layer was formed on the green sheet. Stack these green sheets and heat them to 130℃ for 30 minutes.
Laminated under pressure of 30MPa. The laminated unfired substrates were fired in a nitrogen atmosphere to prevent the copper paste from oxidizing. Firing was performed by first heating at a temperature of 810°C for 10 hours in a nitrogen atmosphere containing water (7% H 2 O) to remove the resin binder, and then in a nitrogen atmosphere with an oxygen concentration of 5 ppm or less. This was done by heating at a temperature of 1000°C for 10 hours. It is better to keep the oxygen concentration as low as possible, but commercially available nitrogen gas contains 2 to 3 ppm of oxygen, so although some oxygen is present, there is no problem in practice as long as it is at this level. The multilayer ceramic circuit board made in this way has a high firing density of over 98.5% and a low dielectric constant of 5.2, so the transmission delay of the circuit board is 80PS/cm.
and small, and the carbon residue of the resin binder is
Since the content was as low as 30 ppm, it exhibited high dielectric strength. In addition, the thermal conductivity is 0.133 Cal/cm・sec・deg,
This is the case of a sintered substrate of a mixture of 50wt% alumina and 50wt% borosilicate glass as a comparative example.
Greater than 0.011Cal/cm・sec・deg. Example 2 A green sheet having a conductive pattern of copper paste was formed in the same process as in Example 1 using silicon nitride powder instead of the beryllia powder in Example 1 and using the slurry composition shown in Table 2.

【表】 得られたグリーンシートを積層して、130℃に
加熱しながら30分間30MPaの加圧でラミネート
した。ラミネートされて一体化したものを実施例
1での銅ペーストが酸化しないように窒素雰囲気
中にて焼成した。焼成は、まず、810℃にて8時
間、水(7%のH2O)を含有した窒素雰囲気中
で加熱し、次に、酸素濃度を5ppm以下にした窒
素雰囲気中で1000℃にて5時間加熱することによ
つて行なつた。 このようにして作られた多層セラミツク回路基
板は、その焼成密度が98.5%以上と高く、誘電率
が5.0と低いので回路基板の伝送遅延は79PS/cm
と小さく、そして炭素残渣が30ppmと少ないので
高い絶縁耐圧を示した。また、熱伝導率は
0.09Cal/cm・sec・degであつた。 実施例 3 実施例1でのベリリア粉末の代わりに人造ダイ
ヤモンド粉末(粒子径5μm程度)を用いて第2表
のスラリー組成AおよびBとして、実施例1と同
じ工程で銅ペーストの導体パターンを有するグリ
ーンシートを形成した。
[Table] The obtained green sheets were stacked and laminated under a pressure of 30 MPa for 30 minutes while heating to 130°C. The laminated and integrated product was fired in a nitrogen atmosphere so that the copper paste in Example 1 would not be oxidized. Firing was performed by first heating at 810°C for 8 hours in a nitrogen atmosphere containing water (7% H 2 O), then heating at 1000°C for 5 hours in a nitrogen atmosphere with an oxygen concentration of 5 ppm or less. This was done by heating for a period of time. The multilayer ceramic circuit board made in this way has a high firing density of over 98.5% and a low dielectric constant of 5.0, so the transmission delay of the circuit board is 79PS/cm.
It is small in size and contains only 30 ppm of carbon residue, so it exhibits high dielectric strength. Also, the thermal conductivity is
It was 0.09 Cal/cm・sec・deg. Example 3 Synthetic diamond powder (particle size of about 5 μm) was used instead of the beryllia powder in Example 1, and slurry compositions A and B in Table 2 were prepared using the same process as in Example 1 to form a copper paste conductor pattern. A green sheet was formed.

【表】【table】

【表】 得られたグリーンシートを積層して、130℃に
加熱しながら30分間35MPaの加圧でラミネート
した。ラミネートされて一体化したものを実施例
1での銅ペーストが酸化しないように窒素雰囲気
中で1000℃の温度にて30分間加熱して焼成した。 このようにして作られた多層セラミツク回路基
板は、その焼成密度が98.5%以上と高く、誘電率
が5.5と低いので回路基板の伝送遅延は82PS/cm
と小さく、そして炭素残渣が30ppmと少ないので
高い絶縁耐圧を示した。 また、得られた焼成基板の熱伝導率および硬度
は第4表に示すようになつた。なお、比較例とし
て、アルミナ50wt%とほうけい酸ガラス50wt%
との混合物焼成基板を同じ条件で作つたものの熱
伝導率および硬度も第4表に示す。
[Table] The obtained green sheets were stacked and laminated under a pressure of 35 MPa for 30 minutes while heating to 130°C. The laminated and integrated product was fired by heating at a temperature of 1000° C. for 30 minutes in a nitrogen atmosphere so that the copper paste in Example 1 would not be oxidized. The multilayer ceramic circuit board made in this way has a high firing density of over 98.5% and a low dielectric constant of 5.5, so the transmission delay of the circuit board is 82PS/cm.
It is small in size and contains only 30 ppm of carbon residue, so it exhibits high dielectric strength. Further, the thermal conductivity and hardness of the obtained fired substrate were as shown in Table 4. As a comparative example, 50wt% alumina and 50wt% borosilicate glass
Table 4 also shows the thermal conductivity and hardness of a mixture fired substrate made under the same conditions.

【表】 g 発明の効果 本発明によれば、銅などの高導電性金属配線層
を有しており、樹脂バインダーが十分に分解飛散
して炭素残渣の少ないことによる絶縁耐圧が高く
かつ熱伝導率の高いセラミツク焼成体の半導体装
置実装用多層基板が得られる。1個のLSIチツプ
を収容するセラミツクパツケージにも本発明の多
層基板が使用できる。
[Table] g Effects of the Invention According to the present invention, it has a highly conductive metal wiring layer made of copper, etc., and the resin binder is sufficiently decomposed and scattered, resulting in high dielectric strength and thermal conductivity due to less carbon residue. A multilayer substrate for mounting a semiconductor device made of a ceramic fired body with a high efficiency can be obtained. The multilayer substrate of the present invention can also be used in a ceramic package that accommodates one LSI chip.

Claims (1)

【特許請求の範囲】 1 高導電性金属配線層を有し、ほうけい酸ガラ
スと、アルミナと、熱伝導率がこれらよりも高く
かつ融点が比較的高い無機材料との混合物焼成体
からなる半導体装置実装用多層基板。 2 前記高導電性金属配線層は、銅、金、銀、又
はこれら金属のいずれかの合金からなる特許請求
の範囲第1項記載の多層基板。 3 前記無機材料がベリリアである特許請求の範
囲第1項記載の多層基板。 4 前記無機材料が炭化ケイ素である特許請求の
範囲第1項記載の多層基板。 5 前記無機材料がダイヤモンドである特許請求
の範囲第1項記載の多層基板。
[Claims] 1. A semiconductor having a highly conductive metal wiring layer and consisting of a fired mixture of borosilicate glass, alumina, and an inorganic material having a higher thermal conductivity than these and a relatively high melting point. Multilayer board for device mounting. 2. The multilayer board according to claim 1, wherein the highly conductive metal wiring layer is made of copper, gold, silver, or an alloy of any of these metals. 3. The multilayer substrate according to claim 1, wherein the inorganic material is beryllia. 4. The multilayer substrate according to claim 1, wherein the inorganic material is silicon carbide. 5. The multilayer substrate according to claim 1, wherein the inorganic material is diamond.
JP59099680A 1984-05-19 1984-05-19 Multilayer substrate for mounting semiconductor device Granted JPS60245154A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59099680A JPS60245154A (en) 1984-05-19 1984-05-19 Multilayer substrate for mounting semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59099680A JPS60245154A (en) 1984-05-19 1984-05-19 Multilayer substrate for mounting semiconductor device

Publications (2)

Publication Number Publication Date
JPS60245154A JPS60245154A (en) 1985-12-04
JPH0252861B2 true JPH0252861B2 (en) 1990-11-14

Family

ID=14253743

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59099680A Granted JPS60245154A (en) 1984-05-19 1984-05-19 Multilayer substrate for mounting semiconductor device

Country Status (1)

Country Link
JP (1) JPS60245154A (en)

Also Published As

Publication number Publication date
JPS60245154A (en) 1985-12-04

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