JPH025302B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a field effect transistor and an integrated circuit using the same. BACKGROUND ART Conventionally, a shot barrier type, a pn junction type, an MIS type, or the like has been used as a field effect transistor. On the other hand, field effect transistors can be broadly classified into normally-on type and normally-off type in terms of operation.
As a switching element for a large-scale integrated circuit, a normally-off type is superior in terms of circuit simplicity and low power consumption. However, all conventional normally-off field effect transistors have practical problems. This will be explained in detail later. On the other hand, the problems of normally-on field effect transistors have not necessarily been solved, and as the operating temperature is lowered to increase speed and reduce power consumption, impurity atoms become trapped in the shotgun barrier type and p-n junction type. In the case of the freezing phenomenon, the shot-barrier type, and the MIS type, the expected behavior was denied due to the carrier trapping phenomenon to the interface state. Next, problems with the normally-off type field effect transistor according to the prior art described above will be explained in detail based on the drawings. Figures 1, 2, and 3 are schematic diagrams of normally-off type field effect transistors according to the prior art, including a shot barrier type and a p-type field effect transistor, respectively.
Shows n-junction type and MIS type. In the case of the shot barrier type field effect transistor shown in Figure 1,
The gate metal 6 is in direct contact with the semiconductor 1 to form a so-called shot barrier type. In this type of field effect transistor, even when the voltage between the source 4 and gate 8 is zero, the diffusion potential between the gate metal 6 and the semiconductor 1 (if the semiconductor 1 is GaAs, it is approximately 0.8 V regardless of the type of metal) Therefore, an electron depletion layer 7 is formed under the gate metal 6. By selecting the thickness of the electron depletion layer 7 and the thickness of the semiconductor 1 to be equal, the thickness of the semiconductor below the electron depletion layer 7 becomes zero, and no current flows between the source 4 and the drain 5. can. When the voltage between the source 4 and the gate 5 is positive, the thickness of the semiconductor 1 below the electron depletion layer 7 is no longer zero, and a current flows between the source 4 and the drain 5. In other words, normally-off type operation can be performed. In this type of field effect transistor, as described above, it is necessary that the thickness of the electron depletion layer 7 due to the diffusion potential is equal to the thickness of the semiconductor 1. When such conditions are required to be satisfied over a large area, as in the case of large-scale integrated circuits, it is extremely difficult to achieve this. That is, it is difficult to form the semiconductor 1 with uniform thickness and impurity concentration over a wide area with high precision. Second illustration p
In the -n junction type field effect transistor, a p-type semiconductor 9 is placed on the semiconductor 1 to form a p-n junction. The operating principle is the same as the Schottky barrier type shown in Figure 1, but the diffusion potential of the p-n junction is larger than that of the Schottky barrier (in the case of GaAs, it is approximately
1.4V), the electron depletion layer 7 becomes larger and the thickness and impurity concentration of the semiconductor 1 become easier to control, but the essential difficulty in manufacturing remains the same. In the MIS type field effect transistor shown in FIG. 3, the metal 6 faces the semiconductor 1 or the semiconductor 11 with an insulator 10 in between. The so-called MOS type uses an oxide as an insulator. Field effect transistors having this structure are further divided into two types as shown in FIGS. 3a and 3b. Figure 3a shows the shotgun.
Similar to the barrier type and pn junction type, when the voltage between the source 4 and the gate 8 is zero, the electron depletion layer 7 extends over the entire thickness of the semiconductor 1, but when a positive voltage is applied, This is a type in which the electron depletion layer 7 is shortened and a current flows between the source 4 and drain 5.
This type is the Schottki barrier type and p-
As with the n-junction type, there are technical difficulties in creating one with uniform characteristics. Another type of MIS field effect transistor shown in FIG. 3b is the semiconductor 11
is P type, and when a positive voltage is applied between the source 4 and the gate 8, an inversion layer is formed at the interface with the insulator 10 in the semiconductor 11, an electronic surface charge is induced, and the electrons are transferred between the source 4 and the drain 5. It is of the type that contributes to current. This type of MIS field effect transistor uses silicon as the semiconductor 11 and silicon dioxide as the insulator 10.
It is currently in widespread practical use as a MOS transistor. However, problems regarding low temperature operation and low noise operation remain unsolved. On the other hand, when a compound semiconductor is used as the semiconductor 11, there is a drawback that a good quality interface between the semiconductor 11 and the insulator 10 cannot be obtained, and therefore a good quality inversion layer and accumulation layer cannot be obtained. . However, regarding this, Japanese Patent Application Laid-Open No. 51-61625
As disclosed in the above publication, there was also a proposal to use a semiconductor having a wider band gap than the semiconductor 11 in place of the insulating film 10. Although this method can certainly provide better characteristics than when the insulating film 10 is used, the degree of improvement is still not sufficient, and in practice, the designability and controllability of the threshold value are also not good. In particular, the invention disclosed in this publication has not been able to break away from the idea of improving the MOS type, and since a metal electrode is used as a matter of course for the gate electrode, this metal gate electrode and the above-mentioned As shown in the figure, a wide
Generally, a shot junction is formed between the band gap semiconductor barrier layer, and the result is the basic form of the so-called HEMT structure using shot electrodes, or a structure similar to it.
Since the voltage applied to the gate electrode indirectly affects the channel through the depletion layer created by the shot barrier, changes in the thickness and impurity concentration of the semiconductor barrier layer affect the threshold extremely sensitively. There was a drawback that it ended up happening. In addition, a large number of interface states are generated at the interface between this wide band gap semiconductor barrier layer and the metal gate electrode, and there is no controllability regarding the density of the interface states. There is no guarantee of uniformity over time. These interface states also naturally affect the gate threshold voltage, so the reproducibility and uniformity of the gate threshold voltage itself is still poor. Furthermore, with the structure and conditions disclosed in this publication, it was difficult to construct complementary circuits on the same support substrate. Apart from this, an improvement was also made that corresponds to the case where the semiconductor barrier layer in the structure disclosed in the above publication was changed to a three-layer structure (Japanese Unexamined Patent Application Publication No. 1983-1982).
Publication No. 160473). That is, on the surface of the semiconductor layer constituting the channel formation region, from the bottom, a GaAs layer with impurities intentionally introduced, an Al _x Ga _1-x As layer, and a SiO ₂
In addition, after forming an amorphous insulating layer, a metal gate electrode is attached thereon. Even in this structure, the problem of interface states is thought to be alleviated to some extent compared to the case where the insulating film is in direct contact with the channel region forming layer, but the interface states exist at the channel interface itself. At the very least, the interface states within the structure including the insulating film between the gate and the channel do not completely disappear, and there is no way to prevent the deterioration of the characteristics such as the instability of the threshold characteristics due to this. Above all, the presence of an insulating film interposed between the metal gate electrode and the channel is an inevitable factor that causes a decrease in trans conductance. In reality, the structure disclosed in this publication is extremely difficult to put into practical use. The present invention eliminates the drawbacks of both the normally-on type and normally-off type field effect transistors according to the prior art described above, and the disadvantages of the normally-off type compound semiconductor field effect transistor, which can be expected to have particularly remarkable effects, and is technically simple. This method can structurally eliminate the existence of interface states and fluctuations in threshold voltage, and can adjust the threshold voltage fairly freely and accurately. The purpose is to obtain a high-performance field effect transistor whose polarity can be easily set. The present invention will be explained below. A two-layer gate is provided on a channel forming region made of a first semiconductor provided in contact with the source and drain regions. The first layer in contact with the channel forming region is composed of a second semiconductor having a lower impurity concentration and a larger band gap than the first semiconductor. When the first semiconductor is Si, GaP is an example of the second semiconductor.
can be mentioned. The second gate layer has a higher impurity concentration than the first semiconductor, and is made of a third semiconductor having a narrower band gap than the first gate layer in order to prevent carrier injection from the second gate layer. In the case of the present invention, the first gate layer serves as a gate barrier layer in place of a gate insulating film in a normal MOS structure, and the second gate layer constitutes an effective gate electrode in place of a normal metal gate electrode. Therefore, as will be described later, even if a metal electrode is formed on the third semiconductor gate electrode (gate second layer) because it is necessary to connect it to an external circuit, this is just an ohmic contact electrode. Therefore, the installation location can be arbitrary.
It is not necessary to be on the channel. Generally, the gate threshold voltage V _th of the field effect transistor of the present invention is V _th =φ _GS +φ _S +−qN ₁ +t ₁ t ₂ /ε ₂ +−qN ₂ t ^{2 2} _/ 2ε ₂ ……(1) Given. Here, φ _GS is the work function difference between the first semiconductor and the second gate layer, and φ _S is the surface potential of the first semiconductor measured from the flat band at the threshold voltage. ε ₂ is the dielectric constant of the second semiconductor, q is the elementary charge, the upper side of the double sign indicates the case where the impurity is a donor, and the lower side indicates the case where the impurity is the acceptor. N ₁ and N ₂ are the impurity concentrations of the first semiconductor and the second semiconductor, respectively. t ₂ is the thickness of the second semiconductor. t ₁ is the thickness of the depletion region of the first semiconductor, but if the first semiconductor is thin and can be depleted over the entire thickness, t ₁ becomes the thickness of the first semiconductor. In addition, in the case of a so-called accumulation type field effect transistor operation mode in which the channel carrier has the same conductivity type as the impurity contained in the channel forming region and is induced on the surface of the first semiconductor, the right side of equation (1) The third term becomes zero. In equation (1), φ _GS + φ _S is the impurity concentration N ₁ of the first semiconductor
and the impurity concentration N ₂ of the second semiconductor, the new value voltage V _th
In order to reduce the dependence on N ₁ and N ₂ , the values of both N ₁ and N ₂ in the third and fourth terms on the right side of equation (1) should be chosen small (the storage type field effect transistor In the operating mode, the third term on the right side of equation (1) is zero, so there is no dependence of V _th on N _1. Therefore, for the above purpose, only the value of N ₂ needs to be chosen small.) However, N ₁ may not be chosen to be small in order to prevent punch-through between the source and drain. Considering the above, it is meaningful to at least choose a small value for N ₂ . In the present invention (1)
By designing the value of N ₂ to be small enough that the fourth term on the right side of the equation does not affect the value of the gate threshold voltage, a configuration with excellent designability and reproducibility of the gate threshold voltage is achieved. In the present invention, the second semiconductor having such a value of N ₂ is referred to as "low impurity concentration." In short, the gate threshold voltage of the field effect transistor of the present invention is not determined by the impurity concentration _N2 of the second semiconductor, but is determined by the work function of the material constituting the second gate layer and the first impurity concentration N2 constituting the channel forming region. Difference in work function and impurity concentration of semiconductors
Can be designed with _N1 . In particular, the channel forming region made of the first semiconductor is formed very thinly on a high resistance reverse conductivity type or insulating semiconductor substrate or an insulating substrate such as sapphire, or
If N ₁ is small, the third term on the right side of equation (1) can be ignored, so the gate threshold voltage is determined by the difference φ _GS between the work function of the material of the second gate layer and the work function of the first semiconductor in the channel forming region. It's decided. Alternatively, even when the operation mode of the field effect transistor is the charge accumulation type, the gate threshold voltage is
It is determined only by the work function of the layer material and the work function φ _GS of the first semiconductor forming the channel. FIG. 4 shows a band diagram for a typical example of a combination of the first semiconductor and the second gate layer semiconductor or low resistance layer. Fourth
In each figure, the reference numeral 13, which has not been explained yet, is the first semiconductor layer constituting the channel forming region, _t1t is the total thickness of this first semiconductor layer, and 14 is in the gate structure and constitutes the gate barrier layer. A first gate layer made of a second semiconductor; 15 a second gate layer made of a third semiconductor which is in the gate structure and effectively constitutes a gate electrode; 16 a lower end of the conduction band; 17 a Fermi level; At the upper end of the valence band, Table 1 shows what type of field effect transistor operation type can be obtained by the combinations of a, b, c, and d in FIG.

[Table] Table 1 shows the results for semiconductors such as Si, which have a relatively large effective density of states in the conduction band of the first semiconductor, around 10 ¹⁹ /cm ³ , and GaAs, which has a density of states around 10 ¹⁷ cm ³ . Regarding semiconductors such as the above, there are other types of field effect transistor operation in addition to the examples shown in Table 1, as will be explained in detail in later examples. From the combination examples in Table 1, it is possible to realize a high-performance integrated circuit that combines transistors with different gate threshold voltages by fabricating transistors with different gate second layer materials or impurity types and concentrations on the same chip. Can be done.
For example, depending on the combination of b and d,
Normally-off type switching transistors can be used as switching transistors, and p-channel or n-channel transistors can also be used.
So-called E/D with a normally-on type as a load
It is possible to obtain integrated circuits such as gates and memories based on type inverters. This makes it possible to realize low-power, high-speed ICs. Looking more closely, even in the combination of a and c, by making the first semiconductor a low impurity concentration and realizing the work function or impurity concentration of the high impurity semiconductor that is the second gate layer to a specified value, it is possible to The threshold voltage can be designed to be slightly on the normally off side. In such cases, the power supply voltage can be significantly reduced without reducing the operating speed, and the LSI
In this case, it is possible to increase the degree of integration while maintaining high speed. Of course, from among the above combinations a, b, c, and d, combinations of the first semiconductor and the gate second layer that are p-channel normally off and n-channel normally off are selected, and a pair of them are placed on the same substrate. It is also possible to integrate complementary circuits using field effect transistors. In other words, the field effect transistor structure of the present invention makes it easy and reliable to construct such a complementary circuit on the same substrate, if necessary. On the other hand, a second semiconductor (first gate layer) is grown on top of the first semiconductor by heteroepitaxial technology (vapor phase growth, crystal growth in high vacuum, etc.) with good continuity of crystal structure. In this case, the influence of interface states and surface scattering is particularly small, and a field effect transistor having an ideal inversion or accumulation type induced channel on the surface of the first semiconductor (channel forming region) can be obtained. Next, as an example of the present invention, the structure of a field effect transistor in which the first semiconductor is a compound semiconductor and the channel is n-type will be described in detail with reference to FIG. The semiconductor 13, which is the first semiconductor constituting the channel forming region, is an n-type or p-type impurity-concentrated compound semiconductor, or a high-purity compound semiconductor such as GaAs with almost no impurity addition. A semiconductor 13 is on an insulating substrate 2. A semiconductor 14 has a larger band gap than the semiconductor 13 and forms a high-quality heterojunction with the semiconductor 13.
3 is a different type of semiconductor with a low impurity concentration.
The thickness of the semiconductor 14 can be made sufficiently thin as long as a tunnel current larger than the drain-source current does not flow between the semiconductor 13 and the semiconductor 15. When the semiconductor 13 is GaAs, an example of the semiconductor 14 is Ga _x Al _1-x As. The semiconductor 15 is an n ⁺ type semiconductor doped with impurities at a higher concentration than the semiconductor 13, and has a smaller band gap than the semiconductor 14. When the semiconductor 13 is GaAs, an example of the semiconductor 15 is n ⁺ GaAs. An ohmic electrode 3'' is provided on at least a portion of the semiconductor 15.The semiconductors 14 and 15 together form a gate.Each source and drain region is provided with an ohmic electrode 3, 3' and an ⁿ⁴ type. Compound semiconductor 1 of the same type as semiconductor 13
2,12'. Semiconductor 13 is GaAs,
When the semiconductor 14 is Ga _x Al _1-x As, the semiconductor 15 may of course be made of InP having a high n-type impurity concentration. In the case of InP, it is possible to obtain a good layer with a nearly continuous crystal structure with the semiconductor 14, as in the case of GaAs, and it is also possible to increase the impurity concentration to make it easier to control than when using GaAs. can. Next, the principle of operation of the field effect transistor of this embodiment will be explained in detail with reference to FIG. FIG. 6 shows a case where n-type GaAs is used as the semiconductor 13, Ga _0.7 Al _0.3 As with a small impurity concentration is used as the semiconductor 14, and n ⁺ type GaAs is used as the semiconductor 15. FIG. 6a is a band diagram near the gate in a direction perpendicular to the source 4/drain 5 direction when no voltage is applied between the source 4 and gate 8. Semiconductor 14 is semiconductor 13,1
The band gap is about 0.36 eV larger than that of 5, of which about 0.3 eV is the difference at the bottom of the conduction band, and the rest is
0.06eV is the difference at the top of the valence band. Therefore,
In a steep heterojunction, line 16 represents the lower end of the conduction band.
increases stepwise by about 0.3 eV at the interface with the semiconductor 14. In order for electrons in semiconductor 13 or semiconductor 15 to cross this step and enter into other regions, they must have a kinetic energy of at least 0.3 eV in that direction. The number of such electrons is extremely small as long as the transistor is operated at low voltage. Therefore, the gate current can be ignored. Further, since the impurity concentration in the semiconductor 14 is low, the amount of space charge generated by donors or acceptors after the carriers in the semiconductor 14 spill over to the semiconductors 13 and 15 with low energy is extremely small. Therefore, the semiconductor 14 is located between the semiconductor 13 and the semiconductor 15 and functions to separate carriers.
Among compound semiconductors, when the effective density of states in the conduction band is about 10 ¹⁷ cm ^-3 , such as GaAs, the semiconductor 1
In the vicinity of the interface with the semiconductor 14 in 3, the 6th
As shown in Figure a, the conduction band lower end 16 drops to near the Fermi level 17, and weak electron charges are induced, but the amount of surface charges is small. When a positive voltage is applied between the source 4 and gate 8 of the transistor of this structure, the band diagram changes as shown in FIG. 6b.
That is, the conduction band lower end 16 is at the Fermi level 17 in the semiconductor 13 near the interface with the semiconductor 14.
and a strong electron charge is induced there. Its surface charge increases with the positive voltage applied to the gate 8, which carries the current between the source 4 and drain 8. As is clear from the band diagram, the field effect transistor of this example has the following characteristics:
The threshold voltage has a value near zero, and it does not change much depending on the impurity concentration, thickness, etc. of the semiconductors 13, 14, 15. Therefore, by using the field effect transistor of this embodiment, a normally-off type field effect transistor with uniform characteristics can be easily obtained over a large area. Also, Ga _x
It is known that the interface between Al _1-x As and GaAs is an ideal interface with few traps, so all the electrons induced near the interface serve to carry the current between source 4 and drain 5. However, noise caused by interface states and abnormal behavior during low-temperature operation are extremely low. The mobility of electrons in GaAs, which has a low impurity concentration, is approximately 5 to 6 times that of electrons in silicon, which is approximately 8500 cm ² V ^-1 S ^-1 . Reduce switching time. The mobility of electrons in GaAs increases further at lower temperatures, reaching nearly 1×10 ⁶ cm ² V ^-1 S ^-1 at 77K. Therefore, if a transistor with this structure is operated at a low temperature, its performance will be further improved dramatically. In the above example, the semiconductor 13 was of the n-type, but it is clear that the same operation can be obtained even if the semiconductor 13 is of the p-type. FIG. 7 shows the semiconductor 1
3 shows a band diagram in the case of p-type. That is, if the impurity semiconductor 14 is made thin, the conduction band lower end 16 will not leave the vicinity of the Fermi level 17 in the semiconductor 13 near the interface with the semiconductor 14. When a positive voltage is applied between the source 4 and gate 8 of a field effect transistor with this structure, the conduction band lower end 16 drops below the Fermi level 17 in the semiconductor 13 near the interface with the semiconductor 14, and electron charges are induced there. What happens is the same as in FIG. In FIG. 6, GaAs is used as the semiconductor 13 and Ga _0.7 Al _0.3 As is used as the semiconductor 14, but it is clear that the combination is not necessarily limited to these compound semiconductors. For example, the semiconductor 13 is GaAs, and the semiconductor 14 is Ga _x Al _1-x As.
combination, InSb−cdTe, Ga _x In _1-x As−In _x
Al _1-x As, GaSb-ZnTe or Ga _x Al _1-x Sb, InAs
There are combinations such as -GaSb or ZnTe, In _1-x Ga _x AS _y P _1-y -InP, etc. Further, in FIG. 5, the electrode 3'' which is in ohmic contact with the gate second layer (third semiconductor) 15, which is the effective gate electrode, is
In the figure, the metal electrode is attached on the entire surface of the second gate layer 15, but as already mentioned, in the case of the present invention, this metal electrode is used only for connection with an external circuit, so It is sufficient to apply it only to a part of the layer 15. This will simplify the gate structure, and in other words, the ohmic electrode 3'' can be attached to any suitable location in terms of circuit construction.
The degree of freedom in design is also greatly increased. As described above, the field effect transistor of the present invention has the following unique effects. That is, by using a semiconductor with a low impurity concentration as the second semiconductor (the first layer of the two layers constituting the gate) that is in contact with the first semiconductor constituting the channel formation region, the gate of the field effect transistor is The threshold voltage can be made independent of the impurity concentration of the second semiconductor. Depending on the type of field effect transistor, it is possible to design the gate threshold voltage to be given only by the difference in work function between the materials of the first semiconductor and the second gate layer, so that an electric field with homogeneous characteristics can be achieved. It becomes easier to manufacture effect transistors over a large area,
Large-scale integrated circuits can be easily realized.
Furthermore, it is possible to avoid deterioration in the characteristics of the field effect transistor due to the influence of interface states between the first semiconductor and the second semiconductor, traps, etc., and the influence of carrier freezing at low temperatures. This effect is particularly noticeable when a high-quality MIS type structure is not obtained, such as when the first semiconductor is a compound semiconductor. That is, by applying the field effect transistor of the present invention to a compound semiconductor, it is possible to obtain an extremely high speed, low power consumption, homogeneous field effect transistor that takes advantage of the high electron mobility of the compound semiconductor. As explained above, the transistor according to the present invention makes it possible to easily obtain large-scale integrated circuits with low power consumption, and makes an extremely large contribution to the technical field of high-speed electronic computers and electronic devices for high-speed communication. be.

[Brief explanation of drawings]

1, 2, and 3 are schematic diagrams of the configuration of field effect transistors according to the prior art, and FIG.
The band diagram, FIG. 5 is a schematic structural diagram of an embodiment of the field effect transistor of the present invention, and FIGS. 6 and 7 are diagrams of the operating principle of the embodiment. In the figure, 1 is an n-type semiconductor, 2 is an insulating substrate, 3,
3', 3'' are ohmic electrodes, 4 is a source, 5 is a drain, 7 is an electron depletion layer, 8 is a gate, 9 is a p-type semiconductor, 10 is an insulator, 11 is a p-type semiconductor, 12
is an n ⁺ type semiconductor, 13 is a semiconductor, 14 is a semiconductor with low impurity concentration, 15 is a semiconductor with high impurity concentration, 16 is the lower end of the conduction band, 17 is the Fermi level, 18 is the upper end of the valence band, and 19 is the low resistance layer. It is.

Claims (1)

[Claims] 1 Consisting of a source/drain region, a channel forming region made of a first semiconductor provided in contact with the source/drain region, and a two-layer stacked structure provided on the channel region a gate structure; in the gate structure, a first layer in contact with the channel forming region has a band width smaller than that of the first semiconductor;
A second semiconductor with a wide gap and a low impurity concentration; On the other hand, a second layer laminated on the first layer has a band gap narrower than that of the first layer and a second semiconductor with a lower impurity concentration. a third semiconductor having a higher impurity concentration; the second layer in the gate structure serves as an effective gate electrode, and the first layer provides carrier separation between the gate electrode and the channel; A field effect transistor characterized by: configuring a barrier layer for; 2. The field effect according to claim 1, characterized in that the third semiconductor constituting the second layer in the gate structure is the same type of semiconductor as the first semiconductor constituting the channel forming region. transistor. 3 The first semiconductor is GaAs, the first semiconductor in the gate structure
2. The field effect transistor according to claim 1, wherein the second semiconductor constituting the layer is Ga _x Al _1-x As or ZnSe. 4. The field effect transistor according to claim 1, wherein the first semiconductor is Si, and the second semiconductor forming the first layer in the gate structure is GaP. 5 The first semiconductor is InSb, the first semiconductor in the gate structure
2. The field effect transistor according to claim 1, wherein the second semiconductor constituting the layer is GdTe. 6. The first semiconductor is Ga _x In _1-x As, and the second semiconductor forming the first layer in the gate structure is In _x Al _1-x As. The field effect transistor described in Section 1. 7 The first semiconductor is GaSb, the first semiconductor in the gate structure
2. The field effect transistor according to claim 1, wherein the second semiconductor constituting the layer is Ga _x Al _1-x Sb or ZnTe. 8 The first semiconductor is InAs, the first semiconductor in the gate structure
The second semiconductor forming the layer is GaSb or ZnTe
The field effect transistor according to claim 1, characterized in that: 9. Claim 1, characterized in that the first semiconductor is In _1-x Ga _x As _y P _1-y and the second semiconductor forming the first layer in the gate structure is InP. Field effect transistor as described.