JPH025337B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit that prevents the outputs of a plurality of delayed flip-flops included in the same system from all matching when the power is turned on.

Generally, when the power is turned on, it is completely uncertain whether the output of each of the multiple flip-flops included in the system will be "H" or "L", and all outputs will be "H" or "L". It is also possible to do so.

Similarly, in the channel selection circuit of the receiver shown in FIG. 1, when the power is turned on, the outputs X ₁ to X 5 of the delayed type flip-flops 1 to ₅ may all match, and it is inconvenient if they all become "L". occurs.

That is, considering FIG. 1 excluding the control circuit 6 as an embodiment of the present invention indicated by a broken line, the output
X ₁ to _{X 5} become "L" when channel buttons 7 to 11 as switches are pressed, and this "L" signal is applied to the preset memory as an address designation signal for the preset memory,
The corresponding channel is selected, and if all delayed type flip-flops 1 to 5 are set to "L" when the power is turned on, all channels will be selected, and the channel to be selected will be is not determined.

In addition, in FIG. 1, for example, when the channel button 9 is pressed, the terminal CH ₃ becomes "L" and the output X ₃ also becomes "L", and this "L" X ₃ output outputs the NOR gate 19. via N channel
Since the MOSFET 24 is turned on, the terminal CH ₃ is held at "L" even after the channel button 9 is released.

The same applies to terminals CH ₁ to CH ₅ .

Note that the DI signal is a control signal that becomes "L" when any one of the outputs X ₁ to _{X 5} becomes "L", that is, when any channel is selected, and the CLK
The (control) signal is sent to the unselected channel, i.e.
This is the clock pulse that occurs when the channel button of an empty channel is pressed.

Therefore, when the power is turned on, if the outputs X ₁ to X 5 of the delayed flip-flops 1 to ₅ are all "L", not only all channels are selected as described above, but also the outputs 7 to 11 are selected. The state cannot be canceled even if you press any channel button.

In view of this, the present invention has been made to forcibly transfer the output of at least one flip-flop to the other flip-flops in order to prevent all the outputs of a plurality of delayed-type flip-flops included in the system from becoming the same. The purpose of this is to set the output to a different value.

In FIG. 1, a control circuit 6 shown by a broken line as an embodiment of the present invention includes a NOR gate 27 inputting outputs X ₄ and X 5 of delayed type flip-flops 4 and ₅ , and an output of this NOR gate 27. and CLK
The output _G0 of the OR gate 28 is inputted to the slave side clock terminal _CL2 of the delayed type flip-flop 5.

That is, flip-flops 1 to 5 are general delayed type flip-flops as shown in FIG _.
The slave side 30 also has a clock terminal _CL2 . The same signal CLK is input to the clock terminals CL ₁ and CL ₂ of flip-flops 1 to 4, the CLK signal is input to the clock terminal CL ₁ of flip-flop 5, and the OR gate 2 is input to the clock terminal CL ₂ of flip-flop 5.
8 output signal G ₀ is input. Note that an input circuit is constituted by the respective OR gates 12 to 16, NOR gates 17 to 21, and P channel MOSFETs 22 to 26.

Therefore, the operation of this embodiment will be explained with reference to the timing chart shown in FIG.

First, by turning on the power, X ₄ and X ₅
If it becomes "L" as shown in Figure 3 A and B, the DI signal also becomes "L", so the NOR gate 20
The outputs of MOSFETs 25 and 21 become "H", so N-channel MOSFETs 25 and 26 turn on and the terminals
CH ₄ and CH ₅ become "L" (Figure 3 D and F).
Also, since the outputs of OR gates 15 and 16 become "H", the input terminals D ₄ and D 5 of flip-flops 4 and ₅
remains at "H" (Figure 3, ho and g).

On the other hand, when the output signals X ₄ and X ₅ become "L",
The output of the NOR gate 27 becomes "H", and therefore the output _G0 of the OR gate 28 also becomes "H", and the _G0 signal of "H" is applied to the slave side clock terminal _CL2 . Here, an "H" signal is applied to input terminal _D5 , and the master side clock terminal
Since the "L" CLK signal is applied to CL ₁ , the "H" signal is output to the master side output, and in this state, the "H" signal is applied to the slave side clock terminal CL ₂ . Output because G ₀ signal is applied
X ₅ (Q ₅ ) changes from "L" to "H".

That is, channel 5 changes from a selected state to an unselected state.

Next, the output X ₅ (Q ₅ ) becomes “H”, so NOR
The output of gate 27 becomes "L", and at this time CLK
Since the signal is “L”, the output of OR gate 28 G ₀
is also "L". Furthermore, since the output X ₅ (Q ₅ ) becomes "H" while the DI signal remains "L", the output of the NOR gate 21 becomes "L", and therefore the terminal CH ₅
changes from "L" to "H", and the channel button 11 becomes pressable (FIG. 3D). still,
As shown in FIG. 3E, the input terminal D ₅ temporarily changes from "H" to "L" because the output of the NOR gate 21 changes from "H" to "L" when the terminal CH ₅ is "L". ”
However, since the terminal CH ₅ subsequently changes from "L" to "H", the input terminal D ₅ returns to "H".

As mentioned above, even if the outputs _X1 to X5 of flip-flops 1 to ₅ are all "L" when the power is turned on,
Only the output _X5 of channel 5 becomes "H" by the control circuit 6, and the outputs X1 of flip-flops 1 to ₅ become "H".
~X Prevent all ₅ from matching.

Also, by pressing the channel button 11, the abnormal state in which all channels 1 to 4 are selected is canceled, and only one channel from channels 1 to 5 is selected. It can be returned to normal state. That is, when the channel button 11 is pressed, only the signal applied to the input terminal _D5 becomes "L".
Therefore, the "H" signal remains applied to the input terminals D ₁ to _{D 4} , and the CLK signal is generated by pressing the channel button 11 in this state, so the outputs X ₁ to _{X 4} are all ""H", only the output _X5 becomes "L", and only channel 5 is selected, returning to the normal state. Note that the terminals CH ₁ to _{CH 4} are all at "H".

By the way, the output of the NOR gate 27 is the output X ₄
and _X5 are both "L", that is, when channel 4 and channel 5 are both selected, it becomes "H", and when the channel selection circuit is operating normally, it becomes "L". Become. That is, under normal operating conditions, the same CLK signal as the signal applied to the master side clock terminal CL ₁ is always applied to the slave side clock terminal CL ₂ of the flip-flop 5 via the OR circuit 28. .

As described above, the output setting circuit of the delayed type flip-flop of the present invention is a simple circuit that ensures that all the outputs of the multiple delayed type flip-flops included in the system match when the power is turned on. can be prevented.

Furthermore, if the present invention is applied to a channel selection circuit of a receiver, it is possible to prevent all channels from being selected when the power is turned on, and to select a plurality of channels by pressing an unselected channel button. It becomes possible to cancel the abnormal state where is selected and return to the normal state.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a specific circuit diagram of a delayed type flip-flop, and FIGS. Explanation of main figure numbers, 1-5...Delayed type flip-flop, 6...Control circuit, 7-11...
...Channel button, 12-16...OR gate, 17-21...NOR gate, 22-26...
...N-channel MOSFET, 27...NOR gate, 28...OR gate, 29...master side of the delayed type flip-flop, 30... slave side of the delayed type flip-flop.

Claims (1)

[Claims] 1. A plurality of switches, a plurality of delayed type flip-flops provided corresponding to the plurality of switches, an operation detection signal obtained when the switches are operated, and an output of the delayed type flip-flops. a first AND circuit to which is applied, a signal indicating the operating state of the switch is applied to one input, and an output of the first AND circuit is applied to the other input, and the output is a first OR circuit applied to the input of the delayed type flip-flop, and a gate connected to the first
the plurality of switches and the plurality of delayed type switches, including a switch circuit that is controlled based on the output of the AND circuit, and puts one input of the first OR circuit in the same state as when the switch is operated; In an output setting circuit for a delayed type flip-flop, the output setting circuit includes a plurality of input circuits provided corresponding to the flip-flops, and at least two outputs of the plurality of delayed type flip-flops are applied. a second AND circuit to which the control signal applied to the master side clock terminal of the plurality of delayed type flip-flops and an output signal of the second AND circuit are applied; 2 OR circuit, and applies the output signal of the second OR circuit to the slave side clock terminal of at least one flip-flop of the plurality of delayed type flip-flops, and A signal is commonly applied to the clock terminals of the master side and slave side of the remaining flip-flops, thereby preventing the outputs of all of the plurality of delayed-type flip-flops from becoming the same when the power is turned on. output setting circuit for a delayed type flip-flop.