JPH0253982B2 - - Google Patents

Description

Claim 1: comprising one input port and two output ports, said input port having N input data lines, and each of said output ports having N output data lines, said input port further comprising: means for selecting only one of said two output ports at a time based on a predetermined character provided to said output port; and means for sending a character from said input port to said selected output port; Each of the characters is N on the input port.
represented by active logic signals on M data lines of M data lines, where M is at least 2
and the N is larger than the M and 3
, the sending means detects when M active logic signals are present on the N data lines of the input port and sends those M active logic signals to the output port. a selector including means for initiating an action; 2. The means for selecting selects one of two predetermined characters on the input port indicating which output port should be selected when no output port has been selected yet. 2. The selector of claim 1, wherein the selector selects an output port in response to the presence of one of the output ports. 3. The selector according to claim 2, further comprising means for prohibiting said character that selects said output port from being sent to said selected output port. 4. The sending means asynchronously receives active logic signals of the characters from the input ports, and transmits all of the logic signals of the respective received characters to the selected output port in parallel and in synchronization with each other. 2. A selector as claimed in claim 1, including width queuing means. 5 said input port further includes one input control line, said means for sending a control signal on said one input control line indicating when a character on said N input data lines can be accepted and changed; A selector according to claim 1, comprising means for generating. 6. Each of the output ports further includes one output control line, and the means for sending one out of the N output data lines of the selected output port.
Claim 1, further comprising means for removing one character and generating another character in response to an externally generated signal on the output control line of the selected output port. selector. 7. The method of claim 1 further comprising means for detecting and responsively deselecting a predetermined character on the N input data lines of the input port from the selected input port. Selector. BACKGROUND OF THE INVENTION This invention relates to arbiters and selectors and their circuitry. Generally, an arbiter is a logic circuit having two input ports and one output port, and in its operation, a message is transmitted from either input port to an output port. One prior art arbiter is also the inventor of the present application, e.g.
No. 4,251,879, issued February 17, 1981 to Becky J. Clark. Generally, a selector is a logic circuit having one input port and two output ports, and in its operation, a message is transmitted from the one input port to a selected one of the two output ports. be done. One prior art selector is, for example, 1980 12 for Becky J.Clark similar to above.
No. 4,237,447, issued May 2nd. A limitation of the arbiters and selectors mentioned above is that they only operate on bit-serial messages. That is, messages are sent from its input port to its output port one bit at a time. Therefore, the maximum baud rate at which such arbiters and selectors operate is relatively low. In order to increase this baud rate, it is also conceivable to connect a number of the above-mentioned arbiters and selectors in parallel. However, the problem with such parallel connections is that the bits do not pass through the parallel paths in sync with each other. The reason is,
If a request arrives at both input ports at the same time,
This is because the arbiter randomly selects one or the other of its input paths. Thus, multiple bits sent from a source through the parallel connection of arbiters and selectors described above will reach their destination in an unpredictable and highly scrambled manner. It is therefore a primary object of this invention to provide an improved selector. Another object of the invention is to provide a selector that conveys multiple bits in parallel from its input port to its output port. SUMMARY OF THE INVENTION These and other objects are achieved by a selector having one input port, two output ports, means for selecting, and means for sending.
The input ports have N input data lines and each of the output ports has N output data lines. The means for selecting selects only one of the two output ports at a time based on a predetermined character provided to the input port. The means of sending
Send a character from the input port to the selected output port. Each of the characters is represented by an active logic signal on M of N data lines on the input port, where M is at least two and N is greater than M and greater than three. The means for sending includes means for detecting when M active logic signals are present on the N data lines of the input port and initiating sending the M active logic signals to the output port.

[Brief explanation of drawings]

The various features and advantages of the invention will be better understood by reference to the following detailed description and accompanying drawings. FIG. 1 shows a selector network constructed in accordance with the present invention. FIG. 2 shows a block diagram of one of the selectors in the network of FIG. 3-7 are detailed logic diagrams of one preferred embodiment of the selector of FIG. 2.

[Detailed description of the invention]

A preferred embodiment of the invention will now be described in detail with reference to FIGS. 1-7. FIG. 1 shows three selectors 1 constructed in accordance with the present invention.
An example of how 0A, 10B, and 10C can be interconnected as a system is shown. Of course, any different number of selectors and arbiters may be used and interconnected in an input port-output port format to form other systems. Selectors 10A, 10B, and 10C are identical to each other, and the letters A, B, and C are added solely to identify the selector's position in the system. Each selector includes one input port and two output ports. In FIG. 1, reference numeral 11 indicates the input port, and reference numerals 12 and 13 indicate the respective output ports. In the system of FIG. 1, the input ports of selectors 10B and 10C are connected to each output port of selector 10A. In operation, a message is transferred from the input port of selector 10A to selector 10
B and 10C to any output port. Each message has the format A _S ... A _S M ... MC _EM A _A ... A _A C _EA when it is introduced into the selector system and is sent to the output ports of selectors 10B and 10C. A _S …A _S
It has the format M...MC _EM A _A ...A _A C _EA . In the message format described above, each symbol A _S , M, C _EM , C _EA and A _A each represents one character. Also, the character is
It is represented by M codes out of N codes. That is, each of input port 11 and output ports 12 and 13 in the selector includes N data lines, and the characters of these data lines are determined by the signals on M of the N lines that are active. It is expressed as Also, in the message format mentioned above,
The symbol M represents a character in the body of the message, while the symbols A _S , C _EM , C _EA and A _A represent control characters. The control characters A _S . . . A _S are used by the selector network to select a path through the network. In particular, the first A _S character selects one of the output ports of the selector 10A,
The second A _S character selects one output port of the next selector. The A _S characters are two particular characters of the set of possible characters for M. The control character _CEM is used by the arbiter circuitry (not shown) to indicate the end of the message body. One control character A _A is generated by each arbiter to indicate which of its input ports a message will pass through. this
The A _A control character is two characters similar to the A _S control character. Control character C _EA
is used by the selector to indicate the end of the A _A character string and message. Turning now to FIG. 2, a block diagram of one of the selectors is shown. In this block diagram, signals D ₁ ...D _o represent the data signals on the input data lines of input port 11, and signals D ₀₁ ...D _0o
represents the signal on each output data line of output port 12, and the signal D ₁₁ . . . D _1o represents the data signal on each output data line of output port 13. Input port 11 also includes one input control line, and each output port includes one output control line. Signal A is generated by a selector on the input control line for input port 11, signal A ₀ is received by a selector on the output control line for output port 12, and signal A ₁ is received by a selector on the output control line for output port 1.
3 is received by a selector on the output control line. Generally, these signals are utilized to regulate the transfer of characters from the output port's data line to the input port's data line. A detailed block diagram of a preferred embodiment of the selector of FIG. 2 is shown in FIGS. 3-7;
The operation of these logic circuits will now be explained. In general, Figures 3 and 5 show the portion of the selector that selects one of the output ports;
Figures 6 and 7 show the portion of the selector that moves a character from an input port to a selected output port. First, the detailed configuration and operation of the logic circuit shown in FIG. 3 will be considered. This circuit consists of logic gate 20
29 and logic gates 30 to 38, all interconnected as shown. Generally, logic gates 20-28 operate to select output port 12 and logic gates 30-38 operate to select output port 13.
works to select. Prior to the selection operation, at power-up, the circuit of FIG. 3 is placed into an initial state in response to RESET' being low. In this initial state, the signal (S ₀ +S ₁ )' is high, the output of NAND gate 22 is low, and the output of NAND gate 27 is high. Signal RESET' then goes high, thereby causing NAND gates 20 and 3
0 to detect the presence of one of the two control characters A _S on the input port 11. That is, in FIG. 3, signals D _S . . . _DT represent M of _the input data signals D ₁ . These particular input data signals are then assigned to the characters that select the output port 12.
Form A _S. Similarly, the signals D _V ...D _U are connected to the M other input data signals D ₁ ...D _N on the input port 11.
It is. These M signals then form a character A _S that selects the output port 13. For example, here all input data signals D _S
...Assume that D _T transitions to its active state, i.e., high. In this case, the output of NAND gate 20 goes low, forcing the output of NAND gate 22 to go high. NAND gate 2
The output of 2 is the NAND gate 21-1 or 21-
is fed back to the input of M, and thus the high output of NAND gate 22 is latched. The high from NAND gate 22 forces the output of NAND gate 23 low, which in turn
Forces the output of NAND gate 25 high.
The outputs of NAND gates 24 and 26 are already high due to the signal (S ₀ +S ₁ )' being high, so the output of NAND gate 27 is forced low. This low from gate 27 is next
Latched by NAND gates 25 and 26, forcing the output of NAND gate 28 high. In response to the output of NAND gate 27 being low, selector 10 generates a high on the input control line to input port 11. That is, signal A on input port 11 is forced high. To explain how this occurs, reference is now made to the logic circuit of FIG. The logic circuit in FIG. 4 consists of a NAND gate 40-1
40-N, 41-1 to 41-X, and 42. For this representation, N is the number of input data lines and X is the number of M-item combinations taking N at a time. These NAND gates are interconnected as shown. NAND gates 40-1 to 40-N and 41-1 to 41-X have a signal D _J1 at their inputs.
Or receive D _JN . These signals are generated by the input buffers in the queue of FIG. However, this queue is prevented from receiving the first control character A _S applied to the input port 11, as will be briefly explained.
Therefore, signals D _J1 to D _JN are all low, and therefore signal ASET ₀ ' is at NAND gate 42.
to force input control signal A high. To understand how the control character A _S is kept out of the input buffer, consider now the control circuit of FIG. This control circuit includes logic gates 50-53, 55-58,
and 60-69, the logic gates of which are interconnected as shown.
This circuit is forced to its initial state by a low signal RESET'. In its initial state,
The outputs of NAND gates 53 and 58 are both low, and the outputs of NAND gates 67 and 69 are both high. As mentioned above, when the control character A _S is detected by the circuit of FIG. 3, the signal G ₀ goes low and, after a three gate delay, the signal ASET ₀ goes high. And since signal G ₀ goes low before signal ASET ₀ goes high, the output of NAND gate 50 remains high. Therefore,
The signal S ₀ from NAND gate 53 remains low;
Therefore, the signal S ₀ +S ₁ from the NAND gate 62
remains low. Next, if we examine Figure 6, we can see that the input buffer remains clear because the signals S ₀ + S ₁ must be high in order for the signals D ₁ to D _N on the input ports to be queued. . Then, in response to input control signal A being high, all data input signals D ₁ to 1 on the input ports
D _N goes low. Therefore, in the circuit of FIG.
The outputs of 1-1 through 21-M are forced high. Therefore, the output of NAND gate 22 goes low and the output of NAND gate 23 goes high. This high from gate 23 is then sent to the input of gate 50 in FIG. 5 as signal _G0 . Therefore, the output of NAND gate 50 goes low,
Also, the output of the NAND gate 53 shifts to high.
This high from NAND gate 53 is sent to the queue of FIG. 6 as signal S ₀ to output port 1.
Activate 2. Furthermore, this high signal S ₀ is
The output of NAND gate 62 is forced high, which is then sent to the queue of FIG. 6 to enable the input buffer. The high signal S ₀ +S ₁ from NAND gate 62 also causes input port control signal A to go low.
The reason this happens is that the high from NAND gate 62 forces the output of NAND gate 63 low, and this low is then sent as a signal (S ₀ +S ₁ )' to NAND gate 29 in FIG. Therefore
The output of NAND gate 29 goes high, which forces the output of NAND gate 24 low, which in turn forces the output of NAND gate 27 high. gate 27
_The high from
to the input of NAND gate 42, thereby causing input port control signal A to go low. The high from NAND gate 27 in FIG.
Note that the output of NAND gate 28 goes low. This low is a signal
It is sent as ASET ₀ to NAND gates 50 and 51 in FIG. However, the signal from the circuit in Figure 5
S ₀ remains high because the circuit is latched by NAND gate 52. Therefore, output port 12 of FIG. 6 remains selected and data continues to be enabled and moved to the input buffer of the queue. Each character received at input port 11 subsequent to the first character is sent via the queue of FIG. 6 to a selected output port as follows. First, the N input data signals in FIG.
M of D ₁ through D _N go high, thereby indicating the presence of a new character on the input data line. As these input data signals go high, they are latched in each latch of the input buffer. In FIG. 6, reference numerals 70-1 to 73-1 indicate input data signals D ₁
70-N to 73-N are data input signals.
Indicates an input buffer error that stores D _N. After M input data signals have been stored in the input data buffer, the circuit of FIG. 4 operates to force input control signal A high. This high indicates that the character has been stored in the input buffer and can be removed from input port 11. This high signal A is connected to a gate 41- which detects the presence of a character in the input buffer.
1 to 41-X. That is, each of gates 41-1 through 41-X has M inputs from the input buffer, and these M inputs are arranged to detect all possible characters. Gate 41-1
detects a certain character, and gate 41-2 detects another character. If any of these gates detects a character in the input buffer, the output of that gate will go low, thereby forcing the output of NAND gate 42 high;
That high then goes to NAND gate 40-1 or 4.
Latched by the feedback provided by 0-N. The data in the input buffer is then transferred to the selected output port as follows. First, data is moved from the input buffer to the output buffer. The output buffer consists of N latches, the first of which is designated by the reference numeral 8 in FIG.
0-1 to 83-1, the last of which is designated by the reference numerals 80-N to 83.
-N. This output buffer is loaded under the direction of a control circuit consisting of NAND gates 84-87 whenever output port control signals A ₀ and A ₁ are both low and signal RESET' is high. From the output buffer, data is routed to the selected output port in response to signals S ₀ and S ₁ .
The signal S ₀ is a pair of NAND gates 90-1 to 90
−N is enabled, and the signal S ₁ is the pair 9 of the NAND gates.
1-1 to 91-N are activated. The signal from the output buffer is also sent to the control circuit of FIG.
The control circuit generally operates to provide feedback from the output buffer to the input buffer. This feedback is in the form of a signal A _K ′,
That signal causes the input buffer to be cleared when it is low, and causes the input buffer to be set when it is high.
Referring to FIG. 7, it can be seen that this circuit consists of NAND gates 100-1 to 100-N, 101-1 to 101-X, 102 and 103. In this display, X is 1
It represents the number of combinations of M items that take N items at a time. Similarly, NAND gates 101-1 to 1
01-X each have M inputs from the output buffer, and the inputs are arranged to detect any character in the output buffer. Therefore, if a character is present in the output buffer, NAND gates 101-1 to 10
The output of one of 1-X goes low and therefore the output of NAND gate 102 goes high. This high is latched by the feedback provided by NAND gates 100-1 through 100-N. Also, this high is a signal
A _K ′ is forced low, which in turn allows the input buffer to be cleared. Note, however, that the input buffers are not cleared until the signals D ₁ -D _N on the input ports go low in response to input port control signal A being high. When the input buffer is cleared, signals D _J1 through D _JN in the input buffer go low. These signals are monitored by the control circuit of FIG. 4, and when they all go low, the NAND gates 40-
1 to 40-N and 41-1 to 41-X
All outputs of are high. This in turn forces input port control signal A low, which indicates that a new character may be present for the input port. However, new characters on the input port will not be accepted by the input buffer of FIG. 6 until the data in the output buffer has been taken from the selected output port. The fact that that happened means that the output port control signal
Represented by A ₀ going high.
When that happens, NAND gate 8 in Figure 6
The output of 7 goes low, which clears the output buffer the next time the input buffer is cleared. Next, all NAND gates 100-1 to 10 in the feedback circuit of FIG.
The outputs of 0-N and 101-1 through 101-X go high, which in turn forces signal A _K ' high. And when signal A _K ′ is high,
A new character can be received by the input buffer, after which all the signal sequences described above are repeated. Here, the control character C _EA is connected to input port 11.
Consider the operation of the selector when the signal is received. The control character indicates to the selector that the message on its input port is complete and that the previously selected output port should be deselected. In detail, the deselection occurs as follows. First, M signals on the input buffer in FIG.
_D1 through _DN go high and their signals are latched into the input buffers. From there they are sent to the control circuit in Figure 4 where they
NAND gate 41-J detects the presence of character _CEA . This detection is performed by NAND gate 41-J
is indicated by the output of going low. This low is transferred to the control circuit of FIG. 5 as signal EA _A '. Therefore, the signal EA _A ′ which is low
forces the output of NAND gate 65 high,
That high then forces the output of NAND gate 67 low. This row is then NAND gate 66
and 65, and it is also sent back to the input of NAND gate 42 in FIG. 4 as signal EA _B '. So the signal that is low
EA _B ′ forces input port control signal A high;
It is thereby shown that the control character _CEA can be removed from the input port. The low signal EA _B ' is also connected to NAND in FIG.
Forces the output of gate 68 high. However, this high is blocked by the signal EA _A ', which is low, so this high
The output of NAND gate 69 never goes low. Therefore, the output of gate 69 remains high and no further signal transmission occurs in the circuit of FIG. In particular, signal S ₀ remains high, and thereby output port 12 remains selected. The control character _CEA in the input buffer of FIG. 6 is then transferred to the output buffer. From there, it is forwarded to the selected output port 12. Next, the gate 101 in the circuit of FIG.
-1 through 101-X detects the presence of control character _CEA in the output buffer, which in turn causes feedback signal A _K ' to go low. The low signal A _K ' resets the input buffer of FIG. 6, but the signal is also sent to NAND gate 69 of FIG. 5 to reset the output of that gate even after the input buffer has been reset. Hold high. When control character _CEA is removed from input port 11 in response to input port control signal A being high, the input buffer is reset. That is, all signals D _J1 to D _JN go low. In response, all NANDs in Figure 4
The outputs of gates 40-1 through 40-N and 41-J go high. Clearing the input buffer described above also forces signal EA _A ' of FIG. 5 high. however,
The output of NAND gate 69 is held high by low signal A _K '. Signal A _K ' remains low until data is taken from the selected output port 12. When the output port control signal A ₀ goes high, the output of NAND gate 87 of FIG. 6 goes low, clearing the output buffer, so that the signal A _K ′ from the circuit of FIG. Go high. The output of NAND gate 69 in FIG. 5 then goes low, which in turn forces _S0 from NAND gate 53 to go low, thereby deselecting the previously selected output port 12. do. The signal S ₀ going low is the NAND gate 62
signals S ₀ +S ₁ block the input to the input buffer.
The low on NAND gate 62 is NAND gate 6
Force 3 to be high. NAND gate 64 goes low, which causes NAND gate 67 to go high, and signal EA _B ' is latched into NAND gates 65 and 66. With EA _B ' going high, NAND gate 42 in FIG. 4 goes low. Input port 11 then returns to its initial state. The details of one preferred embodiment of the invention have been described. However, many changes and modifications can be made without departing from the character and spirit of the invention. It is therefore to be understood that the invention is not limited to the embodiments described above, but is to be defined by the scope of the appended claims.