JPH025434A - Manufacture of field-effect transistor - Google Patents

Abstract

PURPOSE:To reduce the number of total steps in the case of forming field-effect transistors in an integrated circuit or the like, and to reduce an area required therefor by forming oblique parts at both sides of the lower part of a gate on the surface of a semiconductor region, and ion implanting with the gate on an oxide film formed on the surface as a mask. CONSTITUTION:A hill-like protrusion is formed on a semiconductor region 1, and oblique parts 1a are formed of both sides. An oxide film 5 is attached thereon, and a gate 6 is formed. Then, with the gate 6 as a mask the other conductivity type impurity is ion-implanted to form a pair of source, drain layers in a semiconductor region. Thus, the impurity concentration of inner source, drain layers to be diffused from the oblique parts in one ion implanting step can be reduced, the impurity concentration of the source, drain layer to be diffused from the flat part continued thereto can be raised, and an area required to form a transistor can be suppressed to a minimum.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing field effect transistors such as MOS transistors, and particularly to a method of manufacturing suitable for high voltage field effect transistors.

[Conventional technology]

As is well known, field effect transistors are used in a wide range of applications, not only as individual elements but also as basic circuit elements for integration into integrated circuit devices. It is becoming less and less unusual for things to be required to withstand voltages as high as several tens of cubic meters or more. When a high circuit voltage is applied to a field-effect transistor, breakdown phenomena such as so-called bunch-through tend to occur, and a phenomenon known as the short channel effect limits the voltage at which it can be used. As is well known, this short channel effect is a phenomenon in which a channel to be formed between the source and drain layers is pinched off by a depletion layer extending from the drain of a field effect transistor.・Various improvements have been made to the impurity diffusion structure or profile of the drain layer.

FIG. 3 shows a conventional method commonly called the etch bank method. This method, as shown in figure (d),
Normal source/drain WJ27 on both sides of gate 23
In addition to providing the source/drain layer 27, an inner source/drain layer 27 with a lower impurity concentration extends below the gate.
Providing the drain 1!125 prevents the short channel effect from occurring in each tube, and the manufacturing process thereof will be briefly explained below in order.

In the same figure (a), first, a thin gate oxide 11a22 is applied to the surface of a semiconductor region 21, which is an n-type semiconductor substrate or an epitaxial layer, and then a gate 23 made of polycrystalline silicon or the like is formed thereon as shown. do. Then, an oxide film 24 is formed on it by low pressure CVD method, for example, 0.5, 5.
The impurity 2 is grown on the surface of the semiconductor SI region 21 by ion implantation of boron B or the like as a p-type impurity using the gate 23 and the photoresist film 25 as a mask.
6a@Introduce. At this time, since the implanted boron ions B are considerably trapped by the relatively thick oxide film 24, the surface implantation density of the impurity 26a becomes relatively low.

In the same figure (b), the upper introduced impurity 26a is diffused by heat treatment, and the inner source/drain layer 2 with a low impurity concentration is
6 is formed in the semiconductor region 21, and then the oxide film 24 is etched by anisotropic etching such as reactive ion etching, leaving corners on the sides of the gate 23, called sidewalls, shown as 24a in the figure. and remove it. The same figure (C
), using the gate portion including the sidewall 24a and the photoresist film 27 as a mask, P-type impurities such as boron are ion-implanted as before to implant the illustrated impurity 28a into the surface of the semiconductor region at a high dose.

In the same figure (b), the source/drain layer 27 is formed in the semiconductor region 21 with a high impurity concentration by diffusing this impurity deeper than before by heat treatment, and then the oxide film 29 covering the entire source/drain layer 27 is formed in the semiconductor region 21. A field effect transistor is completed by sequentially providing electrode films 30 for drain and gate connections. In a transistor with such a double source/drain structure, a channel is formed between the tips of the inner source/drain layer 26 with a low impurity concentration that penetrates under the gate as shown in the figure.
Drain I? ! When a voltage is applied to 28, the depletion layer is less likely to extend from it to this channel formation, increasing the voltage value at which channel pinch-off and therefore short channel effects occur.

[Problem to be solved by the invention]

As can be seen from the above, in the etch-back method, after the first ion implantation is performed through the oxide film at a low impurity concentration, when the oxide film is etched, a part of it is left as a sidewall, and this is used as a mask for the second implantation. This is a clever method of creating a source/drain layer of 2ffi II m in a field effect transistor suitable for high voltage applications by performing ion implantation at a high impurity concentration, but it is necessary to perform ion implantation twice. Since related processes are also required, the overall number of processes increases and the cost tends to be relatively high. In addition, the width of the sidewall varies depending on the etch-back conditions of the oxide film, so it is necessary to allow some dimensional margin to ensure a good temperature. There is a problem with not being able to reduce the size very much.

An object of the present invention is to solve the problems of the prior art, and to make it possible to reduce the overall number of steps when fabricating field effect transistors into integrated circuits, etc., and to reduce the area required. .

(Means for Solving Problem L!) The present invention provides a field effect transistor including a step of forming sloped portions on both sides of the surface of a semiconductor region having one conductivity type, centering on the lower part of the gate; a step of providing a thin oxide film on the surface including the lower part of the gate and the slope part of the area;
A step of forming a gate at a predetermined location on the oxide ridge, and using the gate as a mask, an impurity of the other conductivity type is diffused from the surface of each sloped portion and the continuous flat portion by ion implantation to form a pair of impurities within the semiconductor SF region. The above-mentioned object is achieved by manufacturing the device through a step of forming source/drain layers.

The dimensions of the slope in the above structure will of course depend on the operating voltage of the transistor, but the height of the slope is usually 0.3μ or more, preferably 0.5μ or more, and the slope is 30 degrees. As mentioned above, it is preferable to set the angle to about 45 degrees. When field effect transistors are fabricated into integrated circuits, this sloped area is a so-called LOCO3ll which is usually provided between transistors or groups of transistors.
It is advantageous to shorten the process by using the process for 1. O.C.
When the OS film is removed by etching after formation, the slope of the semiconductor surface formed at the end can be used as the slope portion in the method of the present invention. If the field effect transistor is a discrete device and does not require LOCOSItff, this sloped portion can be formed by partially etching the semiconductor surface using an anisotropic etching method. The film is used to make the impurity doping density in the slope part different from the density in the flat part during the subsequent ion implantation process, but in the method of the present invention, it can be used in common with the gate oxide film, and its thickness is also the same. 0 suitable for gate oxide film
By selecting the ion accelerating voltage according to the thickness of this oxide film and the slope of the slope part during the ion implantation process, the slope part and the flat part can be set to about 0.05 to 0.1μ. The impurity introduction concentrations can be made different from each other.

[Effect]

As can be seen from the above-mentioned structure, the method of the present invention involves forming slopes in advance on both sides of the surface of the semiconductor #M3A which will be below the gate, and using the gate as a mask to form slopes continuous to the slopes. When implanting ions into a flat area, the impurity is implanted into the surface of the semiconductor region using an ion accelerating voltage selected according to the partial masking effect of the oxide film on the slope and the slope. By implanting the impurity into the sloped area, the concentration of impurities introduced into the sloped area was successfully reduced by more than an order of magnitude compared to the leveled area.

This allows the ion implantation process to be completed once, and by diffusing the impurities introduced in this single ion implantation, the impurity concentration is lower than that of the source/drain layer created in the flat area. Since the inner source/drain layer extends to the semiconductor region under the gate where the channel is formed, the above-mentioned short channel effect can be effectively prevented and the above-mentioned! 5I! be able to solve problems.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings. 1st
The figure shows an example in which the LOCO5 method is used in the slope forming process.

FIG. 6A shows the slope forming step. In this example, the semiconductor 6JTM1 is an n-type epitaxial layer for an integrated circuit, and a p-channel field effect transistor is built into it. First, a thin oxide film 2 is formed on the surface of the semiconductor region 1 to a thickness of about 0.1 μm by dry oxidation or pyrogenic method, and then a silicon nitride film is formed on the thin oxide film 2 to a thickness of about 0.7 μm by low pressure CVD method etc. The oxide film 4 is a so-called LOGO5 film, which is grown on the semiconductor surface and leaves a silicon nitride mask 3 at the location where the gate is to be provided by photoetching.
Oxidized B4 with a thickness of about 1 μm is formed by steam oxidation at °C for 3 hours. The nitride film 3 is removed using CF,
The process up to this point is carried out using a dry etching method using reactive gases such as □CO3 for integrated circuits.
This can be done simultaneously using the film formation process.

Before starting the process of forming the oxide film in FIG. 2B, the oxide film 4 in the area where the field effect transistor is to be formed is completely removed by chemical etching using, for example, oxic acid. L.O.
The oxide film 4, which is a GO5 film, is grown by cutting into the surface of the semiconductor region 1, so after its removal, the semiconductor region 1 under the gate remains as a hill-shaped protrusion in this embodiment.
Slope portions 1a are formed on both sides thereof. If the thickness of the oxidation layer 1a is 1μ as mentioned above, the height of this slope portion 1a will be approximately half that, 0.4 to 0.5μ, and its slope will be approximately as shown in the figure. 45 degrees are obtained.

In the process shown in FIG. 1, 115 oxide is applied, for example, by dry oxidation to a thickness of 0.05 to 0.1 μm in common with the gate oxide film. In the process shown in FIG. 6C, the gate 6 is formed to a thickness of about 0.5 .mu.m by growing polycrystalline silicon by the CVD method and photoetching it as usual. When patterning the gate 6, the right and left ends of the gate 6 overlap the top end of the oxide film 5 on the sloped portion la as shown in the figure, in order to stabilize the characteristics such as the pinch-off voltage of the transistor. desirable.

In the ion implantation process shown in FIG. 6(b), using the gate 6 and the photoresist film 9 as masks, in this example, boron B as a p-type impurity is introduced into the surface of the n-type semiconductor region 1 through a thin oxide film 5. At this time, the oxidized a5 on the sloped part 1a and the flat part lb acts as a so-called partial mask for the implanted ions, and the ion dose per area of the sloped part 1a is originally smaller than that of the flat part 1b due to its slope. In addition, since the effective thickness of the oxide film 5 with respect to the implanted ions increases, the partial masking effect moves strongly and the implanted impurity concentration is lower than that of the flat portion. Furthermore, since the accelerating voltage for the implanted ions is selected to a value suitable for emphasizing the partial masking effect of this oxidized H5, the overall effect of these factors will reduce the impurity 8a to the slope portion 1a.
The surface introduction density of the impurity 7a can be lowered by about one order of magnitude or more than the introduction density of the impurity 7a into the flat portion 1b. Note that the dose amount in this ion implantation step is, for example, 2xlO when the implanted ions are p-type boron as in this example.
"atom/C-degree, 3xlO in the case of n-type phosphorus" atom/
It is appropriate to set it as cj.

Figure (e) shows the state of the field effect transistor when it is completed. After the above ion implantation process, the semiconductor S■ region 1
The source/drain N7 and the inner source/drain layer 8 are created by diffusing the impurities 7a and 8a implanted into the sloped part 1a and flat part 1b of the surface of the transistor by heat treatment.・It is desirable that the diffusion of drain N7 be deep. For example, the diffusion depth is set to 1 under heat treatment conditions of 1100°C and 1 hour.
．． 5n, and the radius of curvature R of the bottom corner is made as large as possible. The diffusion depth of the inner source/drain layer 8 is slightly shallower than this because the impurity concentration is low, and the diffusion depth of the inner source/drain layer 8 is slightly shallower than this, as shown in the figure.
It is almost continuous with the drain 117 and its tip is connected to the gate 6.
It is diffused in a shape that goes slightly under the. The impurity concentration after this heat treatment is, for example, 10 in the source/drain layer 7.
About 11 atoms/C-, 1 in the inner source/drain layer 8
It is estimated that Ql11 atoms/d.

After the above heat treatment, an oxide WA 10 and a connecting film or electrode @ 11 are provided as usual, and terminals for the source S, drain D, and gate G of the field effect transistor are led out from the latter, respectively. In the field effect transistor completed in this way, the inner source/drain layer 8 is continuously formed near the gate 6 of the source/drain 1i1, so that the source/drain 1! I7 is easily diffused toward the inner source/drain layer 8, so that the radius of curvature R at its bottom becomes larger than that of the conventional one in proportion to the diffusion depth, and the withstand voltage value of the transistor is improved.

When a voltage is applied, the depletion layer extends from this source/drain layer 7 with a high impurity concentration, but there is an inner source/drain layer N8 between it and the gate 6, and it extends to the bottom of the gate. Therefore, the extension of the depletion layer is restricted by this, making it difficult to reach the channel forming surface under the gate (therefore, the short channel effect is effectively prevented). The area for the transistor is almost negligible even if the inner source/drain N8 is fabricated because it is fabricated using the slope part 1a, and its position and size can be accurately fabricated by a so-called self-alignment method using the gate 6 as a mask. Does not increase.

FIG. 2 shows a different embodiment of the present invention in a slope forming step corresponding to FIG. 1(a). In this example, for example, an n-channel field effect transistor as an individual element is fabricated in a semiconductor region 1, which is a p-type semiconductor substrate. In this embodiment, since the LOGOS process cannot be used as before, the sloped portion 1a is formed using photoresist 1151.
It is formed by an etching method using No. 12 as a mask. For this purpose, a photoresist 112 is patterned to have a thickness of, for example, 1n and a slightly larger pattern as shown by 12a in the figure at a location on the surface of the semiconductor region 1 where a gate is to be provided.

For example, the etching of the end face for forming the slope part is performed using CF4 and SF.
The surface of the semiconductor region 1 is etched to a depth of about 0.5 nm using a dry etching method using a reaction gas mixed with the following.At this time, as the etching progresses, the photoresist 1lfi12 is also gradually eroded and its width is reduced. As a result of the reduction, as shown in the figure, sloped portions 1a are formed on the surface of semiconductor inclined wall 1 on both sides of photoresist film 12, and flat portions 1b are formed in portions away from the photoresist film.

Moreover, the 11JI slope of the slope portion 1a can be made into a material by changing the mixing ratio of the two types of gases mentioned above as the reaction gas for dry etching. J! J can be adjusted. The subsequent steps in this embodiment can be carried out in the same manner as in the previous embodiment of FIG. 1, and the effects obtained by implementing the present invention are the same.

The method of the present invention is not limited to the embodiments described above, and can be implemented in various ways. For example, in the embodiments, the area under the gate is formed into a hill shape that is higher than both sides thereof, but in some cases, may be formed in the shape of a recess that is lower than both sides, and slopes may be formed on both sides thereof.

〔Effect of the invention〕

As described above, in the method of the present invention, the steps of forming slope portions on both sides of the semiconductor slope centering on the lower part of the gate on the surface of the semiconductor slope having one conductivity type, and forming the slope portions on the surface including the lower gate and slope portion of the semiconductor region. A step of providing a thin oxide film,
A process of forming a gate at a predetermined location on the oxide ridge, and using the gate as a mask, an impurity of the other conductivity type is diffused from the surface of each slope part and the flat part continuous thereto into the semiconductor region by ion implantation. Since a field effect transistor is manufactured through the process of forming a pair of source and drain layers, one step is performed by utilizing the slopes of the slopes formed on both sides of the lower surface of the gate of the semiconductor region. In the ion implantation process, it is possible to lower the impurity concentration of the inner source/drain layer diffused from this sloped area and to increase the impurity concentration of the source/drain layer diffused from the continuous flat area. - The drain structure can effectively prevent the channel pinch-off phenomenon and hence the short channel effect, thereby increasing the operating voltage of the field effect transistor.

As described above, the method of the present invention can manufacture high-voltage field effect transistors through a process that is more streamlined than the conventional method, and has the following advantages.

(1) The inner source/drain layer is formed using the sloped part, and the impurity can be diffused in the exact position and size by self-aligned ion implantation using the gate as a mask. Therefore, the area required for manufacturing the transistor can be minimized.

(2) As a result of the fact that the source/drain layer diffused from the flat part tends to spread toward the inner source/drain layer diffused from the adjacent sloped part, the radius of curvature of the bottom corner is smaller than that of the conventional double structure. By making it larger than the source and drain, the withstand voltage value when the field effect transistor is turned off can be improved.

(3) Since the impurity for the inner source/drain layer is ion-implanted into the sloped area using the gate as a mask, the inner source/drain layer is well extended to the channel formation surface under the gate during diffusion, and therefore the pinch-off starting voltage is It is possible to increase the value and reduce its variation.

The method of the present invention, which has the above-mentioned features, can be widely applied to field effect transistors for integrated circuits and individual devices, and is particularly useful for streamlining the manufacturing of transistors that operate at high voltages and requiring high withstand voltages, and improving their performance. is very useful.

[Brief explanation of the drawing]

1 and 2 relate to the present invention; FIG. 1 is a sectional view showing each main process of an embodiment in which the method for manufacturing a field effect transistor according to the present invention is applied to a transistor for an integrated circuit; The figure is a sectional view showing a state in a slope forming step of an embodiment in which the present invention is applied to a field effect transistor for an individual element. FIG. 3 is a cross-sectional view showing each main step of a typical manufacturing method of a field effect transistor according to the prior art. In FIG.
1a: Slope portion, 1b: Flat portion, 2: Oxide film, 3:
LOCO5 film growth mask, 4 dioxide film or LOG
OS film, 5; oxide film or gate oxide film, 6: gate,
7: Source/drain layer, introduced impurity for 7a near, 8
; Inner source/drain layer, 8a: Introduced impurity for 8,
9: Photoresist film, lO: Oxide film, 11: Electrode film or connection film, 12: Photoresist film, 12a: Original size of photoresist film, 21! Semiconductor area, 22:
Oxide film, 23: Gate, 24: Oxide film, 24a: Side wall, 25: Photoresist film, 26: Inner source/drain layer, 26a Impurity introduced for 16, 27: Photoresist film, 28: Source/drain layer, 28a :28
29: oxide film, 30: electrode film, B: boron ion, R: radius of curvature of the corner of the source/drain layer.

Claims (1)

[Claims] A step of forming slopes on both sides of the semiconductor region with the bottom of the gate centered on the surface of the semiconductor region having one conductivity type, a step of forming a thin oxide film on the surface of the semiconductor region including the bottom of the gate and the slopes, and oxidation. A process of forming a gate at a predetermined location on the film, and using the gate as a mask, an impurity of the other conductivity type is diffused from the surface of each slope and the continuous flat part by ion implantation to form a pair of impurities in the semiconductor region. sauce·
A method for manufacturing a field effect transistor, including a step of forming a drain layer.