JPH0256027A - Parallel processing system for digital signal processor - Google Patents

Abstract

PURPOSE:To enhance the efficiency of the parallel property, to execute other processing during the waiting time and to improve the throughput of the whole by executing independently a transfer and a control of an arithmetic instruction, while holding the causality of the transfer of data and the arithmetic instruction. CONSTITUTION:In the case of transferring simultaneously a dividing instruction (FDV), and a result of operation to a D register connected to an output of an ALU, an arithmetic instruction of the FDV, and the transfer of a result of operation of the FDV are executed by 27 cycles in an IR21 and by one cycle in an IR18, respectively, and as for the IR21, the instruction is held during the cycle, but as for the IR18, said instruction is held only during one cycle. In the remaining 26 cycles, a transfer instruction which is not related to a result of operation and a value of the operation can be executed. In the case of a conventional example, the transfer instruction which can be compounded with the dividing instruction is only one, but according to this invention, as long as the instruction is ended during 27 cycles, its number is not limited.

Description

[Detailed Description of the Invention] [Summary] Parallel processing of digital signal processors that improves the efficiency of parallelism while maintaining the causality of data transfer and arithmetic instructions, regarding a parallel processing method that realizes true high-speed operation of digital signal processors. A sequence control unit for controlling a program sequence of a digital signal processor having a random access memory, the sequence control unit for controlling a program sequence of a digital signal processor having a random access memory, the sequence control unit inputting data representing a predetermined program instruction, storing the data at times, and A first storage circuit that determines an address to be stored in the random access memory; A second memory circuit is connected to the first and second memory circuits to store the data temporarily, reads the data temporarily stored in the first and second memory circuits, decodes the data contents, and executes the data execution cycle. a decoder for determining the number of bits; a third storage means connected to the first storage circuit for inputting and temporarily storing data obtained by dividing the output of the first storage circuit into a predetermined number of bits; a second decoder that is connected to the first and third storage means, reads out the data temporarily stored in the first and third storage means, decodes the contents of the data, and determines the number of execution cycles of the data; and configure.

[Industrial application field]

The present invention is a digital signal processor (hereinafter referred to as DSP).
This paper relates to a parallel processing method that realizes high-speed operation.

At this time, while maintaining the causality of data transfer and calculation instructions,
There is a need for a DSP parallel processing method that increases the efficiency of parallelism.

[Conventional technology]

FIG. 4 is a block diagram showing the configuration of an example DSP.

FIG. 5 is a block diagram showing the configuration of a conventional circuit.

FIG. 6 is a time chart explaining the operation of the conventional example.

As shown in FIG. 4, the DSP 6 generally includes a RAM 3 for storing input data, and an AL for calculating data.
4, an address generator 2 that generates addresses for reading/writing data, an input/output unit 5 that inputs and outputs data, and a sequence controller 1 that controls sequences.

FIG. 5 is a diagram illustrating in detail the sequence control section 1 shown in FIG. 4. In the figure, a signal indicating an address designated by a program counter (hereinafter referred to as PC) 7 is input to a ROM 8, and data representing a program instruction stored at a corresponding address is read from the ROM 8. The above data is the instruction register (hereinafter referred to as IR)
9 and is temporarily stored in I?9 as shown in FIG. The address for storing in AM 3 is calculated in advance. (Lookahead decoding).

Data is read from IRQ, input to IRIO, temporarily stored, and decoder (hereinafter referred to as DEC)
11 is also input. The data read from IRIO is transferred to DEC11 by the timing signal from DHCII.
The DEC 11 decodes the input data from IRQ and IRIO separately.

In addition, since the number of cycles changes depending on the content of data representing an instruction, the cycle control unit (hereinafter referred to as CYC) 12
The number of execution cycles of instruction data is determined by

In one cycle of the PC shown in FIG. 6, for example, n
If a signal indicating the th address is output, IRQ
In the next cycle, the data stored in the nth address of ROM 8 is read out and temporarily stored, and
The address for storing in RAM 3 is calculated in advance. The results are then input to IRIO and DECII, respectively, to perform so-called pipeline processing.

In the next cycle, the DEC 11 performs, for example, division (
FDv) control command is decoded. In this case, data transfer is performed in the last cycle.

[Problems to be Solved by the Invention] However, in the above circuit, the DSP instructions are transfer (mere movement of data) and operation instruction (A+B, A) kB.
commands) are executed at the same time. Most transfer and arithmetic instructions are executed in one cycle, but some, such as division instructions, require as many as 27 cycles. In this case, the transfer performed simultaneously with the division instruction also operates as if it required 27 cycles.

Therefore, although instructions are executed in parallel, the throughput is significantly reduced. Therefore, the purpose of the present invention is to improve the efficiency of parallelism while maintaining the causality of data transfer and operation instructions. The purpose of this invention is to provide a parallel processing method.

The above problem is solved by the circuit configuration shown in FIG.

That is, in FIG. 1, there is shown a sequence control unit that controls the program sequence of a digital signal processor having a random access memory, which inputs data representing a predetermined program command, temporarily stores the data, and stores the data in the random access memory. a first memory circuit that determines an address for storage; and a second memory that is connected to the first memory circuit and reads out and temporarily stores data temporarily stored in the first memory circuit using a timing signal output from a decoder. connected to the circuit and the first and second storage circuits;
210 is connected to the first storage circuit, and has a decoder that reads data temporarily stored in the first and second storage circuits, decodes the contents of the data, and determines the number of execution cycles of the data; This is a third storage means for inputting and temporarily storing data obtained by dividing the output of the first storage circuit into a predetermined number of bits.

220 is a second decoder connected to the first and third storage means, which reads out the data temporarily stored in the first and third storage means, decodes the contents of the data, and determines the number of execution cycles of the data. It is. Configure by adding the above 210.220.

[For production]

In FIG. 1, one side of the data divided into a predetermined number of bits of the output of the first storage circuit is input and temporarily stored in the third storage means 210.

The second decoder 220 reads out the data temporarily stored in the first and third storage means, decodes the contents of the data, and determines the number of execution cycles of the data. Then, a corresponding control signal is output.

On the other hand, in the second storage circuit 180, the other of the divided data is input and temporarily stored. and decoder 19
0, the data temporarily stored in the first and second storage circuits is read out, the contents of the data are decoded, and the number of execution cycles of the data is determined.

Then, a corresponding control signal is output.

For example, when executing an instruction that requires about 27 cycles, such as a division instruction, the third storage means 210,
The second decoder 220 performs calculations of instructions, and the second storage circuit 180 and decoder 190 perform instructions other than calculations, such as transfer.

As a result, throughput can be improved by making data transfer and control of arithmetic instructions independent while maintaining causality between data transfer and arithmetic instructions.

〔Example〕

FIG. 2 is a block diagram showing the configuration of a circuit according to an embodiment of the present invention.

FIG. 3 is a time chart explaining the operation of the embodiment.

The same reference numerals refer to the same objects throughout the design.

As shown in FIG. 2, the present invention differs from the conventional example in that lR21, DEC22, and CYC23 are added to the conventional example.

Figure 3 shows the division instruction (FDv) (27 cycles), AL
This shows a case in which calculation results are simultaneously transferred to a D register (not shown) connected to the output of U.

The FDV operation instruction takes 27 cycles in lR21, P
Transfer of the DV operation result is performed in lR18 in l cycles, lR21 holds the instruction for 27 cycles, but lR18 holds only one cycle. remaining 26
In a cycle, a transfer instruction that is not related to the operation result or the value of the operation can be executed.

In the conventional example, the number of transfer instructions that can be combined with a division instruction is limited to one, but in the present invention, there is no limit to the number as long as the transfer instruction is completed within 27 cycles. (≦27).

As a result, when a calculation requires a long cycle, the overall throughput can be improved by performing transfer or other processing that may be performed during the waiting time.

〔Effect of the invention〕

As described above, according to the present invention, throughput can be improved by making the control of data transfer and arithmetic instructions independent while maintaining the causality between data transfer and arithmetic instructions.

[Brief explanation of the drawing]

Fig. 1 is a principle diagram of the present invention, Fig. 2 is a block diagram showing the circuit configuration of an embodiment of the invention, Fig. 3 is a time chart explaining the operation of the embodiment, and Fig. 4 is an example of an OSP. FIG. 5 is a block diagram showing the configuration of a conventional circuit, and FIG. 6 is a time chart illustrating the operation of the conventional example. In the figure, 210 is the third storage means, and 220 is the second decoder. (7) Principle g Cow 1 day - 45') (7) T) SF cy:, *Follow following R'/2Q thousand 4 Z

Claims (1)

[Claims] A sequence control section for controlling a program sequence of a digital signal processor having a random access memory, the sequence control section for inputting data representing a predetermined program instruction, temporarily storing the data, and storing the data in the random access memory. a first memory circuit (170) for determining an address; connected to the first memory circuit;
A decoder (
190), a second storage circuit (180) that reads and temporarily stores the data according to the timing signal of the output of the first and second storage circuits (180);
a decoder (1) connected to the first and second storage circuits, reads the data temporarily stored in the first and second storage circuits, decodes the contents of the data, and determines the number of execution cycles of the data;
90), the third storage means (2) is connected to the first storage circuit and inputs and temporarily stores data obtained by dividing the output of the first storage circuit into a predetermined number of bits.
10) is connected to the first and third storage means, reads out the data temporarily stored in the first and third storage means, decodes the contents of the data, and calculates the number of execution cycles of the data. 1. A parallel processing method for a digital signal processor, characterized in that a second decoder (220) is added.