JPH03232019A - Information processor - Google Patents

Abstract

PURPOSE:To accelerate the execution cycle of an instruction by computing a jump address and executing the instruction stored in a second microinstruction register when it is judged that the instruction of the second microinstruction register is an unconditional jump instruction. CONSTITUTION:When it is judged that the instruction stored in the second microinstruction register 2 is the unconditional jump instruction, it is decoded with a jump instruction judging decoder 4, and furthermore, the jump address of it is computer with a second address arithmetic circuit 9, and it is sent to a first address line 10 via a first address circuit 12, and simultaneously, the instruction stored in the second microinstruction register 2 is executed. Thereby, a fast processor can be realized.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an information processing device.

[Conventional technology]

Conventionally, when executing a jump instruction, the processor of this type of information processing device calculates the jump address when the jump condition is satisfied during execution of the instruction, outputs the result to the address bus, and executes the next instruction from the storage unit. I was taking it out.

[Problem to be solved by the invention]

The above-described conventional information processing apparatus executes the jump instruction as a single instruction, and therefore only executes the instruction execution cycle, which poses a problem in that the instruction execution cycle is delayed.

[Means to solve the problem]

The information processing device of the present invention includes a processor and a storage unit that stores therein a program that instructs the operation of the processor, and the processor reads a program from the storage unit and operates according to the instructions, and at the same time, the next program is started. An information processing device that outputs a stored address and reads the contents of the address from the storage unit,
(A) a first microinstruction register that stores an instruction to be executed; (B) a second microinstruction register that stores an instruction stored at the next address of the storage section where the instruction to be executed was stored; (C) a jump instruction determination decoder that determines whether the instruction in the second microinstruction register is an unconditional jump instruction or a conditional jump instruction; <D) the jump instruction determination decoder determines whether the instruction in the second microinstruction register is (E) a first address circuit that outputs a jump destination address to the storage unit when the instruction is determined to be an unconditional jump instruction; (E) the jump instruction determination decoder determines whether the instruction in the second microinstruction register is a conditional If it is determined to be 1 command 1. (F) an address register that stores a jump destination address when the conditional jump instruction is established; an address calculation circuit that calculates the jump destination address when the instruction is established; (G) a condition storage unit that stores the condition of the conditional jump instruction; (H) an input or output of the condition storage unit that stores the condition; A second address circuit outputs the output value of the address calculation circuit to the address of the condition storage section when the condition is satisfied.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

The information processing device shown in FIG. 1 includes a microinstruction storage unit (storage unit) 5 that stores programs, a first microinstruction register 1 that stores instructions to be executed, and a microinstruction register 1 that stores instructions to be executed. A second microinstruction register 2 that stores the instruction stored at the next address in the storage section, an instruction decoder 3, and a jump that determines whether the instruction in the second microinstruction register is an unconditional jump instruction or a conditional jump instruction. an instruction judgment decoder 4, an address register 7 for storing jump addresses, a first address calculation circuit (address calculation circuit) 8 for calculating the jump address, a second address calculation circuit 9 for calculating the next address, When the jump instruction determination decoder determines that the instruction in the second microinstruction register is an unconditional jump instruction, the first address circuit 12 outputs the jump destination address to the storage section, and the input or output of the condition storage section 14 If either condition is not satisfied, the condition storage unit 14
A second circuit that outputs the output value of the address calculation circuit to the address of
The address circuit 13 includes a condition storage section 14 that stores conditions for conditional jump instructions.

Next, the operation will be explained.

As shown in FIG. 2, when the processor executes one program instruction at the rising edge of the storage section, it outputs an address for fetching the next instruction from the first address line 1o in accordance with that instruction. Based on the output address, the next program instruction is read from the microinstruction storage section 5, execution starts at the next rising edge of the clock, and the process is repeated. The above operation is the same as before.

Here, the microinstruction storage unit 5 is composed of, for example, a dual port memory, and the address value of the instruction to be executed is outputted to the first address line 10. at the same time,
The next address value of the first address line 10 is output to the second address line 11 . The output data of each address is output to the first microinstruction register 1 and the second microinstruction register 2, respectively, and stored at the rising edge of the clock. First microinstruction register 1
The instructions stored in are decoded by the instruction decoder 3 and executed.

The instruction stored in the second microinstruction register 2 is determined whether the instruction stored in the first microinstruction register 1 is a jump instruction or the instruction stored in the second microinstruction register 2
This is the next instruction to be executed, unless the instruction stored in is an unconditional jump instruction.

Here, if the instruction stored in the second micro-instruction register 2 is a conditional jump instruction, it is decoded by the jump instruction determination decoder 4, and the instruction is decoded by the first address calculation circuit 8.
The jump address when the jump condition of the jump instruction is satisfied is calculated, and the address register 7 is
is stored in Then, if either the input or the output of the storage section 14 that stores the jump condition satisfies the jump condition, the output of the first address calculation circuit 8 is sent to the first address line 10 by the second address circuit 13. At the same time, the instruction stored in the first microinstruction register 1 is executed.

Next, if the instruction stored in the second microinstruction register 2 is an unconditional jump instruction, it is decoded by the jump instruction determination decoder 3, and furthermore, a jump address is calculated by the second address calculation circuit 9. The instruction stored in the second microinstruction register 2 is executed at the same time that the instruction is sent to the first address line 10 through the first address circuit 12.

〔Effect of the invention〕

As explained above, the present invention has a first microinstruction register that stores an instruction to be executed, and a microinstruction register that stores an instruction stored at the next address of the storage section where the instruction to be executed is stored. a jump instruction determination decoder that determines whether the instruction in the second microinstruction register is an unconditional jump instruction or a conditional jump instruction;
A first address circuit that outputs the jump destination address to the storage unit when the jump instruction determination decoder determines that the jump is an unconditional jump, and a first address circuit that outputs the jump destination address to the storage unit when the jump instruction is determined to be a conditional jump instruction and the jump destination when the jump instruction is established. an address calculation circuit that calculates the address of , a condition storage unit that stores condition jump conditions, and when either the input or output of this condition storage unit satisfies the condition, outputs the output value of the address calculation circuit to the storage address. By including the second address circuit that performs the second address circuit, there is an effect that a high-speed processor can be realized.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
FIG. 3 is a diagram showing the timing of each part of the information processing device shown in the figure. l...-first microinstruction register, 2...
... second microinstruction register, 3 - ... instruction decoder, 4 ... jump instruction judgment decoder, 5 ... microinstruction storage section, 7 ....・
Address register, 8...first address arithmetic circuit, 9...second address arithmetic circuit, 10.
...First address line, 11...Second address line, 12...First address circuit, 1 3...Second address circuit , 4... Condition storage section.

Claims (1)

[Scope of Claims] A storage unit that stores a processor and a program that instructs the operation of the processor is provided, and the processor reads a program from the storage unit and operates according to the instructions, and at the same time starts the next program. An information processing device that outputs a stored address and reads the contents of the address from the storage unit, comprising: (A) a first microinstruction register storing an instruction to be executed; (B) an instruction to be executed; a second microinstruction register that stores the instruction stored at the next address of the storage unit; (C) whether the instruction in the second microinstruction register is an unconditional jump instruction or a conditional jump instruction; (D) a jump instruction determining decoder that outputs a jump destination address to the storage section when the jump instruction determining decoder determines that the instruction in the second microinstruction register is an unconditional jump instruction (E) an address register that stores a jump destination address when the conditional jump instruction is established when the jump instruction determination decoder determines that the instruction in the second microinstruction register is a conditional jump instruction; , (F) when the jump instruction determination decoder determines that the instruction in the second microinstruction register is a conditional jump instruction, an address calculation circuit that calculates a jump destination address when the conditional jump instruction is established; G) a condition storage unit that stores the conditions of the conditional jump instruction; (H) when either the input or output of the condition storage unit satisfies the condition, the output value of the address calculation circuit is sent to the address of the condition storage unit; An information processing device comprising: a second address circuit that outputs.