JPH0256655A - Detecting system for error of memory - Google Patents

Abstract

PURPOSE:To constitute the title system so that a scale of a hardware is not increased by executing a memory error detection processing in the idle time of a CPU and reading out data written in a ROM by the CPU, executing the error detection processing, and informing its result to the outside of a microprocessor system through an I/O port. CONSTITUTION:The title system is provided with a CPU 1 and an I/O port 4. In a ROM 2, data for controlling an error and a program are stored, and the CPU 1 reads out the contents of the ROM 2 and executes an error detection processing, and the I/P port 4 informs the result of the error detection processing to the outside. The CPU 1 derives a parity of every byte in a program area, collates it with a parity bit in a an error control use data store area and detects abnormality of memory. In such a way, by executing a memory error detection processing in an idle time of the CPU 1, an error can be detected surely by the hardware of a small scale.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a microprocessor system, and particularly to a memory error detection method thereof.

(Prior Art) Conventionally, a memory error detection method in a microprocessor system has been executed according to a flow as shown in FIG. Here, the memory map was constructed as shown in FIG.

In Figures 5 and 6, when performing memory error detection, a ROM vertical parity check or CRC check is implemented as a function of initial processing, and a ROM horizontal parity check in real time is implemented by hardware. Ta.

In a system that detects the CRC check or vertical parity of the ROM here, the C
RC or vertical parity was written. Furthermore, there are areas on the memory map that are not used by the system.

(Problem to be Solved by the Invention) The conventional memory error detection method described above executes memory error detection processing only during initial processing, so it cannot detect errors if the memory is destroyed during operation. There is a drawback.

Furthermore, when memory error detection is implemented using hardware, a special detection circuit is required, so there is a drawback that the hardware scale is large.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory error detection method that eliminates the above drawbacks by executing memory error detection processing during CPU idle time, and is configured to reliably detect errors with small-scale hardware. Then there is a certain thing.

(Means for solving the problem) The memory error detection method according to the present invention is applicable to ROM and CP.
This configuration includes a port U and an I10 port.

The ROM is for storing error 9 control data and programs.

The CPU is a round CPU that reads the contents of the ROM and performs error detection processing.

The I/O port is for notifying the result of error detection processing to the outside.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a memory error detection method according to the present invention. In Figure 1 h, 1 is CP
U, 2 is ROM, 3 is RAM, and 4 is I10 port.

The memory map of ROM2 is structured as shown in FIG.

The CPUI executes processing using the micro hood according to the flowchart shown in FIG.

In the error control data storage area shown in Figure 2, the horizontal parity pits of the program area are stored one bit at a time.

In the memory error detection process shown in FIG. 8, the CPU 1 obtains the parity for each byte in the program area, and compares it with the parity pit in the error control data storage area to detect an abnormality in the memory.

FIG. 4 is a flowchart showing details of memory error detection processing. Memory error detection is performed according to the flowchart in FIG.

(Effects of the Invention) As explained above, the present invention enables the CPU to execute error detection processing during idle time of the CPU.
It is possible to read the data written in the OM, execute error detection processing, and notify the result of the error detection processing to the outside of the microprocessor system via the I/O port, increasing the hardware scale. It has the effect of never happening.

Furthermore, since errors in memory can be detected in real time, the reliability of the system can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a memory error detection method according to the present invention. Figure ta2 is a memory map diagram of the ROM in Figure 1. FIG. 8 is a flowchart showing the processing of the CPU in FIG. FIG. 4 is a flowchart showing details of the memory error detection process of FIG. 1. FIG. 5 is a flowchart showing an example of memory error detection processing according to the prior art. Figure w46 is a memory map diagram of the ROM in the conventional system. 1...CPU 2...ROM 3...RAM 4...I10 port

Claims (1)

[Claims] R for storing error control data and programs
The device is characterized by being configured to include an OM, a CPU for reading the contents of the ROM and executing error detection processing, and an I/O port for notifying the result of the error detection processing to the outside. Memory error detection method.