JPH0258236A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To make the relief to an electric field and the driving capacity of elements compatible with each other even if the gate length is further shortened by a method wherein a low concentration diffused layer is formed using upper layer gate electrodes as masks and after forming lower layer gate electrodes using the first insulator sidewall films as masks, high concentration diffused layers are formed using the second insulating sidewall films as masks and so forth. CONSTITUTION:The first conductor films 5, a conductor barrier film 7 and the second conductor film 8 are successively deposited on the first conductivity type semiconductor substrate 1 having a gate oxide film on the surface thereof and then upper layer gate electrodes 10 comprising the second conductor film 8 are formed using mask patterns 9 while the second conductivity type low concentration diffused layer is formed on the substrate 1 using the gate electrodes 10 as masks. Next, the first insulator sidewall films 13 are formed on the sidewalls of the upper layer gate electrodes 10; the conductor barrier films 7 and the first conductor film 5 are etched away using the mask patterns 9 and the first insulator sidewall films 13 as masks to form lower layer gate electrodes 15. Finally, the second insulator sidewall films 16 are formed outside the first insulator sidewall films 13 and then the second conductivity type high concentration diffused layers 17 is formed on the substrate 1 using the mask patterns 8, using the first insulator sidewall films 13 and the second insulator sidewall films 16 as masks.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device including an insulated gate field effect transistor.

[Conventional technology]

2. Description of the Related Art In order to achieve higher integration and higher performance of semiconductor devices, miniaturization of semiconductor elements is being promoted. The design rules have already become sub-micron, less than 1 micron.
It is expected that further miniaturization will occur in the future. Needless to say, it has become difficult to process elements with submicron dimensions with high precision, and it has been pointed out that there are problems with long-term reliability of elements formed with submicron dimensions. For example, these include fluctuations in the dark value voltage and drain current due to hot carriers, or leakage current due to band-to-band tunneling occurring in the highly doped drain region directly under the gate electrode. These problems are caused by the high electric field near the drain due to the scaling of the geometric dimensions and impurity concentration while keeping the current voltage constant.

Reliability can be maintained if the power supply voltage is also scaled, but there are other problems such as system compatibility and reduced operating speed.

One method for mitigating high field effects is a lightly doped drain structure (LDD).

That is, by creating a drain structure in which a low concentration diffusion layer is formed in addition to a high concentration diffusion layer, the electric field at the drain end is relaxed and device deterioration due to real carriers is suppressed. The disadvantage of the LDD structure is that if the electric field is sufficiently relaxed by simply lengthening the low concentration diffusion layer region, the resistance in the low concentration diffusion layer region will increase, which will reduce the driving ability of the element and reduce the operating speed of the device. It is something you end up doing.

As an element structure that achieves both electric field relaxation and element driving ability, Ryu Izawa et al. published IEICE Technical Research Report Vol. 87, No. 343, 31-3 on January 25, 1988.
On page 6 [High withstand voltage/high speed 5■ operation submicron device G
There was a presentation titled OLDJ. According to this, an n-channel field effect type MOS transistor (n
We are proposing a method for manufacturing MO3FET). According to this method, as shown in FIG. 2(a), a two-layer polycrystalline silicon (polysilicon) film is formed on a gate oxide film 32 on a p-type silicon substrate 31 with a native oxide thin film 34 in between. The second polycrystalline silicon film 35 is etched using the first CVD5 i Oz film 36 as a mask. At this time, it is necessary to perform etching under highly selective conditions in order to stop the etching with the native oxide thin film 34, and as shown in FIG. 35 is side etched. Subsequently, a low concentration n-swelling diffusion layer 37 is formed by ion implantation. As shown in FIG. 2(c), CVD5 i
After O□ film deposition, reactive ion etching (RIE)
The second CVDSi is applied only to the sidewalls of the gate electrode pattern.
An Oz film 38 is formed, and the first polycrystalline silicon layer 33 is etched using this as a mask. As shown in FIG. 2(d), after forming a high concentration n-swell diffusion layer 39 by ion implantation, both ends of the first polycrystalline silicon film 330 are selectively oxidized under wet oxidation conditions of 800°C. A SiO□ film obtained by oxidizing a polycrystalline silicon film is indicated by 40.

Using the above manufacturing process, a sufficiently long low concentration n-type diffusion N
37 are present directly below both ends of the gate electrode, and a high concentration n-swelling diffusion layer 39 is formed outside the gate electrode. As a result, the lateral electric field is relaxed at the drain end, and in the lightly doped n-swelled diffusion layer 37, carriers are induced at the gate oxide film interface by the gate electric field, reducing the resistance.

In other words, it has become possible to achieve both electric field relaxation and element driving ability.

[Problem to be solved by the invention]

In the method of manufacturing a semiconductor device explained in FIG. 2, when etching the second polycrystalline silicon film 35,
An extremely thin natural oxide thin film 34 is used as an etching stopper to prevent the first polycrystalline silicon film 33 from being etched.
Since the first CVD SiOz film 3
A second polycrystalline silicon film 35 is side-etched under both ends of the polycrystalline silicon film 35. If an attempt is made to further refine the gate electrode, the width of the first CVD5 i O□ film 36 and the side etching width will become equal to or less than that, and the
It becomes impossible to support the VDSiOz film 36. To prevent this, the thickness of the second polycrystalline silicon film 35 can be reduced, but this increases the resistance of the gate electrode and reduces the device operating speed. Further, when the polycrystalline silicon used as the gate electrode is miniaturized, the increase in resistance cannot be ignored, and furthermore, although the natural oxide thin film 34 is thin, it is not preferable for high-speed operation to have an insulating layer therebetween.

An object of the present invention is to provide a method for manufacturing a semiconductor device that solves the above-mentioned problems.

[Means to solve the problem]

The method for manufacturing a semiconductor device of the present invention includes the step of successively depositing a first conductor film, a conductor barrier film, and a second conductor film on a semiconductor substrate of a first conductivity type having a gate oxide film on at least the surface thereof. Then, an upper layer gate electrode made of the second conductor film is formed in a desired region using a mask pattern, and a low concentration of a second conductive type is diffused onto the first conductive type semiconductor substrate using the upper layer gate electrode as a mask. forming a first insulator sidewall film on the sidewall of the upper layer gate electrode, and etching the conductor barrier film and the first conductor film using the mask pattern and the first insulator sidewall film as a mask; forming a second insulator sidewall film outside the first insulator sidewall film, and combining the mask pattern, the first insulator sidewall film, and the second insulator sidewall film; The method is characterized in that it includes a step of forming a high concentration diffusion layer of a second conductivity type on the semiconductor substrate of the first conductivity type using a mask.

[Effect]

According to the present invention, when performing reactive ion etching on the upper layer gate electrode, the upper layer gate electrode is formed under anisotropic etching conditions that have an appropriate etching selectivity as an etching stopper and less side etching, thereby reducing the gate length. can correspond to Further, the position of the end of the high-4 degree diffusion layer was controlled by the thickness of the second insulator sidewall film. In addition, if a barrier film is used, even if different materials are used for the upper and lower gate electrodes, mutual reactions due to heat treatment after gate electrode formation can be prevented, so the work function of the gate electrode is determined by the lower gate electrode, and the resistance The value can be reduced by an upper gate electrode layer.

Further, since the barrier film is conductive, no insulating film is required between the upper layer gate electrode and the lower layer gate electrode, so that no operational problems occur.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a schematic diagram sequentially showing the cross-sectional structure of each step for explaining the manufacturing of a CMOS according to the manufacturing method of the present invention.

First, as shown in FIG. 1(a), p-type silicon 1Jf
An n-well 2 is formed on the flll, an element isolation 5iQ2 film 3 is formed to dielectrically isolate a semiconductor element to be formed later, and a gate oxide film 4 is formed by thermal oxidation.

Next, as shown in FIG. 1(b), after depositing a 2,000-layer polycrystalline silicon film, phosphorus is added to the polycrystalline silicon film on the p-type silicon substrate l by ion implantation into the n-well 2.
Boron is implanted into the upper polycrystalline silicon film to form an n polycrystalline silicon film 5p and a polycrystalline silicon pattern film 6, respectively. Next, 300 titanium nitride films 7 were deposited, followed by 15
00 tungsten films 8 were continuously sppack deposited,
CVD5 i O□ at a desired position on the tungsten film 8
A mask 9 is formed.

Next, as shown in FIG. 1(c), the tungsten film 8 is subjected to CVD by RIE using the CVD5 iO□ mask 9.
After forming the second gate electrode 10 with a tungsten film left only directly under the D5iO□ mask 9, a low concentration n-swell diffusion layer 11 and a low concentration p-swell diffusion layer 12 are formed in desired regions by ion implantation.

Next, as shown in Figure 1(d), 1500 CVD5
An iO□ film is deposited on the entire surface, and a first cVDsioz sidewall film 13 is formed only on the side surface of the second gate electrode 10 by RIE. Next, CV D S iOz mask 9 and 1st C
Using the VDSiOz sidewall film 13 as a mask, the n゛゛crystalline silicon first gate electrode 14 and the p゛゛crystalline silicon first gate electrode! 5 is formed by tE.

Next, as shown in FIG. 1Ce), the first CVD5iO
□By the same method as that used to form the sidewall film 13, the second CV
After forming the DSiO□ sidewall film 16 and forming the high concentration n expansion layer 1 & layer 17 and the high concentration p expansion diffusion layer 18 in desired regions by ion implantation, the low concentration diffusion layer is formed directly under the end of the first gate electrode. A CMOS having a structure in which the high concentration diffusion layer is formed outside the edge of the first gate electrode can be obtained.

Finally, as shown in Figure 1(f), CVD5iO is applied to the entire surface.
, Ji insulation film 19 is deposited, and after contact holes are opened, aluminum interconnections 20 are formed.

In the above embodiments, a case has been described in which the present invention is applied to the manufacture of CMOS, but the present invention is not limited thereto, and can also be applied to the manufacture of nMOSFETs and pMOSFETs. In addition, n + p as the first gate electrode, the conductive barrier film, and the second gate electrode, respectively.
+ Although a combination of polycrystalline silicon, titanium nitride film, and tungsten film was used, the material and film thickness are not limited to this.The second gate electrode is made of a material with low resistivity and has a high etching selectivity with respect to the barrier film. It is sufficient that the conductive barrier film is formed by heat treating the first gate electrode and the second gate electrode.
It is sufficient that the first gate electrode has barrier properties to prevent reaction of the gate electrode, and the first gate electrode may be made of a material with low resistivity. Furthermore, although the SiO□ film was used as the sidewall insulating film, the film thickness and material are not limited thereto.

〔Effect of the invention〕

By using the manufacturing method of the present invention, side etching of the upper layer gate electrode is eliminated. As a result, the lateral electric field is relaxed at the drain end, and in the lightly doped diffusion layer, carriers are induced at the gate oxide film interface by the gate electric field, reducing resistance, achieving both electric field relaxation and device drive performance. This has become possible even when the gate length is further reduced. In addition, since the gate electrode and the high concentration diffusion layer do not overlap, the gate and source
The parasitic capacitance between the drains has been reduced, increasing the operating speed, and interband tunneling current in the drain region due to the gate electric field has been reduced. Furthermore, since the conductive barrier film is used as an etching stopper, side etching can be prevented and miniaturization can be accommodated. Furthermore, since no insulating film is required between the upper layer gate electrode and the lower layer gate electrode, no operational problems occur.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram sequentially showing a cross-sectional structure of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a schematic diagram sequentially showing a cross-sectional structure of a semiconductor device according to a conventional example. l, 31...P type silicon substrate 2...N well 3...4.32...5...6...7...8...9...10... IL 37・ 12・ ・ ・ 13・ ・ 14・ ・ ・ 15・ ・ ・ ・ 16・ ・ ・ 17, 39・ 18・ ・ 19・ ・ ・ 20・ ・ Element isolation Si0g film Gate oxide film n Crystalline silicon peritoneum polycrystalline silicon peritonealized titanium film tungsten film CVD5iO mask 2nd gate electrode low concentration n swelling diffusion layer low concentration p swelling diffusion layer 1st cVDsio □ side wall film n crystal silicon 1st gate electrode° p electrode 2CVDSiOz sidewall film, high concentration n-swelling diffusion layer, high-concentration p-swelling diffusion layer, CV D Si Q z interlayer insulating film, aluminum wiring polycrystalline silicon first gate 33, 34, 35, 36, 38, 40, 1st Polycrystalline silicon film Natural oxide thin film Second polycrystalline silicon film First CV D SiOz film Second CVDSi○2 film SiO□ film obtained by oxidizing polycrystalline silicon film

Claims (1)

[Claims] (1) A step of successively depositing a first conductor film, a conductor barrier film, and a second conductor film on a semiconductor substrate of a first conductivity type having a gate oxide film on at least the surface, and using a mask pattern. forming an upper gate electrode made of the second conductor film in a desired region and forming a low concentration diffusion layer of a second conductivity type on the semiconductor substrate of the first conductivity type using the upper gate electrode as a mask; A first insulator sidewall film is formed on a sidewall of the upper gate electrode, and the conductor barrier film and the first conductor film are etched using the mask pattern and the first insulator sidewall film as a mask to form a lower gate electrode. forming a second insulator sidewall film on the outside of the first insulator sidewall film; and using the mask pattern, the first insulator sidewall film, and the second insulator sidewall film as a mask, forming the first conductivity type; forming a highly doped diffusion layer of a second conductivity type on a semiconductor substrate.