JPH0258352A - Testing circuit for semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the number of transistors for testing and number of wirings for clock transmission and to alleviate the load of a logic designer by fixedly providing clock transmission wirings from a clock input cell to a basic cell through a buffer independently of other wirings. CONSTITUTION:Clock transmission wirings 15 are fixedly wired near aluminum or polysilicon, and may be formed of the same material as that of wiring basic cells to each other, and signals on the wirings are different. Clocks are applied externally to one 11-2 of input/output cells operated as a clock buffer 14. They are distributed from the line 15-1 from the buffer 14 to basic cell rows 12-1, 12-2,..., and then distributed from the line 15-2 to the basic cells. Clocks are applied from its scan clock terminal to the logic unit cell 16 of the basic cells. The buffer 14 and the lie 15-1 may be disposed along the lower side, and the cell 16 may be disposed at the other place.

Description

[Detailed Description of the Invention] Summary] The present invention provides a method for testing in the design stage of a mask slice type semiconductor integrated circuit (hereinafter, a large-scale semiconductor integrated circuit will be abbreviated as LSI in this specification) having a built-in scan circuit. Regarding LSI test circuits that reduce the number of elements used in added circuits, the number of test transistors, the number of clock transmission wiring networks, and the burden on logic designers in logic design including scan circuits will be reduced. The purpose of the present invention is to provide a test circuit for an LSI that reduces the amount of noise caused by a clock.In a test circuit for semiconductor integrated circuits that applies a clock and tests the presence or absence of a failure in a semiconductor integrated circuit using a scan circuit method, the buffer is removed from the clock cell manually. The structure is such that the clock transmission wiring that reaches the basic cells via the integrated circuit cells is provided fixedly and independently of other wiring that connects the integrated circuit cells.

[Industrial Application Field] The present invention is a mask slice type LS with a built-in scan circuit.
At the design stage of I, the number of elements used in the circuit added for testing was reduced.
Regarding SI test circuits.

As semiconductors become highly integrated into LSIs, the proportion of time required to create test circuits and test data backbones in the development process increases.

For this reason, a ``scan circuit method'' is used to easily conduct tests, but it is more complex than a normal circuit and requires a significant increase in the number of transistors and nets, so there was a desire to simplify it.

[Prior art] LSIs sometimes detect the presence or absence of a failure that has occurred during the manufacturing process, or check whether a previously anticipated failure exists, but usually only the former is required; In order to feed back the results, check the latter. When detecting the presence or absence of a failure, it is natural that LSIs designed and manufactured using "design for testability" can be tested more easily than those designed and manufactured using other design methods.

The only things that can be used for testing the LSI (detecting the presence or absence of a failure) are the manual pins and output bins used as interfaces with the outside. In order to detect internal failures using only these pins, first create in advance a sequence of input cover turns to be applied to the input pins and a sequence of response output cover turns expected to be applied to the output pins. These input cover turn rows and output cover turn rows are compared, and if they match, it is determined that there is no failure, and if they do not match, it is determined that there is a failure.

At this time, in sequential circuits that include memory circuits such as flip-flops, the number of internally recorded ta states increases, making fault detection (testing) difficult. It can be easily executed by replacing it with a circuit test. That is, as shown in FIG. 3, a scan circuit 3 is added for setting the states of flip-flops (hereinafter abbreviated as FF) 2-1.2-2-2-n in the sequential circuit 1 of the LSI. All FF 2
-1.2-2. -2-n is detected by the clock input from the input terminal scan in 4 of the scan circuit 3.
The state of F can be set directly from the outside. At this time FF
The output point of OF is treated like an external input bin, and the input point of other OF is treated as an external output bin. Since the hatched portion is a combinational circuit, testing of a sequential circuit can be replaced with a test of a combinational circuit. At this time, all FFs must be connected to form a shift register. Each time one scan clock is applied, the state of the FF shifts, and the scan circuit 3
are extracted sequentially starting from the end.

The above scan circuits were designed by logic designers, including circuits used only for testing purposes.

[Problem to be solved by the invention] Therefore, when designing a logic including a scan circuit,
This increases the number of buffer transistors for clocks and the number of clock transmission wiring networks, and has the disadvantage of placing a burden on logic designers. In recent LSIs, the number of FFs used has reached several hundred, and the wiring for I-link transmission must have a tree structure, resulting in the use of several tens of clock buffers.

An object of the present invention is to improve the above-mentioned drawbacks and to reduce the number of test transistors, the number of clock transmission wiring networks, and the burden on logic designers in logic design including scan circuits. The purpose is to provide test circuits.

[Means for Solving the Problems] The present invention has the following configuration in a test circuit for a semiconductor integrated circuit that tests the presence or absence of a failure in a semiconductor integrated circuit by applying a clock and using a scan circuit method. That is, the clock transmission wiring from the clock input cell to the basic cell via the buffer is fixedly provided and independent of other wiring.

[Operation 1] In the present invention, since the clock transmission wiring for the predetermined OFF or RANCH is fixedly provided, the clock and other signals are clearly separated and transmitted. Therefore, for the operation of the scan circuit, the clock and status signals of the FF can be smoothly transmitted. A designer can easily design so as to minimize the number of elements such as transistors and wiring networks related to clock transmission.

[Embodiment] FIG. 1 is a schematic top view of an LSI showing the configuration of a first embodiment of the present invention. FIG. 1 shows a mask slice type LS1, in which basic cells corresponding to input/output cells and logic gates are arranged in a grid pattern. In Figure 1, 10 is an LSI
Ill, 112-41-n is a human output cell, 12-1.12-2-12-n is a basic cell string,
13-1, 13-2- are basic cells, 14 is a clock buffer, and 15 is a clock transmission line.

The clock transmission line 15 is fixedly wired with aluminum or polysilicon, and may be made of the same material as that used to wire the basic cells, but the signals on the wires are different. A clock is externally applied to one of the output cells 11-2 which acts as a clock buffer 14. Then, from the buffer 14, the basic cell string 12-
1.12-2-, and then distributed to basic cells via transmission line 15-2.

A clock is applied to the logic unit cell 16 behind the main cell from its scan clock terminal. The clock buffer 14 and the transmission L5f15-1 may be arranged along the F side of the figure, and the logic unit cell 1
6 may also be placed elsewhere.

FIG. 2 is a diagram showing the configuration of another embodiment of the present invention. In FIG. 2, 144.14-2-44-n is a clock buffer arranged at the upper end of the basic cell column 12-1.12-2- to amplify and shape the clock. If there is a logical unit provided in the basic cell of each basic cell column, the signal is transmitted to that unit via transmission 'gA15-2. transmission line 1
As shown in 5-2 and 15-3, in a multilayered LSI, an aluminum wiring of 2N or more can be passed through the internal position of the basic cell.

[Effects of the Invention] As described above, according to the present invention, the clock used for failure detection by the scan circuit is appropriately transmitted, and the number of transmission buffers and wiring networks is reduced. It also makes the design easier for designers who logically design the failure detection section.
Since there is no increase in workload, LSI design man-hours are reduced and products can be manufactured more quickly.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of a first embodiment of the present invention, FIG. 2 is a diagram showing the configuration of the second embodiment, and FIG. 3 is a diagram showing the configuration of a conventional LSI test circuit. 0-LSl 11-1.11-2-Person output cell 12-[12-2-Basic cell row 14 Clock buffer

Claims (1)

[Scope of Claims] In a test circuit for a semiconductor integrated circuit that tests whether a semiconductor integrated circuit has a failure using a scan circuit method by applying a clock, a clock transmission wiring from a clock input cell to a basic cell via a buffer is provided. A test circuit for a semiconductor integrated circuit, characterized in that it is provided fixedly and independently of other wiring connecting integrated circuit cells.