JPH0258366A - semiconductor storage device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a technique that is particularly effective when applied to a semiconductor memory device, and includes, for example, a memory cell consisting of a series circuit of a capacitive element and a MISFET. The present invention relates to techniques that are effective for use in semiconductor memory devices.

[Conventional technique 1] A P-channel MO is used in the memory cell portion of a semiconductor memory device.
When using a 5FET, since the diffusion coefficient of boron (B) used as a P-type impurity to form a diffusion layer is large,
Since the lateral spread becomes large and the width of the isolation part needs to be widened, it is not possible to configure the cell surface to be small, and it is not possible to increase the surface concentration of boron, so the gate insulating film is made thinner. In this case, there is a problem that surface depletion during U Hu writing tends to increase.

Therefore, N-channel MO3FETs are currently used in the memory cell portion of semiconductor memory devices.

In addition, an N-channel MO5FET is used in the memory cell part,
Furthermore, a single semiconductor memory using a trench for isolation is also being considered. For semiconductor storage devices using trench isolation, see 1, for example, IEDM, 1984, pp. 244-24.
5 (IDEM 1984 p244-245).

[The problem that the invention tries to solve! ] However, a semiconductor memory device using an N-channel MO8FET in a memory cell portion has a problem in that soft errors are more likely to occur than a semiconductor memory device using a P-channel MO8FET. In addition, an N-channel MO8FET is installed in the memory cell section.
In a semiconductor memory device using P-type semiconductor, a highly doped P-type semiconductor region must be formed as a channel stopper.
As mentioned above, since the P-type impurity element has a large lateral deflection, there is a problem that the narrow channel effect is likely to occur due to the outflow of the P-type impurity element.

Such problems become more serious as semiconductor integrated circuits become smaller and smaller.

The present invention has been made in view of the above, and an object of the present invention is to provide a semiconductor memory device which can prevent the occurrence of soft errors and has a structure suitable for miniaturization and high integration.

The above and other objects and novel features of the present invention will become clear from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

That is, in a semiconductor memory device consisting of a series circuit of a MISFET and a capacitive element, the MISFET is composed of a P-channel M5FET, and the memory cell is isolated by a trench deeper than the lower capacitance pole. The capacitor upper layer electrode is made of polycrystalline silicon doped with a P-type impurity element.

[Operation: According to the above-mentioned means, MISF! ': Since T is composed of a P-channel M I S FET, when forming an insulating film (oxide film) in the trench, there is a possibility that positive charges may be accumulated at the interface between the silicon substrate and the insulating film. However, the accumulated charge acts in the direction of reducing leakage current, resulting in a decrease in leakage current. Also, M
Since the rSFET is composed of a P-channel MISFET, it has a structure that is resistant to alpha radiation.5 As a result, characteristic deterioration is less than that of an N-channel MISFET, and a highly reliable semiconductor memory device can therefore be realized.

In addition, since a trench deeper than the bottom electrode is formed and an insulating film is formed within the trench, a pile-up phenomenon occurs in the semiconductor region in contact with the bottom of the trench, and for example, a layer with a high concentration of phosphorus automatically forms. Due to the effect of forming the channel stopper, isolation characteristics can be obtained without performing ion implantation for the channel stopper, and furthermore, since there is no protrusion of the channel stopper, the narrow channel effect can be avoided.

Furthermore, since a trench deeper than the lower electrode is formed in the N-type silicon substrate, the horizontal expansion of the P-type impurity layer is suppressed by the trench. This will contribute to miniaturization and higher integration.

Furthermore, since the capacitor upper layer electrode is made of P-type polycrystalline silicon, it is possible to prevent a decrease in storage capacitance by reducing surface depletion caused by a difference in work function.

[Example] Hereinafter, an example of a semiconductor device according to the present invention will be described based on the drawings.

1 and 2 show a first embodiment of a semiconductor memory device according to the present invention, of which FIG. 2 shows a longitudinal cross-sectional view taken along the line ■-■ in FIG. There is.

In FIGS. 1 and 2, reference numeral 1 represents an N-type silicon substrate, in which a MOSFET and a capacitive element are formed in a region isolated by a trench 2 to form a series circuit. has been done.

Here, the MOSFET is composed of a P-channel MOSFET. That is, in this semiconductor memory device, P-type semiconductor regions 3, 3, which become the source and drain of a P-channel MOSFET, are formed on an N-type silicon substrate 1. In FIG. 1, reference numeral 4 represents an oxide film (second gate insulating film), and reference numeral 5 represents a gate electrode (second gate electrode).

Further, the capacitor lower layer electrode 6 constituting the capacitor element is composed of a P-type semiconductor region, and this P-type semiconductor region is a MOS
The FET and the capacitive element are connected to one side of the semiconductor region 3 so as to be connected in series. In addition, below the above capacity W
A capacitor upper layer electrode (first gate electrode) 8 is formed above the J electrode 6 with an oxide film (first gate insulating film) 7 interposed therebetween. This capacitor lower electrode 8 is made of polycrystalline silicon doped with a P-type impurity element at a high concentration.

Note that a field oxide film 9 is formed within the trench 2. Furthermore, a P-type impurity element is added to the semiconductor region 3°3 at a high concentration (I x 10''C3I-'' or more).

Next, a method for manufacturing the above semiconductor memory device will be explained.

First, an isolation trench 2 is formed in an N-type silicon substrate 1 doped with phosphorus. Next, trench 2
A thick field oxide film 9 is formed on the side and bottom surfaces of the substrate by thermal oxidation. Next, ions of boron (B), for example, are implanted into the region where the capacitor lower layer electrode 6 is to be formed. Next, the above capacity W! An oxide film (first gate insulating film) 7 is formed on the J electrode 6, and polycrystalline silicon is further deposited thereon. Then, ions of, for example, boron are implanted into the polycrystalline silicon. Thereafter, the capacitor upper layer electrode 8 is formed by processing the polycrystalline silicon. After that, M open membrane LOa,
After forming the oxide film 4 that will become the second gate insulating film, polycrystalline silicon that will become the second gate electrode 5 is deposited, and processing is performed after adding an impurity element to this polycrystalline silicon.6 After that, boron ion implantation is performed. P-type semiconductor region 3,3
A contact hole 11 is formed by depositing an interlayer insulating film such as PSG. Thereafter, an AQ wiring layer 12 is formed to obtain a DRAM memory cell. Note that in FIG. 1, the reference numeral 1o indicates the entire interlayer insulating film.

According to the semiconductor memory device configured as described above, the following effects can be obtained.

According to the semiconductor memory device, the MOSFET is composed of a P-channel MOSFET.

When forming the oxide film 9 in the trench 2, the silicon substrate 1
Even if positive charges are accumulated at the interface between the oxide film 9 and the oxide film 9, the MFI charges act in a direction to reduce the leakage current, resulting in a decrease in the leakage current. Also, M.O.
Since the SFET is composed of a P-channel MOSFET, the structure is strong against alpha rays. As a result, characteristic deterioration is less than that of an N-channel MOSFET, and a highly reliable semiconductor memory device can therefore be realized.

Furthermore, since the trench 2 is formed deeper than the lower electrode and the oxide film 9 is formed within the trench 2,
A pile-up phenomenon occurs in the semiconductor region in contact with the bottom of the trench 2, and a layer with a high concentration of phosphorus, for example, is automatically formed, making it possible to obtain isolation characteristics without performing ion implantation for a channel stopper. Moreover, there is no springing out of the channel stopper, so that the narrow channel effect can be avoided.

Furthermore, there is a lower part in the N-type silicon substrate 1! ! Since the trenches 2 are formed deeper than the poles, the lateral expansion of the P-type semiconductor region is suppressed by the trenches 2, which contributes to miniaturization and miniaturization of the memory cell portion and ultimately the semiconductor memory device. It turns out.

In addition, since the capacitor upper layer electrode 9 is made of P-type polycrystalline silicon, and in addition, the capacitor lower N'fl electrode 6 is also formed with a high concentration, it is possible to reduce surface depletion caused by work function differences. This action can prevent the storage capacity from decreasing.

Further, FIGS. 3 and 4 show second and third embodiments of the present invention.

Among these, the semiconductor memory device of the second embodiment has the trench filled with polycrystalline silicon 8.13 (however, an insulating film 14 is disposed between them), and the semiconductor memory device of the third embodiment has The trench 2 is filled with an insulating film 14. Incidentally, since a channel stopper implant is not required, the trench 2 is formed vertically in this embodiment.

This embodiment also provides the same effects as the first embodiment.

Further, FIGS. 5, 6(a) and 6(b) show the fourth and fjS5 embodiments of the present invention.

In the semiconductor memory device of the fourth embodiment, an N-type semiconductor region 16 is formed under the capacitive lower WI electrode 6, and this N-type semiconductor region 16 is formed under the capacitive lower WI electrode 6.
Ij:! The width of the depletion layer is reduced by the semiconductor region 16 and the N-well region formed in the substrate.

(a) and (b) show the N-channel MISFET and P-channel MISFET that constitute the peripheral circuit when trenches are used for isolation and when LOGOS is used, respectively.
A cross section of the SFET is shown.

Although the present invention has been specifically described above based on Examples, it goes without saying that the present invention is not limited to the above-mentioned Examples, and can be modified in various ways without departing from the gist thereof.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, in a semiconductor memory device consisting of a series circuit of a MISFET and a capacitive element, the MISFET is composed of a P-channel MISFET, and isolation of the memory cell is performed by a trench deeper than the pole under the capacitance.
An insulating film is formed on the inner surface of the trench, and the capacitor upper layer electrode is made of polycrystalline silicon doped with a P-type impurity element. Even if positive charges are accumulated in the structure, the accumulated charges act in the direction of reducing leakage current, resulting in a structure with less leakage current and resistance to alpha rays. As a result, the characteristic deterioration is N
The number of transistors is smaller than that of a channel MISFET, and therefore a highly reliable semiconductor memory device can be realized.

In addition, a pile-up phenomenon occurs in the semiconductor region in contact with the bottom of the trench, and a layer with a high concentration of phosphorus, for example, is automatically formed, making it possible to obtain isolation characteristics without performing ion implantation for a channel stopper. is possible,
Furthermore, since there is no springing out of the channel stopper, the narrow channel effect can be avoided.

Furthermore, by suppressing the lateral spread of the P-type impurity layer by the trench, it is possible to miniaturize the memory cell portion and even the electrodes of the semiconductor memory device, thereby reducing surface depletion due to work function differences. As a result, a decrease in storage capacity can be prevented. In addition, the effect becomes even greater when the capacitor lower layer electrode has a high concentration.

[Brief explanation of the drawing]

FIG. 1 is a longitudinal sectional view showing a first embodiment of a semiconductor memory device according to the present invention. FIG. 2 is a longitudinal cross-sectional view of the semiconductor memory device of FIG. 1 taken along line H--H. FIG. 3 is a sectional view showing a second embodiment of the semiconductor memory device according to the present invention. FIG. 4 is a vertical cross-sectional view showing a third embodiment of the semiconductor memory device according to the present invention, FIG. 5 is a cross-sectional view showing a fourth embodiment of the semiconductor memory device according to the present invention, and FIG. FIGS. 1A and 2B are cross-sectional views showing a peripheral circuit portion of a semiconductor memory device according to the present invention. 1...Silicon substrate-2...Trench, 3...
... P-type semiconductor region, 6 ... capacitor lower layer electrode (P-type semiconductor region), 7 ... oxide film, 8 ... capacitor upper/!
Electrode, 9...Oxide film, 12...AQI! lil
! line layer, 17...N-type semiconductor region, 18...P
type semiconductor area. Figure Figure Figure Figure Figure /Z 6th) (J

Claims (1)

[Claims] 1. A capacitor lower layer electrode made of a semiconductor region of the same conductivity type is connected to one of the semiconductor regions constituting the MISFET, and a capacitor upper layer electrode is disposed on the capacitor lower layer electrode via an insulating film. In a semiconductor memory device equipped with a memory cell section,
The MISFET is composed of a P-channel MISFET, the memory cell is isolated by a trench deeper than the capacitor lower layer electrode, an insulating film is formed on the inner surface of the trench, and the capacitor upper layer electrode is doped with a P-type impurity element. A semiconductor memory device characterized in that it is constructed of polycrystalline silicon. 2. The semiconductor memory device according to claim 1, wherein a P-type impurity element is added at a high concentration to the semiconductor region constituting the capacitor lower layer electrode.