JPH0258420A - Josephson gate circuit - Google Patents

Abstract

PURPOSE:To obtain an output voltage enough to satisfy the logical amplitude of respective types of the semiconductor circuit by increasing the number of the junction of respective steps of the cascade connected Josephson gate as the rear step is approached. CONSTITUTION:Josephson gates 10 and 11 are composed by connecting first and second branches 10a, 11a, 10b and 11b in the opposite direction in parallel, an input terminal is provided at the connecting point of the Josephson junction and the resistance of the first branches 10a and 11a. And an output terminal is provided at the connecting point of the Josephson junction and the resistance of the second branches 10b and 11b. The number of the Josephson junctions at a rear step 11 side of the cascade connected plural Josephson gates 10 and 11 is composed of the number larger than a front step 10. Consequently, the size of the output voltage of the Josephson gate of the arbitrary step becomes several times as much as the junction of the step for the input voltage of the step, and as the rear step is approached, the polyploidize extent of the output voltage becomes larger. Thus, by making the number of the cascade steps of the Josephson gate into the suitable number, the output voltage of the desired size can be obtained from the Josephson gate of the final step.

Description

[Detailed Description of the Invention] [Summary] Regarding Josephson gate circuits, an object of the present invention is to provide a Josephson gate circuit that can obtain an output voltage that fully satisfies the logic amplitude of various semiconductor circuits. A Josephson gate circuit with a gate connected to ml, the Josephson gate being configured by connecting first and second branches in parallel in opposite directions, each having a plurality of Josephson junctions and resistors connected in series. An input terminal is provided at the connection point between the Josephson junction of the first branch and the resistor, and an input terminal is provided at the connection point between the Josephson junction of the first branch and the resistor.
An output terminal is provided at the connection point between the Josephson junction of the branch and the resistor, and the input and output terminals are connected to form a Josephson gate circuit. The number of Josephson junctions is larger than that in the previous stage.

[Fields of use for graduation]

The present invention relates to a Josephson gate circuit, and particularly to a Josephson gate circuit that has a large gate output voltage and is suitable for interfacing with, for example, a semiconductor circuit.

Generally, the output voltage of a superconducting logic circuit using a Josephson element is determined by the magnitude of the gear gear energy of the superconducting material.
It is about V. Although this is preferable in terms of power consumption, when applying the output voltage to other logic circuits, the voltage is too small, so there are problems such as the inability to drive the load impedance sufficiently.

1. Prior Art] Therefore, the present applicant first developed the Josephson Gate (patent application filed in 1983).
2-171551).

Figure 3 is a diagram showing the recent Josephson date. In FIG. 3, the Josephson gate 1 includes n Josephson junctions Jll, J1□...J, , a first junction group 2 which is laminated sub-connected, and a first junction group 2 of this first junction group 2. n Josephson junctions Jul, JtZ-, the same number as the number of junctions
...The second junction group 3 in which JZn is connected in series and the resistors R+ and Rz constitute a bridge,
The critical current +C of each junction in the first junction group 2 and the second junction group 3 is approximately equal.

In such a configuration, the bias current 1 b flows almost equally through the first junction group 2 and the second junction group 3 which are in a superconducting state. That is, ib/2 flows into each of the first junction group 2 and the second junction group 3. Now, when T b , , /2 is smaller than the critical current TC of each junction, both the first junction group 2 and the second junction group 3 maintain a superconducting state.

When a positive current A (in the direction of arrow A in the figure) is applied to the input terminal 11n through the Josephson gate 1, the following operation occurs.

That is, 11. , flows from the first junction group 2 to the second junction group 3 via R2, and in this second junction group 3, currents I+, , +(I b/2) flow. Here, if the critical current Ic is set smaller than IIn+(Ib/2), some Josephson junctions of the second junction group 3 switch to the voltage state. As a result, the I b/
2 flows into the first junction group 2-, and this flowing current (i.e., (I b/2) + N b/2) =
Since I b) is sufficiently larger than the critical current of each junction of the first junction group 2, all the junctions of the first junction group 2 quickly switch to the voltage state, cutting off the IbO flow path. . As a result, Ib flows into the second junction group 3 and switches all the unswitched junctions of the second junction group 3.

Therefore, the output voltage V taken out from both ends of the second junction group 3. , a are the gear tooth energy Vg of each junction multiplied by the number of junctions (n), so a relatively large output voltage can be obtained and the driving ability of the load RL can be improved.

[Problem to be solved by the invention]

However, in the case of the earlier application, Josephson Gate,
The number n of junctions in the first junction group 2 and the second junction group 3 can only be set to about 10 at maximum even when considering the bias margin.For example, when the load is a semiconductor circuit, Logic amplitude of the circuit (1500 for CMO3
mV, 800mV for GaAs-based FETs, and 400mV for bipolar) cannot be obtained. That is, there was a problem in that it was not possible to interface with various semiconductor circuits.

SUMMARY OF THE INVENTION An object of the present invention is to provide a Josephson gate circuit that can obtain an output voltage that fully satisfies the logic amplitude of various semiconductor circuits.

[Means for Solving the Problems] In order to achieve the above object, a Josephson gate circuit according to the present invention is a Josephson gate circuit in which a plurality of Josephson gates are continuously connected, and the Josephson gate has a plurality of The first and second branches each having a Josephson junction and a resistor connected in series are connected in parallel in opposite directions, and an input terminal is provided at the connection point between the Josephson junction and the resistor of the first branch. An output terminal is provided at the connection point between the Josephson junction of the second branch and the resistor, and the input/output terminals are connected to form a Josephson gate circuit, and a plurality of cascaded Josephson gates are connected at the subsequent stage. The number of Josephson junctions on the side is greater than that on the previous stage.

[Effect]

In the present invention, the magnitude of the output voltage of the Josephson gate in any stage is the input voltage of that stage multiplied by the junction of that stage, and the degree of doubling of the output voltage increases as the stage progresses. .

Therefore, by appropriately selecting the number of cascaded Josephson gates, a desired level of output voltage can be obtained from the Josephson gate at the last stage, satisfying, for example, the logic amplitude of CMOS of 1500 mV.

Figure 1 is an explanatory diagram of the principle of the present invention. In Figure 1,
10.11 are Josephson gates connected in cascade; a two-stage cascade case is shown as an example. The Josephson gate 10 at the front stage includes a plurality (n) of Josephson junctions J1,
A first branch 1oa in which J, □...Jln and resistor R3 are connected in series, and a plurality of (n) Josephson junctions J2J2□...J2h and resistor R2
a second branch 1ob connected in series; the first branch], Oa and the second branch 10b are connected in parallel in opposite directions.

Further, the Josephson gate 11 in the latter stage has 1 (m, where m>n) Josephson junctions JJI! ,Jl3,J
A first branch 11a in which l4...Jl and a resistor R1' are connected in series, and a plurality (m) of Josephson junctions JZI, J2□, J23, Jl4..., 12
1 and a resistor R2' connected in series.
The first branch 11a and the second branch 11b are connected in parallel in opposite directions.

Note that RIH+ − and R+Nt are input resistances, Ro, and R+Nt, respectively.
Rb2 is a bias resistor, TR is a MOS as a load.
It is a transistor.

Now, it is assumed that an output voltage from a Josephson gate (not shown) having a gap voltage Vg is applied to the Josephson gate IO in the previous stage. In this case, all the junctions J2 and J2□ of the second branch 10b of the Josephson gate 10
...J2. , switches, the output voltage of the Josephson gate 10 becomes nXVg, and n times Vg is applied to the Josephson gate 11 at the subsequent stage. Then, when the second branch 11b of the Josephson gate 11 in the latter stage is switched, from this Josephson gate 1, Vg
A voltage whose magnitude is n times as large as n is applied to the MOS transistor TR.

In other words, the number of junctions in the '4?1bi Josephson gate increases as it approaches the later stage, and the upper limit of the number of junctions is determined by the magnitude of the signal from the previous stage. Therefore, in determining the magnitude of the output signal required for the final stage, it is only necessary to appropriately set the number of cascades and the degree of increase in the number of connections in each stage.

〔Example〕

Hereinafter, the present invention will be explained based on the drawings.

FIG. 2 is a diagram showing an embodiment of the Josephson gate circuit according to the present invention, and is an example of an interface with CMOS.

In FIG. 2, 20 is a Josephson gate circuit, 21
is a CMOS inverter circuit having a P-channel MOS transistor 21a and an N-channel MO5I-transistor 21b, and the Josephson date circuit 20 is as follows:
The first stage Josephson gate 22, the second stage Josephson gate 23, and the third stage Josephson gate 24 are connected in cascade.

The first stage Josephson gate 22 is a first junction group 2 in which eight Josephson junctions with a 9p field current of 1° are connected in series.
2a and the second junction group 22b, and a resistance R with a resistance value RO.
2□ and R2□. The second-stage Josephson gate 23 includes a first junction group 23a and a second junction group 23b, which are formed by connecting 64 Josephson junctions in series with a critical current of 2XI0, a resistor R1 with a resistance value of 4×RO, and Rtlb. It has The third stage Josephson gate 24 has a Josephson junction with a critical current of 4×IO.
It has 212 directly connected first junction group 24a and second junction group 24b, and resistors R241 and R2ab with a resistance value of 16XRo.

In addition, V D D % V 5 B is each CMO5OU
H4 logic side power supply and LO logic side power supply that determine the logic amplitude of T, RIHlZ, RIN! 1, R, N, and 4 are input resistances for each stage. In addition, VCC is a bias power supply, and the bias current of each stage is controlled by a bias setting resistor Rbtt.
It is set by Rbzs and Rbta. For example, the bias current 1bzz of the first-stage Josephson gate 22 is set by the following formula, Ib, □-2X (10)Xα ...... ■However,
α〈1 Bias current Ibz of the second stage Josephson gate 23
s is set by the following formula ■, I bzs=2X (2X r o)Xα ・・・・
...■ Bias current rb2 of the third stage Josephson gate 24. is set by the following formula (■).

Ibz4 = 2X (4Xro) The bias current flowing through each junction of the Josephson gates 24 in the first stage is less than the critical current (To in the first stage, 2To in the second stage, 4To in the third stage), so all the junctions are in a superconducting state. , Vg (for example, voltage corresponding to Nb gap energy of 3 mV)
When an input voltage Vi having a magnitude of Flowing into the second joint group 22b
switch at least one of the junctions. As a result, the bias current ([
b2□/2) is added to the first joint group 22a side, and the first
All the junctions of the junction group 22a are quickly switched to cut off the flow path of the bias current rb,t. For this reason, Ib
tz flows on the side of the second junction group 22b, causing all remaining unswitched junctions of the second junction group 22b to switch. As a result, the output voltage VOI from the first stage Josephson gate 22 is the same as that of the second junction group 2.
It is the value obtained by multiplying the gap energy of each junction of 2b by the number of junctions (8 in the first stage), and assuming that the above gap energy is equal to Vg of Vi, (V.1=■g×
8) is obtained.

The second stage Josephson gate 23 is this V. , the output voltage V of the second stage Josephson gate 23 is switched in the same manner as the first stage Josephson gate 22.
at becomes (Voz=V g X64).

And the third stage Josephson Gate 24 is this VO
The switch operates in response to W, and the output voltage VO3 of the third stage Josephson gate 24 is (Vox=VgX512)
becomes. Here, the first stage Josephson gate 22.2
The material of each junction of the Josephson gate 23 in the first stage and the Josephson gate 24 in the third stage is Nb/AI!
Assuming Ox/Nb, the gap energy per junction is approximately 3 mV, so VO3 is (V
os=3mVx 512#1500mV), CM
The logical amplitude (1500 mV) of O3 can be satisfied.

As described above, in this embodiment, a plurality of Josephson gates are connected in series, and the number of connections in each stage increases as the stage progresses. In other words, the upper limit of the number of connections in each stage is limited by the input signal voltage, but since the input signal voltage is increased sequentially in each stage, the number of connections in the subsequent stage can be easily increased to the desired number. be able to. Therefore, when applying the output voltage of the Josephson gate to CMO3, by setting the number of junctions in the final stage to, for example, 512, it is possible to obtain an output signal with an amplitude of 1500 mV required for CMO3, and the interface between the Josephson gate and CMO3 can be You can take it.

Furthermore, in this embodiment, not only the voltage of the output signal but also the amount of current is increased. In other words, the second stage Josephson gate 23 is twice the lo of the first stage Josephson gate 22.
is set to 4 times 10, so the CMOS inverter circuit 21 can be driven with a large output current corresponding to 4 times as much IO, which is preferable when driving a capacitive load such as 0MO3.

In this embodiment, CMO3 logic is used as an example, but the logic of other semiconductor circuits can be easily applied by appropriately selecting the number of connections in each stage.

〔Effect of the invention〕

According to the present invention, the number of junctions in each stage of Josephson gates connected in cascade is increased toward the later stage, so that when the signal voltage input to the gate of the first stage is outputted from the gate of the final stage, It can be enlarged and taken out depending on the number of gates connected in the final stage. Therefore, it is possible to obtain an output voltage sufficient to satisfy, for example, the logic amplitude of CMOS, and it is possible to interface with various semiconductor circuits.

[Brief explanation of the drawing]

FIG. 1 is a diagram illustrating the principle of the present invention, FIG. 2 is a block diagram showing an embodiment of a Josephson gate circuit according to the present invention, and FIG. 3 is a block diagram showing a conventional example. 10.11...Josephson Gate, 10a,
lla...first branch, 10b, llb...
...Second branch. Agent: Patent Attorney Gesada Ii −

Claims (1)

[Claims] A Josephson gate circuit in which a plurality of Josephson gates are connected in series, the Josephson gate having first and second branches each having a plurality of Josephson junctions and resistors connected in series. are connected in parallel in opposite directions, with an input terminal provided at the connection point between the Josephson junction and the resistor in the first branch, and an output terminal provided at the connection point between the Josephson junction and the resistor in the second branch. The input and output terminals are connected to form a Josephson gate circuit, and the number of Josephson junctions in the latter stage of the plurality of cascaded Josephson gates is greater than that in the former stage. Josephson gate circuit.