JPH0258793A - Dram controller - Google Patents

Abstract

PURPOSE:To reduce a refresh current when refreshing operations are performed by refreshing only one or plural memory banks based on previously given designating information. CONSTITUTION:A refresh request generation circuit RFTO 24 which generates a refresh request RFREQ in a cycle earlier than the ordinary refreshing interval, refresh request count circuit RBS 30 which counts the refresh request RFREQ in accordance with a preset setting value, and a selection logic circuit LC 31 which selects at least one memory bank out of plural memory banks in accordance with the count value of the count circuit RBS 30 upon receiving the refresh request RFREQ are provided.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention is directed to a DRAM (Dyn-an
ic Randon Access Hen+ory
) This invention relates to a DRAM control device that has a DRAM controller at its core that controls read/write and refresh operations for an array, and in particular improves the DRAM array refresh method.

<Prior Art> DRAMs are often used in memory systems that require large capacity, such as main frame memories, buffer memories, and image memories.

A typical example of a conventional DRAM system is shown in the block diagram of FIG.

The system shown in this figure is roughly divided into DMA sections I and D.
Consists of three main parts of MCM2O.

The DMA unit 1 is a DRAM array, and is composed of N memory banks #1 to #N, and each memory bank is composed of DRAM memory elements.

That is, the data width is 2 bits.

DMCM2O3 A DRAM controller that controls the DMA section 1, and includes the DMC21, refresh timer R
FT22, go to way 1/stay) to generation part WG23.

DMC21 is a DRAM controller, and receives, for example, a memory bank selection signal BS (1 bit), row address RA, column address CA, memory read/write access request signal MR1SIQ, from the CPU side.
Upon receiving read/write signal R/W, address AD (including row address RA and column address CA) is sent to only one memory bank selected by memory bank selection signal BS"C". , row address strobe signal n refresh timer RF'f'' 22 is transmitted at a constant interval of 1゛o (for example, To<15.6μs = 8m
s 1512 refresh cycle)
This is a timer that provides a refresh request RFREQ to 1.

The wait state generation unit WG23 indicates the end of the DRAM read/write operation, for example, CPLJII! + to inform the access request signal MREQ and DMC
Ready signal RT from 21) End signal END upon receiving Y
generate.

With this configuration, each memory bank receives an address signal AD, a row address strobe signal RASi, a column address strobe signal CAS i, and a write enable signal WE, and when W - "H", a read operation is performed. and read data DOUT (k bits) as data.
When WE- is “L”, write operation is performed and write data D IN (k pit) is sent to bus DB.
Import from bus DB. Normally, one of the memory banks for which row address strobe signal RASi and column address strobe signal CASi are enabled is accessed.

During a refresh (rewrite) operation, (a) RAS only refresh or (b) CAS before RAS refresh is performed according to the timing shown in FIG.

When performing a refresh, regardless of (a) RAS only refresh or (b) CAS before RAS refresh, regardless of the memory bank selection signal BS,
All row address, column address, and strobe signals (CASI to CASN) become valid, thereby causing memory banks #] to #N to be refreshed simultaneously.

Also, the ready signal R of the DMC21 during refresh operation
I) Y is "L". If the memory read/write request signal MREQ occurs during a refresh operation, memory access is made to wait until the refresh operation is completed, and the WG 23 terminates after confirming that the ready signal RDY has become "H". Outputs signal END.

<Problems to be Solved by the Invention> In the RAM control device as described above, all memory banks are refreshed at the same time during the refresh operation, so when the number of memory banks N increases, the Requires a high refresh current. Therefore, during the refresh operation, it is necessary to supply a much larger power supply current than that required for normal read/write operations, which is undesirable because it results in an increase in the output capacity of the power supply.

For example, if a 1 mecha-bit DRAM device is used and N=4. In the case of =32, the average power supply current is 2.7 A Hax during normal read/write operations, whereas the average power supply current is approximately 7.7 A Hax during refresh operations.

Furthermore, the flow of the refresh current generally tends to cause crosstalk noise and common impedance noise, making the entire circuit system unstable, which is undesirable.

Furthermore, if a manufacturer's standard device (for example, model 1431, etc.) is to be used as a DRAM controller, a layer problem arises because the specification of refreshing all memory banks at the same time cannot be changed.

The present invention addresses the above-mentioned problem, ie, attempts to suppress the large current generated during refresh, and aims to always realize stable operation of the memory system circuitry.

Means for Solving the Problems> The present invention provides a DRAM that performs read/write and refresh operations on a DRAM array consisting of a plurality of memory banks.
In a DRAM control device having a controller, a refresh request generating circuit generates a refresh request at a cycle faster than a normal refresh interval, a refresh request counting circuit has a set value set in advance and counts the refresh requests, and the refresh request and a selection logic circuit for receiving the refresh request counting circuit and selecting at least one memory bank from among the plurality of memory banks according to the count value of the refresh request counting circuit.
M control device.

The refresh request generation circuit has a switch means to which a predetermined value is externally set so that a refresh request is generated at 1/k of the normal refresh request interval time T in the case of the number of memory banks. Alternatively, the refresh request may be issued when the tally from the department is counted and the counted value reaches the predetermined value.

The refresh request counting circuit calculates the number of memory banks k
It is also possible to have a switch means for externally setting a setting value corresponding to , and to count the refresh requests and cyclically output the counted value according to the number of memory banks k.

The selection logic circuit inputs the count value from the refresh request counting circuit, performs a logical operation according to a preset logic configuration, and based on the result, selects at least one set of row address strobes provided from the DRAM controller. The column address strobe signal may be selectively output.

By the operation of the CPU 111, appropriate data is sequentially written to/read from the plurality of memory banks, and the number of matched data is set as the number of installed memory banks;
The refresh request generation circuit may set a predetermined value in an internal register based on this number of memory banks, and the refresh request counting circuit may set a set value in an internal register based on this number of memory banks. good.

Effect> The DRAM control device of the present invention generates a refresh request at a cycle earlier than usual, counts the refresh requests, selects at least one memory bank corresponding to the counted value, and performs a refresh operation. Execute.

<Embodiment> FIG. 1 is a diagram showing the configuration of a DRAM control device embodying the present invention.

The device of the present invention includes a DRAM controller r) Me 2
1 (same as the conventional one shown in FIG. 7), refresh request generation circuit (refresh timer) RFT024, refresh request counting circuit RBS30, selection logic circuit LC
Consists of 31.

Refresh request generation circuit (refresh timer R
The function of F'r'024 is the same as that of the conventional refresh timer RFT22 shown in FIG. W 1243 is added. R.F.C.
242 is a down counter, and switch means s W
Once the value Vs1 which is not set in 1243 is taken in, the tally clocks CL and K are counted, and when the contents become 0'', a refresh request RFREQ is given to the DMC21.

The refresh request count NRBS30 is RF T02
This is a counting circuit that counts refresh requests RF RE Q generated from 4, and is composed of a counter CN l' 301 and a switch means SW 2302. 0NT
For example, 301 is a down counter, and 5W2302
Once the value Vs2 set in
It counts, and when the content reaches 0'', it takes in the value Vs2 again and operates cyclically.For example, the value Vs2=2
If so, “′2′” ” i ”“O′”, °“2
”, “1”, “'o”, etc.,
This count value is given to the selection logic section LC in 2 bits.

The selection logic circuit LC31 is DM during read/write operations.
Row address strobe signal RAS from C21,
The column address strobe signal CAs is passed through as is and output to the DMA section (1) RAM element (not shown). During the refresh operation, several rows are made valid (“L”) according to the count value of the RBS 30. LC31 is, for example, a programmable logic
A device PLD (PLSi6, etc.) is used.

The operation of the DRAM control device of the present invention configured as described above will be explained next.

Here, the number of memory banks that can be implemented is N = 4, and the number of memory banks that are actually implemented is = 3 (1≦≦N)!
=2 bits (s=so, sl) as an example. Furthermore, GAS before RAS refresh will be handled as the refresh mode.

It is assumed that one memory bank is refreshed during the refresh operation. Therefore, the logic shown in FIG. 2 is programmed into the LC 31 for normal read/write and refresh operations.

In addition, SW 1243 of RF T 024 has a time T corresponding to approximately 1/3 of the conventional refresh request interval time 1o (1/k in the case of the number of memory banks).
Set the value Vsl (T/l; t is the clock CLK period) required to generate the RBS30 SW
In 2302, the value "2" is set as the value Vs2.

Next, using the time chart of FIG. 3, the cases of (1) memory read/write cycle and (2) memory refresh cycle will be explained separately.

(1) Read/write cycle memory access request M Rt'', Q becomes valid 'H path, address signal MAT) (signal AI), RA, CA
), the read/write signal R/W is DMC21
is input. The DMC 21 determines the priority of the read/write 1 cycle based on the access request signal MREQ and the refresh cycle based on the refresh request signal RFREQ. If a refresh is not being executed, the ready signal RDY of the DMC 21 starts a read/write cycle at °'H'', and if a refresh is being executed, read/write reception is delayed.

The DMC21 outputs the address AD, write enable signal WE, and the corresponding memory selected by the bank selection signal BS.
Row address strobe signal RASi corresponding to bank #i (i=1.2.3).

Column address strobe signal C port] only "'
L, ” output as level.

LC31 knows that the read/write cycle has started due to the ready signal RDY"11", and 0MC21
Row address strobe signal RASi
"I-5'", column address strobe signal CA
S i "I-," signal IRASi ICASj
and the corresponding signal O according to the logic table in Figure 2.
RA S i and OCA S i are set to ``progress'' level in sequence.

On the other hand, there is an address AI on the RAM side (not shown).
), the write enable signal WE is input, and the row address strobe signal RASi and column address strobe signal CASi are applied to the corresponding memory bank #i at the ``L'' level, and a read/write operation is executed. In the operation example of the time chart in Figure 3, 1-1 (bank #1
).

The WG 23 detects the access request signal MREQ "H'" and the ready signal RDY "H", waits for a certain period of time (a time corresponding to the memory access time), and then outputs the end signal E.
N I) is output.

This completes the memory read/write cycle.

(2) Refresh cycle RI? 'I' When the refresh request signal RF REQ from 02/l becomes valid ")I '", the signal RF
RE Q is CN T 3 in 0MC21 and RBS30
01.

1) In the MC21, the refresh cycle by the refresh request signal RFREQ and the access request signal MRE
Determine the priority order of read/write to 1 cycle by Q. If the access request signal M REQ is "H" at the time the refresh request RF REQ becomes valid, reception of the refresh request 1 is delayed until the access request signal M REQ becomes "L". Access request signal M
If REQ is "L'", the refresh operation starts immediately. When a refresh cycle starts, DMC
The ready signal RJ) Y of 21 becomes 'L'.

At this time, the DMC 21 sends row address strobe signals RASI to RAS4. Column address strobe signals CAS1 to CAS4 are all "L". CN'r301 in RBS30 counts down the refresh request signal RFREQ by +1 and outputs the result! bit (/=2, that is, in FIG.
“L”, s O = count down to “H”)
It is output to the LC31 as

L, C31 knows that the refresh cycle has started from the ready signal RDY"'L", and according to the logic table shown in FIG.
Memory bank #i (
In this example, memory bank #2) is selected and the corresponding signals 0RAS i and 0CAS 1 (i=2) are output as "L".

On the DRAM side, row address strobe signal RAS2. is applied only to memory bank #2. Column address strobe signal CAS2 is applied to start the refresh operation.

When the refresh operation is completed, the 0MC21 sets the ready signal RDY to "17".

This completes the refresh operation for memory bank #2.

In the explanation of the example in item 1, the CAS-before-RAS refresh mode was used as an example of the refresh mode, but the RAS-only refresh mode can also be handled in the same way.

Further, in the above example, the logic of the LC 31 may be configured to select only one memory bank at the time of refresh, or may be configured to refresh several banks at the same time. At this time, the setting of the SW 1243 in the RFTO 24 is changed to a correspondingly larger value so that more refresh requests are generated. For example, you can use two memory banks at the same time (Bank #1.#2 at the same time or Bank #3
．． The table in FIG. 4 shows the logical configuration of the LC 31 in the case of refresh #4 simultaneously).

In the embodiment shown in FIG.
Depending on the number of banks k (]≦≦N), RFT024. R
Switch values are manually set for SW1243 and 5W2302 in the BS30, but when the number of memory banks differs depending on the system being constructed, it is troublesome to manually set the optimal value each time, and it is also prone to errors. This is not desirable as there is a risk of causing settings.

In such a case, instead of 5W1243.5W2302, the register REG1244 is added to the refresh request generation circuit RFTO24 as shown in FIGS. 5(a) and (b).
, the register REG is added to the refresh request counting circuit RBS.
2303 is provided, an operating program of a flowchart as shown in FIG. 6 is set on the CPU side, and the CPU
The value Vs1. Vs2 to register REG1244,
It may be set in REG2302.

That is, let the maximum number of memory banks that can be implemented be N, and (N-
1) is set to REGl, 244, and the number of memory banks N
A value necessary for generating the refresh request interval time in the case of 1 is set in RE G 2303.

Then, write/read appropriate data in the installed memory banks in sequence, and calculate the number (j-
1> is the number of memory banks actually implemented, and the value (,j-2) is set in REG2303 as the value Vs2.6 On the other hand, the refresh request interval time according to the number of memory banks (j-2) is The value Vsl required for generation is reset to REG1244.

In this way, the value Vs1. By determining V, s2, it is possible to make a pair (16) for various systems.

In the example of FIG. 1, the logic selection circuit LC31 and the refresh request counting circuit RBS30 are configured separately and added.
It may be incorporated into the DR/AM controller DMC21.

<Effects of the Invention> According to the DRAM control device of the present invention, the following effects can be obtained.

In a DRAM array consisting of multiple memory banks,
When performing a refresh operation, only one or more memory banks are refreshed based on specified information given in advance, so the refresh current can be significantly reduced compared to when all memory banks are refreshed at the same time. can be reduced.

In addition, if the number of memory banks actually implemented is small compared to the number of memory banks that can be implemented, the refresh request interval time is set according to the number of memory banks, so the refresh request interval time is fixed. Compared to conventional devices, unnecessary refresh operations can be omitted, and a decrease in processing efficiency of memory read/write operations can be prevented.

Furthermore, it is possible to configure the system so that values corresponding to the actual number of memory banks and refresh request interval times can be automatically set in the registers by a program.
Even if the number of memory banks varies depending on the system, there is no need to rely on manual settings.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a DRAM control device embodying the present invention, FIG. 2 is a table showing the logic configuration programmed in the selection logic circuit LC31 in the device of the present invention, and FIG. A time chart showing the operation,
FIG. 4 is a table showing other logic configurations programmed into the selection logic circuit LC31 in the device of the present invention, and FIG.
) is the refresh request generation circuit RF in the device of the present invention.
Another configuration example of T' 024, FIG. 5(b) is another configuration example of the refresh request counting circuit RBS30 of the device of the present invention, and FIG. 6 uses the configuration of FIGS. 5(a>, (b)). FIG. 7 is a block diagram showing the conventional DRAM control device, and FIG. 8 (a)
) and (b) are time charts showing refresh operations in a conventional device. 1...DMA section, 2...DMC section, 21...DR
AM controller DMC122...Refresh timer RF T, 23...Wait state generation section W
G, 24...Refresh request generation circuit RP 'r'
05241... Clock generation section 0C1 242... Down counter RF C2243...
Switch means SWI, 244...Register REGI, 30...Refresh request counting circuit RBS, 31...
- Selection logic circuit LC1 301... Town counter CNT, 302... Switch means SW2. 303...Register RE G 2nd degree) 11'7 Figure

Claims (5)

[Claims] (1) In a DRAM control device having a DRAM controller that reads/writes and refreshes a DRAM array consisting of multiple memory banks, a refresh request generation circuit that generates a refresh request at a faster cycle than a normal refresh interval; a refresh request counting circuit having a set value set in advance and counting the refresh requests; and at least one memory bank among the plurality of memory banks responsive to the count value of the refresh request counting circuit upon receiving the refresh request. A selection logic circuit for selecting a DRAM control device. (2) When the number of memory banks is k, the refresh request generation circuit is configured to
A switch means is provided with a predetermined value externally set so that a refresh request is generated at /k, and the refresh request is issued when the counted value reaches the predetermined value by counting the clocks from the clock generator. Claims characterized (
1) DRAM control device described. (3) The refresh request counting circuit has a switch means to which a set value corresponding to the number k of memory banks is externally set, and counts the refresh requests to count the memory banks.
2. The DRAM control device according to claim 1, wherein the count value is output cyclically according to the number of banks k. (4) The selection logic circuit inputs the count value from the refresh request counting circuit, performs a logical operation according to a preset logic configuration, and uses the result to select the DRAM.
2. The DRAM control device according to claim 1, wherein the DRAM control device selectively outputs at least one set of row address strobe signals and column address strobe signals given from the controller. (5) By the operation of the CPU side, appropriate data is sequentially written/read in the plurality of memory banks, and the number of matched data is set as the number of installed memory banks, and the refresh request generation circuit - Claim (1) characterized in that a predetermined value is set in an internal register based on the number of banks, and the refresh request counting circuit sets a set value in the internal register based on the number of memory banks.
) DRAM control device described.