JPH0258800U - - Google Patents
Info
- Publication number
- JPH0258800U JPH0258800U JP1988138241U JP13824188U JPH0258800U JP H0258800 U JPH0258800 U JP H0258800U JP 1988138241 U JP1988138241 U JP 1988138241U JP 13824188 U JP13824188 U JP 13824188U JP H0258800 U JPH0258800 U JP H0258800U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- voice synthesis
- type flip
- operation buttons
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 238000003786 synthesis reaction Methods 0.000 claims description 5
- 230000010355 oscillation Effects 0.000 claims description 3
- 244000145845 chattering Species 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 3
- 230000002265 prevention Effects 0.000 description 1
Description
第１図はこの考案の一実施例を示す回路構成図
、第２図は第１図の動作説明に供するための図、
第３図は従来装置の一例を示す回路構成図である
。
２はアドレス指定回路、３は音声合成回路、１
０１〜１０６は操作釦、１１はチヤタリング防止
回路、１１１〜１１６はＤ型フリツプフロツプ回
路、１２は基準発振回路、１３，１５は分周回路
である。
Fig. 1 is a circuit configuration diagram showing an embodiment of this invention, Fig. 2 is a diagram for explaining the operation of Fig. 1,
FIG. 3 is a circuit configuration diagram showing an example of a conventional device. 2 is an addressing circuit, 3 is a speech synthesis circuit, 1
0 1 to 10 6 are operation buttons, 11 is a chattering prevention circuit, 11 1 to 11 6 are D-type flip-flop circuits, 12 is a reference oscillation circuit, and 13 and 15 are frequency dividing circuits.
Claims (1)
報に応じてアドレス信号を発生するアドレス指定
回路と、該アドレス指定回路からのアドレス信号
に基づいて音声合成信号を発生する音声合成回路
とを備えた音声合成装置において、 上記複数の操作釦に対応して設けられたチヤタ
リング防止用の複数のＤ型フリツプフロツプ回路
と、 該複数のＤ型フリツプフロツプ回路にクロツク
信号を供給する共通の基準発振回路と、 を備え、上記Ｄ型フリツプフロツプ回路の出力を
上記アドレス指定回路に供給するようにしたこと
を特徴とする音声合成装置。[Claims for Utility Model Registration] A plurality of operation buttons, an address designation circuit that generates an address signal according to operation information from the plurality of operation buttons, and a voice synthesis signal based on the address signal from the address designation circuit. A voice synthesis device is provided with a voice synthesis circuit that generates a voice synthesis circuit, a plurality of D-type flip-flop circuits for preventing chattering provided corresponding to the plurality of operation buttons, and a clock signal to the plurality of D-type flip-flop circuits. a common reference oscillation circuit for supplying a common reference oscillation circuit, and an output of the D-type flip-flop circuit is supplied to the addressing circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988138241U JPH0258800U (en) | 1988-10-24 | 1988-10-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988138241U JPH0258800U (en) | 1988-10-24 | 1988-10-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0258800U true JPH0258800U (en) | 1990-04-26 |
Family
ID=31400397
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988138241U Pending JPH0258800U (en) | 1988-10-24 | 1988-10-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0258800U (en) |
-
1988
- 1988-10-24 JP JP1988138241U patent/JPH0258800U/ja active Pending
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