JPH0446725U

JPH0446725U -

Info

Publication number: JPH0446725U
Application number: JP8938190U
Authority: JP
Priority date: 1990-08-27
Filing date: 1990-08-27
Publication date: 1992-04-21

Description

[Brief explanation of the drawing]

第１図はこの考案による1/m出力合成回路図、
第２図は第１図のｍ＝３のときの実施例の回路図
、第３図は第２図のタイムチヤート、第４図は第
１図のｍ＝５のときの実施例の回路図、第５図は
第４図のタイムチヤート、第６図は第１図のｍ＝
７のときの実施例の回路図、第７図は第６図のタ
イムチヤート、第８図は従来技術による分周回路
の回路図、第９図は第８図のタイムチヤートであ
る。１……クロツク発生器、２……ＥＸ−ＯＲ（排
他的論理和回路）、３……２^ｎ分周回路、４……
反転パルス合成回路。 Figure 1 is a 1/m output synthesis circuit diagram based on this invention.
Figure 2 is a circuit diagram of the embodiment when m = 3 in Figure 1, Figure 3 is a time chart of Figure 2, and Figure 4 is a circuit diagram of the embodiment when m = 5 in Figure 1. , Figure 5 is the time chart of Figure 4, and Figure 6 is the time chart of Figure 1.
7 is a time chart of FIG. 6, FIG. 8 is a circuit diagram of a conventional frequency dividing circuit, and FIG. 9 is a time chart of FIG. 8. 1...Clock generator, 2...EX-OR (exclusive OR circuit), 3... ²ⁿ frequency divider circuit, 4...
Inverted pulse synthesis circuit.

Claims

[Claims for Utility Model Registration] A clock generator 1 that generates a clock 1A, an exclusive OR circuit 2 whose first input is the clock 1A, and a circuit 2 whose input is the output 2A of the exclusive OR circuit 2.
ⁿ frequency divider circuit 3, and an exclusive OR circuit 2 from the output of the ²ⁿ frequency divider circuit 3.
1/m output synthesis circuit from a frequency dividing circuit, comprising: an inverted pulse synthesis circuit 4 for synthesizing a second input of the frequency dividing circuit.