JPH0258839A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To enable a semiconductor device to be highly integrated by a method wherein respective gate regions of a plurality of JFETs are disposed in a array in the perpendicular direction with one another while a source region and a drain region are arranged on both upper and lower sides of the gate regions. CONSTITUTION:A plurality of JFETs 401, 402... are junctioned with one another in series by disposing the respective gate regions 411, 412... in an array in the perpendicular direction to a substrate 42. A source region 43 and a drain region 44 are arranged on upper and lower both sides of the gate regions 411, 412. During the manufacturing process, the gate regions 411, 412... of one JFET are formed in the substrate 42 immediately below a mask 45 by ion-implantation using the mask 45 provided with an opening 45a and simultaneously the source region 43 is formed in the substrate 42 immediately below the opening 45a. Through these procedures, a smaller space suffices compared with that disposed in an array in the lateral direction, thus enabling the semiconductor to be highly integrated.

Description

[Detailed description of the invention] [Summary] Junction field effect transistor (hereinafter referred to as JFET)
In order to enable high integration of semiconductor devices configured with JFETs, a plurality of JFETs are connected in series by arranging their gate regions perpendicularly to the substrate, and the source The gate region and the drain region are arranged on both sides of the upper and lower sides of the gate region, and during manufacturing, a mask with an opening is used to form the gate region of one JFET in the substrate directly under the mask by ion implantation. , forming a gate region of another JFET in the substrate directly under the opening, and forming a source ramp in the substrate directly under the opening by ion implantation using the mask.

(Industrial Application Field) The present invention relates to a semiconductor device configured with a JFET.

Traditionally, high integration and high speed have been important issues for ICs such as logical operation circuits, and in recent years, especially as computer systems have come to be used in various places and applications, the amount of information they handle has increased. Demand for higher speeds is increasing. The logical operation elements are composed of MOS transistors, bipolar transistors, etc., and it is necessary to miniaturize both of these elements in order to increase the speed.

However, in current RAMs using MOS transistors or bipolar transistors, the minimum dimension is 0.7 μm.
Therefore, it will be difficult to advance microfabrication technology at the mass production level in the future. In this case, there are devices such as Josephson devices and high electron mobility transistors (HEMT), but these are not suitable for mass production.

Therefore, there is a need for a logic operation element (ie, a JFET) that is faster than a MOS I-transistor or a bipolar transistor and can be mass-produced.

[Conventional technology]

Conventionally, when constructing a circuit such as an inverter or a NOR gate using JFETs, a plurality of JFETs are arranged horizontally in parallel on a substrate. In this case, the JFET is generally
Since the carrier moves in the bulk, MOS
It has a higher effective mobility than a transistor and can be operated at high speed. The electron mobility of a MOS transistor is 600
Cffl/V-sec, whereas the electron mobility of JFET is 1600 cm/■·sec.

As shown in FIG. 4, a JFET generally has an n+ diffusion layer formed on the upper surface of an n-type substrate 1, including a drain 2, a source 3, and a drain 2, a source 3, and so on. A first gate 4 of a P+ diffusion layer is provided, and a P+ diffusion layer is provided on the underside of the substrate 1.
It has a horizontal configuration in which a + second gate 5 is provided. When constructing a NOR gate as shown in FIG. 5 using this JFET, for example, two JFETs are arranged side by side in the horizontal direction as shown in FIG.

In FIG. 6, 10 is a first JFET, and 11 is a second JFET, which are arranged in parallel to the n-type substrate 12.

13 is the source, 14 is the drain, 151 is the first JFET
10 is the gate of the second JFET 11, and 152 is the gate of the second JFET 11. 16 is the gate of the first JFETIO and the second JFETll. 16 is the first JFET10 and the second JFET11
17 is a common gate. Here, if a voltage is applied to at least one of the gates 151 and 152 and a depletion layer is created in the P+ diffusion layer below it, current will no longer flow from the source 13 to the drain 14.
On the other hand, current flows from the source 13 to the drain 14 only when no voltage is applied to both gates 151 and 152 and no depletion layer is generated in the P+ diffusion layer below each gate. In other words,
This thing constitutes Noah Gate.

(Problems to be Solved by the Invention) The conventional device shown in FIG. 6 is a horizontal type J as shown in FIG.
Since two FETs are arranged side by side in the horizontal direction, the overall area must be large, making it unsuitable for high integration.

An object of the present invention is to provide a semiconductor device that can be highly integrated and a method for manufacturing the same.

(Means for Solving the Problem) FIG. 1 shows a diagram of the principle of the present invention. In the same figure (A), 40+
, 402 , . . . are a plurality of JFETs, and their respective gate regions 411 , 412 , . 43
is a source region, 44 is a drain region, and gate region 411
, 412 are arranged on both sides of the upper and lower sides. In manufacturing the same, as shown in FIG. 4B, a gate region 41 of one JFET is formed in the substrate (42) directly under the mask 45 by ion implantation using a mask 45 provided with an opening 45a, and at the same time, A gate region 1iit412. of another JFET is formed in the substrate 42 directly under the opening 45a. The opening 45 is formed by ion implantation using the mask 45.
The step of forming a source region 43 in the substrate 42 directly under the region a is included.

[Effect]

The present invention has a configuration in which a plurality of JFETs 40+, 402, . This allows for a smaller area as a whole compared to those arranged side by side in the horizontal direction, making it possible to achieve high integration.

〔Example〕

FIG. 2 shows a manufacturing process diagram of one embodiment of the device of the present invention (Noah Gate). In the same figure (A>, an n-type silicon substrate 20 (10Ωcffi (NSub ~ 5×10” crn
−” )) 1X 10 with an energy of 5 MeV on the entire surface
The drain 21 is formed by ion-implanting phosphorus (P) at a concentration of " an-2. At this time, Rp (projection range) is relatively deep, approximately 5 μm. Next, in the same figure <8) A tungsten (W) mask 22 (film thickness 1 μff1) with an opening 22a provided on the surface of the substrate 20 is formed using a resistor or the like, and with an energy of 2.5 M e V,
Boron (B) is ion-implanted at a concentration of 5×10 13 CjI. In this case, since tungsten has an Rp that is approximately 1/2 that of silicon, there is approximately 1.
The gates 23a and 23 of the first J FET are placed at a depth of 5 μm.
b is formed, while approximately 3.5μ is formed directly under the opening 22a.
A gate 24 of the second FET is formed at a depth of m. Note that the ion implantation is performed at a predetermined angle with respect to the normal direction of the substrate 20, and the boron implantation region is formed in a region wider than the opening 22a (Ge 1-23a, 23b). The gate 24 may also be formed by implantation.

Next, in the same figure (B), using the mask 22 as it is, with an energy of 70kll13V, lX101St-1
Source 2 is formed by ion-implanting arsenic <As) at a concentration of
form 5. Rp at this time is approximately 0.2 μm. Next, the mask 22 is removed and annealing is performed (900° C., 20m+n) to activate the implanted impurities.

N2 atmosphere).

Subsequently, in the same figure (C), PSG is applied to the surface of the substrate 20.
A mask 26 (approx. 3μl 1l) is formed to open the opening 26.
trenches 27a and 27b of about 6t1m are formed in the substrate 20. Next, using this mask 26, at an energy of 40 keV, 1×10 13 CIR″2
The element isolation impurity region 28a is implanted with boron at a concentration of
, 28b.

Next, in the same figure (D), trench 27a.

Insulating films 29a and 29b of silicon oxide are buried in 27b, the insulating film on the surface is removed, and a protective film 30 such as PSG is formed on the surface.
form.

Next, in the same figure (E), contact holes 31a and 3 for gates 23a and 23b are formed in the mask 30 and the substrate 20.
1b, contact holes 32a, 32 for drain 21
b, contact holes 33a, 33b for gate 24,
A contact ball 31c for the source 25 is formed, and then, in FIG.
a, 35, gate electrodes 36a, 36b,' of the second FET;
/- source electrode 37. Drain electrodes 38a and 38b are formed, and the manufacturing of the device of the present invention is completed. Figure 3 shows a plan view, in which the same parts as in Figure 2 are given the same numbers.
(Figure (F) shows a sectional view taken along the line ■-■ in Figure 3).

In this way, as is clear from FIG. 2, the device of the present invention serves as one input terminal of the first FET (the gates are 23a and 23b, and the gate electrode 35a constitutes 7 gates).
and a second FET (the gate is 24, the gate electrode 36a
are the other input terminals constituting the NOR gate) are arranged in parallel in the vertical direction with respect to the substrate 20. Therefore, compared to the conventional devices arranged side by side in the horizontal direction as shown in FIG. 6, the overall area is smaller and higher integration is possible.

Next, the operation of the device of the present invention will be explained. Figure 2 (F
), the gate electrodes 35a, 35b of the first FET
, the gate electrode 36a of the second FET.

When no voltage is applied to both gates 23a and 36b (that is, the two input terminals of the NOR gate are at L level), the gates 23a and
A depletion layer is not formed around 23b and 24, so that the current from source electrode 37 reaches drain 21 via substrate 20 and is taken out from train electrodes ff138a and 38b (output on state).

On the other hand, for example, the gate electrode 35a of the first FET.

For example, when a voltage of -5V is applied to 35b (that is,
When one input terminal of the NOR gate is at H level), a depletion layer is formed around the gates 23a and 23b, so that the source electrode 37 is The current from the drain electrode 38a is blocked by this depletion layer and does not reach the drain 21.

No current is taken out from 38b (output off state). Similarly, when a voltage of, for example, -5V is applied to the gate electrodes 36a and 36b of the second FET (that is, the other input terminal of the NOR gate is at H level), a depletion layer is formed around the gate 24. Accordingly, the electrode 35a of the first FET.

Source electrode 3 regardless of whether the voltage 35b is applied or not.
The current from the drain electrode 7 is blocked by this depletion layer and does not reach the drain 21, and no current is taken out from the drain electrodes 38a and 38b (output off state).

Gate electrodes 35a, 35b of the first FET and the second FE
A state in which voltage is applied to both gate electrodes 36a and 36b of T (that is, two input terminals of the NOR gate are at H level)
Now, gates 23a and 23b.

A depletion layer is formed around 24, and no current is extracted (output off state). The above is the operation of Noah Gate.

Although the above embodiment has a configuration using two JFETs, the present invention is not limited to this, and can be similarly applied to a configuration using three or more JFETs.

In this case, sets of gates 23a, 23b and gate 24 are repeatedly arranged in parallel on the substrate 20, and sources and drains are arranged on both upper and lower sides thereof.

Furthermore, although the above embodiment has a configuration in which a negative voltage is applied to a P-type gate, an n-type gate may be formed and a positive voltage applied thereto.

〔Effect of the invention〕

As described above, according to the present invention, compared to the conventional device in which a plurality of JFETs are arranged side by side in the horizontal direction and bonded together, the overall area is smaller and higher integration is possible.

[Brief explanation of the drawing]

Figure 1 is a diagram of the principle of the present invention, Figure 2 is a manufacturing process diagram of an embodiment of the present invention, Figure 3 is a plan view of the device of the present invention, Figure 4 is a sectional view of a conventional JFET, and Figure 5. is the circuit diagram of Noah gate using J FET, No. 6
The figure is a cross-sectional view of a conventional Noah gate. 38a and 38b are drain electrodes, 40+ and 402 are a plurality of JFETs 1, 411 is a gate of this one JFET, 412 is a gate of another JFET, and 42 is a substrate. In the figure, 20 is a silicon substrate, 21.44 is a drain, 22.45 is a mask, 22a and 45a are openings, 23a and 23b are IIJFET (7) gates, 24 is a gate of the second JFET, 25.43 is a source, 28a, 28b are element isolation impurity regions, 29a, 29
b is an insulating film, 30 is a protective layer, 35a and 35b are gate electrodes of the first JFET, 36a,
36b is the gate electrode of the second JFETf7), 37 is the source electrode,

Claims (3)

[Claims] (1) Multiple junction field effect transistors (40_1,
40_2,...) to their respective gate regions (41_1,...)
41_2,...) are vertically arranged in parallel to the substrate (42) and bonded in series, and the source region (43) and drain region (44) are connected to both upper and lower sides of the gate region (41_1, 41_2,...). A semiconductor device characterized by being arranged in a. (2) Multiple junction field effect transistors (40_1,
40_2,...) to their respective gate regions (41_1,...)
41_2,...) are vertically arranged in parallel to the substrate (42) and bonded in series, and the source region (43) and drain region (44) are connected to both upper and lower sides of the gate region (41_1, 41_2,...). When manufacturing a semiconductor device arranged in a mask (45) provided with an opening (45a),
By ion implantation, the substrate (42) directly under the mask (45)
The gate region of one junction field effect transistor (4
1_1,...), and at the same time, the opening (45a)
A process of forming gate regions (41_2,...) of other junction field effect transistors in the substrate (42) directly below, and ion implantation using the mask (45) to remove the substrate directly below the opening (45a). (42) inside the source area (43
) A method for manufacturing a semiconductor device, the method comprising: forming a semiconductor device. (3) Multiple junction field effect transistors (40_1,
40_2,...) to their respective gate regions (41_1,...)
41_2,...) are vertically arranged in parallel to the substrate (42) and bonded in series, and the source region (43) and drain region (44) are connected to both upper and lower sides of the gate region (41_1, 41_2,...). When manufacturing a semiconductor device arranged in a mask (45) provided with an opening (45a),
The substrate (42) directly under the mask (45) is implanted with ions at a predetermined angle with respect to the normal direction of the substrate (42).
2) forming a gate region (41_1,...) of one junction field effect transistor in the substrate (42) directly under the opening (45a) by ion implantation using the mask (45); A step of forming gate regions (41_2,...) of other junction field effect transistors, and a step of forming source regions in the substrate (42) directly under the opening (45a) by ion implantation using the mask (45). (4
3) A method for manufacturing a semiconductor device, comprising the step of forming.