JPH0259399A - Semiconductor device for ic card - Google Patents

Semiconductor device for ic card

Info

Publication number
JPH0259399A
JPH0259399A JP63209537A JP20953788A JPH0259399A JP H0259399 A JPH0259399 A JP H0259399A JP 63209537 A JP63209537 A JP 63209537A JP 20953788 A JP20953788 A JP 20953788A JP H0259399 A JPH0259399 A JP H0259399A
Authority
JP
Japan
Prior art keywords
chip
die
module
card
modulus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63209537A
Other languages
Japanese (ja)
Inventor
Sunao Fukutake
素直 福武
Yoshito Tanaka
義人 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Maxell Ltd
Original Assignee
Hitachi Maxell Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Maxell Ltd filed Critical Hitachi Maxell Ltd
Priority to JP63209537A priority Critical patent/JPH0259399A/en
Publication of JPH0259399A publication Critical patent/JPH0259399A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/851Dispositions of multiple connectors or interconnections
    • H10W72/874On different surfaces
    • H10W72/884Die-attach connectors and bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Credit Cards Or The Like (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To alleviate residual stress in an IC chip and enhance yield of production by using a material having a Young's modulus of not more than a specified value as a die-bonding material for an IC chip of a semiconductor device comprising an IC module mounted on a card. CONSTITUTION:As a die-bonding material 11, a resin having a Young's modulus of not more than 100kgf/mm<2> is used, whereby a residual stress in an IC chip 10 upon fabrication of an IC module 3 is markedly alleviated. That is, when the die-bonding material having a low Young's modulus and being comparatively soft is used, the residual stress on the face side of the IC chip arising from heat shrinkage of the die-bonding material 11 is greatly reduced. Also, it is possible to enhance the breaking limit of the IC chip upon exertion of an external force on an IC card fabricated by use of the IC module.

Description

【発明の詳細な説明】 [産業上の利用分野コ 本発明はICカード用の半導体装置に係り、更に詳しく
は、カード塔載用のChip on Board型IC
モジュールに関する。
[Detailed Description of the Invention] [Industrial Field of Application] The present invention relates to a semiconductor device for an IC card, and more specifically, to a chip-on-board type IC for mounting on a card.
Regarding modules.

[従来の技術] ICカードは、コンパクトでありながら記憶容量が大き
く情報の読み書きができることから、近時急速に汁及し
つつある。
[Prior Art] IC cards are rapidly gaining popularity in recent years because they are compact, have a large storage capacity, and can read and write information.

第6図〜第10図は従来のICカードに係り、第6図並
びに第7図示のように、例えば塩化ビニールなどのプラ
スチック製のカード1の収納凹部内に、ICカード用の
ICチップを樹脂で封止してなるICモジュール3を内
蔵・塔載して接着剤2で固着し、該ICモジュール3に
形成した外部接続用の端子部4をカード1の表面と路面
−に露呈させた構成を採っている。そして、ICカード
をカードリーダライタに装着した際には、上記端子部4
を介して情報の読み書きが行なわれるようになっている
Figures 6 to 10 relate to conventional IC cards, and as shown in Figures 6 and 7, an IC chip for an IC card is placed in a resin storage recess in a card 1 made of plastic such as vinyl chloride. A structure in which an IC module 3 sealed with is built-in and mounted on a tower and fixed with an adhesive 2, and a terminal portion 4 for external connection formed on the IC module 3 is exposed on the surface of the card 1 and the road surface. are taken. When the IC card is installed in the card reader/writer, the terminal section 4
Information is read and written through the .

第8図は前記ICモジュール3を示している。FIG. 8 shows the IC module 3. As shown in FIG.

同図において、5はモジュール用の基板で、該基板の一
面上にはICチップ接続用の導体パターン6並びに金属
製のダイパッド7が形成されており。
In the figure, reference numeral 5 denotes a module substrate, and a conductor pattern 6 for connecting an IC chip and a metal die pad 7 are formed on one surface of the substrate.

また、基板5の他面には上記導体パターン6とスルーホ
ール8を介して接続された端子部4が形成されている。
Furthermore, a terminal portion 4 connected to the conductive pattern 6 through a through hole 8 is formed on the other surface of the substrate 5.

10はICチップで、上記ダイパッド7上に熱硬化型の
比較的高ヤング率のエポキシ系樹脂よりなるダイボンド
材11を加熱硬化させることによってダイボンディング
されており、また、ICチップ10の接続端子部は、A
u線12によって前記導体パターン6とワイヤボンディ
ングによって電気的に接続されている。13は封止材で
、例えば熱硬化型のエポキシ系樹脂よりなっており、ボ
ッティグもしくはトランスファモールドで形成されて前
記ICチップ10を封入・保護するようになっている。
Reference numeral 10 denotes an IC chip, which is die-bonded onto the die pad 7 by heating and curing a die-bonding material 11 made of a thermosetting epoxy resin with a relatively high Young's modulus. is A
It is electrically connected to the conductor pattern 6 by wire bonding through the U-wire 12. A sealing material 13 is made of, for example, a thermosetting epoxy resin, and is formed by botting or transfer molding to encapsulate and protect the IC chip 10.

第9図は前記ICモジュール3の製造工程を示すブロッ
ク図である。同図に示すように、まず工程S1で1油記
ICチツプ10がエポキシ系熱硬化型樹脂よりなる前記
ダイボンド材11によって前記基板5のダイパッド7上
に固着される。次に、工程S2のワイヤボンディング工
程で、ICチップ10と基板5の前記導体パターン6と
が接続される。続いて工程S3のボッティング工程で、
ICチップ10が前記封止材13で封止され、これが硬
化した後、封止材13が工程S4の研磨工程で所定厚み
まで研磨されてICモジュール3が完成される。
FIG. 9 is a block diagram showing the manufacturing process of the IC module 3. As shown in the figure, first, in step S1, a one-oil IC chip 10 is fixed onto the die pad 7 of the substrate 5 using the die bonding material 11 made of an epoxy thermosetting resin. Next, in a wire bonding step S2, the IC chip 10 and the conductive pattern 6 of the substrate 5 are connected. Next, in step S3, the botting step,
After the IC chip 10 is sealed with the sealant 13 and cured, the sealant 13 is polished to a predetermined thickness in a polishing step S4 to complete the IC module 3.

なお、前記封止材13をトランスファモールドで形成す
る場合には、前記工程S2の次に、工程S5のトランス
ファモールド工程で封止材13を所定厚みに形成するこ
とによって、工程は終了する。
In addition, when forming the said sealing material 13 by transfer molding, a process is complete|finished by forming the sealing material 13 to a predetermined thickness in the transfer molding process of process S5 after the said process S2.

[発明が解決しようとする課ME ところで、上述した従来のICカード用のICモジュー
ル3は、前記ダイボンド材11としてヤング率が300
Kgf/mm2以上の比較的硬い(高ヤング率の)材料
が用いられており、ダイボンド工程後、ダイボンド材1
1の収縮応力によって、ICチップ10の表面には第1
0図(a)に示すように大きな引張応力が発生する。例
えば、ヤング率330Kgf/mm2の熱硬化型のエポ
キシ系のダイボンド材を用いた場合、第4図に・印で示
すように(+)85MPa程度の引張応力が発生する。
[Problem to be Solved by the Invention] By the way, in the above-described conventional IC module 3 for an IC card, the die-bonding material 11 has a Young's modulus of 300.
A relatively hard (high Young's modulus) material of Kgf/mm2 or more is used, and after the die bonding process, the die bonding material 1
Due to the shrinkage stress of 1, the surface of the IC chip 10 has a first
As shown in Figure 0(a), a large tensile stress is generated. For example, when a thermosetting epoxy die-bonding material with a Young's modulus of 330 Kgf/mm 2 is used, a tensile stress of about (+) 85 MPa is generated, as shown by the symbol * in FIG. 4.

このダイボンド工程後のICチップ10表面の引張応力
は、第10図(b)に示すように、次のポツティング工
程時の前記封止材13の収縮によって一旦は圧縮応力側
へ緩和されるが、続く封止材13の研磨工程によって、
第10図(c)に示すように再びICチップIOの表面
には引張応力が発生する。即ち、上述のダイボンド材を
用い、封止材13としてヤング率が550Kgf/mm
2の熱硬化型エポキシ系樹脂を用いた場合には、第4図
示のように研磨工程後はICチップIOの表面には(+
)50MPa強の引張応力が生じている。
As shown in FIG. 10(b), the tensile stress on the surface of the IC chip 10 after this die bonding step is temporarily relieved to the compressive stress side by the contraction of the sealing material 13 during the next potting step. By the subsequent polishing process of the sealing material 13,
As shown in FIG. 10(c), tensile stress is generated again on the surface of the IC chip IO. That is, using the above die bonding material, the Young's modulus is 550 Kgf/mm as the sealing material 13.
When the thermosetting epoxy resin of No. 2 is used, the surface of the IC chip IO has (+) after the polishing process as shown in Figure 4.
) A tensile stress of over 50 MPa is generated.

因みに、ICチップ10の破壊限界値は、引張応力で(
十)100MPa、圧縮応力で(−)500M P a
程度であるため、上記したダイボンド工程によって生じ
るICチップIOの引張応力は、組立て工程時のICチ
ップクラックの発生や、カード化した後のICチップ破
壊限界値の低下、並びにワイヤボンディングの歩留り低
下などを招来し、製造歩留り並びに製品の信頼性を著し
く劣化させるという問題があった。
Incidentally, the fracture limit value of the IC chip 10 is expressed by the tensile stress (
10) 100MPa, compressive stress (-)500MPa
Therefore, the tensile stress of the IC chip IO caused by the die bonding process described above can cause problems such as the occurrence of IC chip cracks during the assembly process, a decrease in the IC chip breakdown limit after being made into a card, and a decrease in the yield of wire bonding. There is a problem in that the manufacturing yield and the reliability of the product are significantly deteriorated.

この点を解消するため、前記封止材13の研磨量をごく
僅かにすることも考えられるが、ICカードは規格上そ
の厚みを0.78mmに規定されていて、ICモジュー
ル3の厚みは最大0.68mm以下に制約される。また
、ICチップ10の厚みが0.3mmあり、他の要素要
素の厚みを勘案すると封止材13の厚みはどうしても0
.18mrn程度以下に制約され、ICチップ10の表
面側の残留引張応力はどうしても緩和不能であった。
In order to solve this problem, it may be possible to reduce the amount of polishing of the sealing material 13 to a very small amount, but the thickness of the IC card is specified to be 0.78 mm according to the standard, and the thickness of the IC module 3 is the maximum. It is restricted to 0.68 mm or less. Moreover, the thickness of the IC chip 10 is 0.3 mm, and considering the thickness of other elements, the thickness of the sealing material 13 is inevitably 0.3 mm.
.. The residual tensile stress on the surface side of the IC chip 10 was limited to about 18 mrn or less, and the residual tensile stress on the surface side of the IC chip 10 could not be alleviated.

なお、封止材13をトランスファモールド法で形成した
場合でも、同様に封止材13の厚みが制約されるため、
やはりICチップの表面側に引張応力を生じて同様の間
層が指摘された。
Note that even when the encapsulant 13 is formed by a transfer molding method, the thickness of the encapsulant 13 is similarly restricted;
Similarly, tensile stress was generated on the surface side of the IC chip, and a similar interlayer was noted.

従って、本発明の解決すべき技術的課顕は上述した従来
技術のもつ問題点を解消することにあり、その目的とす
るところは、ICチップの残留応力を軽減し、以って製
造歩留りが向上でき、信頼性の高いICカード用の半導
体装置(ICモジュール)を提供することにある。
Therefore, the technical problem to be solved by the present invention is to solve the above-mentioned problems of the prior art, and its purpose is to reduce the residual stress of IC chips, thereby increasing the manufacturing yield. An object of the present invention is to provide a semiconductor device (IC module) for an IC card that can be improved and has high reliability.

[課題を解決するための手段] 本発明の上記した目的は、基板上にICチップをダイボ
ンディングすると共に、基板上の導体パターンとICチ
ップとをワイヤボンデイグし、さらにICチップを封止
材で封止してなるICモジュールを、カードに塔載する
ようにしたICカード用の半導体装置において、前記I
Cチップ用のダイボンド材をヤング率が100Kgf/
mm”以下の材料とすることによって達成される。
[Means for Solving the Problems] The above-mentioned object of the present invention is to die-bond an IC chip onto a substrate, perform wire bonding between a conductive pattern on the substrate and the IC chip, and further seal the IC chip with a sealing material. In the semiconductor device for an IC card, the IC module is mounted on the card.
The die bonding material for C chip has a Young's modulus of 100Kgf/
This can be achieved by using a material with a diameter of 2 mm or less.

[作用] 本願発明者らは種々検討の結果、ダイボンド材をヤング
率が100Kgf/mm”以下の樹脂とすることによっ
て、ICモジュール作製後のICチップの残留応力が著
しく軽減できることを見出した。即ち、従来よりもヤン
グ率が小さな比較的軟らかなダイボンド材を用いること
によって、ダイボンド材の熱収縮に起因して生じるIC
チップ表面側の残留応力が大幅に低減される。また、カ
ード化した後にICカードに外力が加った際のICチッ
プの破壊限界値も向上できることが確認された。
[Function] As a result of various studies, the inventors of the present application found that by using a resin with a Young's modulus of 100 Kgf/mm" or less as the die-bonding material, the residual stress of the IC chip after manufacturing the IC module can be significantly reduced. By using a relatively soft die-bonding material with a smaller Young's modulus than conventional ones, ICs generated due to thermal contraction of the die-bonding material can be reduced.
Residual stress on the chip surface side is significantly reduced. Furthermore, it was confirmed that the destruction limit value of the IC chip when an external force is applied to the IC card after being made into a card can also be improved.

[実施例コ 以下本発明を図示した実施例によって説明する。[Example code] The present invention will be explained below with reference to illustrated embodiments.

第1図は本発明の第1実施例に係るICカード用の半導
体装置たるICそジュールを示す図で、同図において前
記第8図示の従来構成と同一の部材には同一符号を付し
、その説明は重複を避けるため省略する。
FIG. 1 is a diagram showing an IC module which is a semiconductor device for an IC card according to a first embodiment of the present invention. In the figure, the same members as those in the conventional configuration shown in FIG. 8 are given the same reference numerals. The explanation will be omitted to avoid duplication.

該第1実施例のICモジュール3Aは、前記第8図の従
来例と同等構造をとり同一手法によって作製されている
も、前記ICチップ10を前記ダイパッド7にダイボン
ディングによって固着するためのダイボンド材11Aと
ルて、ヤング率が、0.2Kgf/mm2の熱硬化型シ
リコーンゴム系の樹脂(ゴム系ペースト)が用いられて
いる。
The IC module 3A of the first embodiment has the same structure as the conventional example shown in FIG. 11A, a thermosetting silicone rubber resin (rubber paste) having a Young's modulus of 0.2 Kgf/mm2 is used.

該ダイボンド材11Aの厚みは約30μmに設定されて
おり、ダイボンド材11Aを加熱硬化することによって
、厚み約300μmのICチップ10が前記基板5上に
ダイパッド7を介して固着される。
The thickness of the die bonding material 11A is set to about 30 μm, and the IC chip 10 having a thickness of about 300 μm is fixed onto the substrate 5 via the die pad 7 by heating and curing the die bonding material 11A.

そして、前述の如く前記Au線12がワイヤボンディン
グされた後、前記封止材13がボッティングによって充
填され、然る後、所定厚みに研磨されてICモジュール
3Aが完成される。該実施例においては、この封止材1
3としてヤング率が550Kgf/mm”の熱硬化型の
エポキシ系樹脂が用いられており、研磨後には、ICチ
ップ10の表面上における封止材13の厚みは最大18
0μm程度になるよう設定されている。
After the Au wire 12 is wire-bonded as described above, the sealing material 13 is filled by botting, and then polished to a predetermined thickness to complete the IC module 3A. In this example, this sealing material 1
3, a thermosetting epoxy resin with a Young's modulus of 550 Kgf/mm is used, and after polishing, the thickness of the sealing material 13 on the surface of the IC chip 10 is at most 18 kgf/mm.
It is set to be approximately 0 μm.

第2図は本発明の第2実施例に係るICカード用の半導
体装置たるICモジュールを示す図で、該実施例におけ
るICモジュール3Bは、封圧材をトランスファモール
ドによって形成しである。
FIG. 2 is a diagram showing an IC module as a semiconductor device for an IC card according to a second embodiment of the present invention, and an IC module 3B in this embodiment is formed by transfer molding a sealing material.

同図に示す基板5Aの一面には、前記導体パターン6並
びにダイパッド7が形成されていると共に、該基板5A
の他面には前記スルーホール8を介して導体パターン6
と接続された前記端子部4が形成されている。そして、
前記ICチップ10が、第1実施例のダイボンド材lI
Aと同一の材料、ヤング率、厚みのダイボンド材11A
によってダイボンディングされた後、前記Au線12に
よってICチップ10と導体パターン6とがワイヤボン
ディングされ、然る後、第1実施例の封止材13と同一
の材料、ヤング率の封止材13′をトランスファモール
ド法で形成することによって、ICモジュール3Bが完
成されるようになっている。
The conductor pattern 6 and die pad 7 are formed on one surface of the substrate 5A shown in the same figure, and the substrate 5A is
A conductive pattern 6 is formed on the other surface through the through hole 8.
The terminal portion 4 connected to the terminal portion 4 is formed. and,
The IC chip 10 is made of die bonding material lI of the first embodiment.
Die bond material 11A with the same material, Young's modulus, and thickness as A
After die bonding, the IC chip 10 and the conductor pattern 6 are wire-bonded using the Au wire 12, and then a sealing material 13 of the same material and Young's modulus as the sealing material 13 of the first embodiment is used. ' by the transfer molding method, the IC module 3B is completed.

なお、ICチップ10の表面上における封止材13′の
厚みは前記第1実施例と同様の厚みに設定されている。
The thickness of the sealing material 13' on the surface of the IC chip 10 is set to the same thickness as in the first embodiment.

第4図は、上記した本発明の第1実施例のICチップ1
0表面の残留応力と、従来構成におけるICチップ10
表面の残留応力とを対比して、各プロセス(ダイボンデ
ィング後、ボッティングによる封止後、研磨後)毎に示
す残留応力特性図で、同図で実線で示されたものが本発
明の第1実施例を、点線で示されたものが従来例を示し
ており、従来構成のものは前記ダイボンド材11のヤン
グ率が330 K g f / m m 2であること
以外は第1実施例と同一条件としである。なお、同図に
おける残留応力値の(+)側は引張応力を、(−)側は
圧縮応力をそれぞれ示しており、応力測定はICチップ
10の表面について行なった。
FIG. 4 shows the IC chip 1 of the first embodiment of the present invention described above.
0 surface residual stress and IC chip 10 in conventional configuration
The residual stress characteristic diagram is shown for each process (after die bonding, after sealing by botting, and after polishing) in comparison with the residual stress on the surface. The dotted line indicates the conventional example, and the conventional structure is the same as the first example except that the Young's modulus of the die bonding material 11 is 330 K g f / m m 2. Under the same conditions. Note that the (+) side of the residual stress value in the figure indicates tensile stress, and the (-) side indicates compressive stress, and the stress measurements were performed on the surface of the IC chip 10.

同図から明らかなように、本発明の第1実施例において
は、ダイボンディング後において残留応力が約(+)1
4MPa、研磨後(モジュール完成後)における残留応
力が約()14MPaとなり、従来例に比して残留応力
の軽減効果は顕著である。
As is clear from the figure, in the first embodiment of the present invention, the residual stress is approximately (+)1 after die bonding.
4 MPa, and the residual stress after polishing (after completing the module) is approximately () 14 MPa, and the effect of reducing residual stress is remarkable compared to the conventional example.

このため、組立て工程時におけるICチップ10の破損
やカード化した後のICチップ10の破壊限界値の低下
を招来することなく、製造歩留り並びに製品の(a頼性
が大幅に向上できることが確認された。
Therefore, it has been confirmed that the manufacturing yield and product reliability can be significantly improved without causing damage to the IC chip 10 during the assembly process or lowering the destruction threshold of the IC chip 10 after it is made into a card. Ta.

なお、前記第1.第2実施例ではダイボンド材11Aの
ヤング率を0.2Kgf/mm”としているが、実験に
よれば多少のバラツキはあるも、ダイボンド材11Aの
ヤング率を約100Kgf/ m rn 2以下とすれ
ば、ICモジュール化した後のICチップ10の表面の
残留応力は従来に比して絶対値対比で1/3程度以下に
軽減出来ることが確認され、ヤング率を100Kgf/
rnm2とすれば実使用上、歩留り並びに信頼性の向上
に大きく貢献する。なおまた、ICチップ10の残留応
力を可及的に低減するには封止材のヤング率との兼合い
もあるが、ダイボンド材11Aのヤング率は50 K 
K f /mm”以下とすることが望ましい。
In addition, the above-mentioned No. 1. In the second embodiment, the Young's modulus of the die-bonding material 11A is set to 0.2 Kgf/mm'', but according to experiments, although there is some variation, if the Young's modulus of the die-bonding material 11A is approximately 100 Kgf/m rn 2 or less. It was confirmed that the residual stress on the surface of the IC chip 10 after being made into an IC module can be reduced to about 1/3 or less in absolute value compared to the conventional one, and the Young's modulus can be reduced to 100 kgf/
If rnm2 is used, it will greatly contribute to improving yield and reliability in actual use. Furthermore, in order to reduce the residual stress of the IC chip 10 as much as possible, there is a need to balance the Young's modulus of the sealing material, and the Young's modulus of the die bonding material 11A is 50 K.
It is desirable to set it to K f /mm'' or less.

第5図は、ICモジュール化した後の負荷荷重とICチ
ップ10の表面の応力との関係を示す荷重一応力特性図
で、同図の特性線Aがダイボンド材のヤング率を0.2
Kgf/mm”とした場合を、同図の特性線Bがダイボ
ンド材のヤング率を20Kgf/mrn2とした場合を
、同図の特性線Cがダイボンド材のヤング率を100K
Hf /+nm2とした場合の本発明の各実験例を、ま
た、同図の特性線りがダイボンド材のヤング率を330
Kgf/ m m ”とした場合(従来例)を示してお
り、何れも封止材のヤング率は550Kgf/rnm2
としである。測定方法は、第3図に示すようにL=12
rnm、W=l OrnmのICモジュール3(3Aも
しくは3B)を2本のバー状支持体14で支承し、反対
面に荷重Fを加える3点曲げ試験を行ない、ICチップ
10の表面応力を測定した。
FIG. 5 is a load-stress characteristic diagram showing the relationship between the applied load and the stress on the surface of the IC chip 10 after it is made into an IC module, and the characteristic line A in the figure shows the Young's modulus of the die bonding material of 0.2.
Kgf/mm", characteristic line B in the same figure represents the case where the Young's modulus of the die-bonding material is 20 Kgf/mrn2, and characteristic line C in the same figure represents the Young's modulus of the die-bonding material at 100 K.
The experimental examples of the present invention when Hf /+nm2 are shown, and the characteristic line in the same figure shows that the Young's modulus of the die bonding material is 330.
Kgf/m m'' (conventional example), and the Young's modulus of the sealing material is 550 Kgf/rnm2 in both cases.
It's Toshide. The measurement method is L=12 as shown in Figure 3.
rnm, W=l Ornm's IC module 3 (3A or 3B) is supported by two bar-shaped supports 14, and a three-point bending test is performed in which a load F is applied to the opposite surface, and the surface stress of the IC chip 10 is measured. did.

第5図から明らかなように、ダイボンド材のヤング率が
100Kgf/mm2以下であれば、2Kgf強の外力
が加っても、ICチップには(+)100MPa以下の
応力しか発生せず、実使用上、ICカードを相当にラフ
に取扱ってもICチップに破壊が生じないことが確認さ
れた。
As is clear from Fig. 5, if the Young's modulus of the die-bonding material is 100 Kgf/mm2 or less, even if an external force of over 2 Kgf is applied, only a stress of (+)100 MPa or less will be generated in the IC chip, which is not practical. It has been confirmed that the IC chip is not damaged even if the IC card is handled fairly roughly.

なお、前述した第1.第2実施例においては、ダイボン
ド材としてシリコーンゴム系のものを用いているが、こ
の他にエポキシ系樹脂、アクリル系樹脂などの任意の材
料が選択し得ること勿論である。なおまた、前記封止材
の材料も種々のものが選択可能で、例えば、光硬化型の
アクリル系樹脂をボッティングし、これをガラス板で押
付けてノブみを規制した状態で光照射して樹脂を硬化さ
せ、封止するようにしてもよい。
In addition, the above-mentioned 1. In the second embodiment, silicone rubber is used as the die bonding material, but it goes without saying that any other material such as epoxy resin or acrylic resin may be selected. Furthermore, various materials can be selected for the sealing material; for example, a photo-curable acrylic resin is potted, and this is pressed with a glass plate and irradiated with light while controlling the knob shape. The resin may be cured and sealed.

[発明の効果] 叙上のように本発明によれば、ICチップの残留応力が
軽減でき、ffd造歩留りが向上すると共に、信頼性の
高いICカード用の半導体装置(ICモジュール)が提
供でき、その産業的価値は多大である。
[Effects of the Invention] As described above, according to the present invention, the residual stress of the IC chip can be reduced, the FFD manufacturing yield can be improved, and a highly reliable semiconductor device (IC module) for an IC card can be provided. , its industrial value is enormous.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の第1実施例に係るICモジュールの断
面図、第2図は本発明の第2実施例に係るICモジュー
ルの断面図、第3図は3点曲げ試験の説明図、第4図は
本発明の第1実施例と従来例の各製造プロセス毎のIC
チップの残留応力を示す残留応力特性図、第5図はダイ
ボンド材のヤング率を異ならせた各ICモジュールにお
ける負荷荷重とICチップの応力との関係を示す荷重−
応力特性図、第6図〜第10図は従来例に係り、第6図
はICカードの平面図、第7図はICカードの要部断面
図、第8図はICモジュールの断面図、第9図はICモ
ジュールの製造工程を示すブロック図、第10図はIC
チップの残留応力発生を説明するためのモデル化した説
明図である。 l・・・・・・カード、2・・・・・・接着剤、3.3
A、3B・・・・・・ICモジュール、4・・・・・・
端子部、5,5A・・・・・・モジュール用の基板、6
・・・・・・導体パターン、7・・・・・・ダイパッド
、8・・・・・・スルーホール、10・・・・・・IC
チップ、11.IIA・・・・・・ダイボンド材、12
・・・・・・Au線、13.13’・・・・・・封止材
。 第5図 第4図
FIG. 1 is a sectional view of an IC module according to a first embodiment of the present invention, FIG. 2 is a sectional view of an IC module according to a second embodiment of the present invention, and FIG. 3 is an explanatory diagram of a three-point bending test. Figure 4 shows ICs for each manufacturing process of the first embodiment of the present invention and the conventional example.
A residual stress characteristic diagram showing the residual stress of the chip. Figure 5 is a load diagram showing the relationship between the applied load and the stress of the IC chip in each IC module with different Young's modulus of the die-bonding material.
Stress characteristic diagrams, Figures 6 to 10 relate to conventional examples, Figure 6 is a plan view of the IC card, Figure 7 is a sectional view of the main parts of the IC card, Figure 8 is a sectional view of the IC module, and Figure 8 is a sectional view of the IC module. Figure 9 is a block diagram showing the manufacturing process of the IC module, and Figure 10 is the IC module.
FIG. 3 is a modeled explanatory diagram for explaining the generation of residual stress in a chip. l...Card, 2...Adhesive, 3.3
A, 3B...IC module, 4...
Terminal part, 5,5A... Board for module, 6
...Conductor pattern, 7...Die pad, 8...Through hole, 10...IC
Chip, 11. IIA・・・Die bond material, 12
...Au wire, 13.13'... Sealing material. Figure 5Figure 4

Claims (1)

【特許請求の範囲】[Claims]  基板上にICチップをダイボンディングすると共に、
基板上の導体パターンとICチップとをワイヤボンデイ
グし、さらにICチップを封止材で封止してなるICモ
ジュールを、カードに塔載するようにしたICカード用
の半導体装置において、前記ICチップ用のダイボンド
材を、ヤング率が100Kgf/mm^2以下の材料と
したことを特徴とするICカード用の半導体装置。
Along with die bonding the IC chip onto the substrate,
In a semiconductor device for an IC card, in which an IC module is mounted on a card by wire bonding a conductor pattern on a substrate and an IC chip, and further sealing the IC chip with a sealing material, A semiconductor device for an IC card, characterized in that the die-bonding material is a material having a Young's modulus of 100 Kgf/mm^2 or less.
JP63209537A 1988-08-25 1988-08-25 Semiconductor device for ic card Pending JPH0259399A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63209537A JPH0259399A (en) 1988-08-25 1988-08-25 Semiconductor device for ic card

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63209537A JPH0259399A (en) 1988-08-25 1988-08-25 Semiconductor device for ic card

Publications (1)

Publication Number Publication Date
JPH0259399A true JPH0259399A (en) 1990-02-28

Family

ID=16574447

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63209537A Pending JPH0259399A (en) 1988-08-25 1988-08-25 Semiconductor device for ic card

Country Status (1)

Country Link
JP (1) JPH0259399A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2684235A1 (en) * 1991-11-25 1993-05-28 Gemplus Card Int INTEGRATED CIRCUIT CARD COMPRISING MEANS OF PROTECTING THE INTEGRATED CIRCUIT.
JP2007280983A (en) * 2006-04-03 2007-10-25 Nichia Chem Ind Ltd Light emitting device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2684235A1 (en) * 1991-11-25 1993-05-28 Gemplus Card Int INTEGRATED CIRCUIT CARD COMPRISING MEANS OF PROTECTING THE INTEGRATED CIRCUIT.
JP2007280983A (en) * 2006-04-03 2007-10-25 Nichia Chem Ind Ltd Light emitting device

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