JPH0260096B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a two-coefficient frequency divider used in a PLL (Phase Locked Loop) circuit, particularly a frequency divider of 1/(2N+1) and 1/2N (N is an integer). The present invention relates to a signal selection circuit for a two-coefficient frequency divider having a switching function.

Configuration of the conventional example and its problems FIG. 1 shows the configuration of the conventional example. 1 is the first 1/2 counter, 2 is the second 1/2 counter, 3
is a 1/10 counter, and 4 is a signal selection circuit. 5
~8,32 are inverters, 9~16,31 are
NAND gate, 17, 18 is AND gate, 19
is a NOR gate. Outputs of the first 1/2 counters having mutually opposite phases are connected to the signal selection circuit 4, the selected output is connected to the second 1/2 counter, and the output of the second 1/2 counter 2 is connected to the signal selection circuit 4. teeth,
It is connected to one input of the 1/10 counter 3 and the NAND gate 9, and the output of the 1/10 counter 3 is connected to the other input. The output of the NAND gate 9 is sent to the signal selection circuit 4 via the inverter 5.
This is one of the switching control inputs. 26 is another switching control input.

The configuration of the signal selection circuit 4 will be explained below.

NAND gates 15 and 16 form a reset flip-flop. AND gate 1
7, 18 and the NOR gate 19 form a selector. The switching control input 26 is provided via the NAND gate 11 and the inverter 6.
Connected to NAND gate 10. The output 27 of the inverter 5 is connected to NAND gates 10,11. NAND gates 10 and 11
The outputs of are transmitted through inverters 7 and 8 respectively.
Connected to NAND gates 13 and 31.
The outputs of NAND gates 13 and 31 are connected to NAND gates 15 and 31 forming a flip-flop.
16, respectively. As for the outputs of the flip-flop, the output 29 of the NAND gate 15 is connected to the AND gate 17, and the output 28 of the NAND gate 16 is connected to the AND gate 18.
The output of the selector composed of AND gates 17, 18 and NOR gate 19, that is, NOR
The output of the gate 19 is passed through the inverter 32 to
It is connected to NAND gates 13 and 31.

Outputs 21 and 22 of mutually opposite phases of the first 1/2 counter 1 constitute a selector.
It is connected to AND gates 17 and 18.

At the switching control input 26 and the other switching control input, that is, the output 27 of the inverter 5, the outputs of the 1/2 selector 1 having opposite phases to each other are connected to the signal selection circuit 4.
is selected and output.

The conventional example shown in FIG. 1 is a two-coefficient prescaler, and as a whole constitutes a counter capable of switching coefficients of 1/40 and 1/41.

Next, the operation of the conventional example will be explained using a timing chart.

FIG. 2 is a timing chart showing the timing of the main parts.

20 is an input pulse of the first 1/2 counter, and 21 and 22 are outputs having opposite phases to each other. 23 is the output of the signal selection circuit 4; 30
is the output of the inverter 32. 24 is the second
is the output of 1/2 counter 2, and 25 is 1/10
This is the output of counter 3. 26 and 27 are switching control inputs. 28 and 29 are flip-flop outputs.

When the output 28 of the flip-flop is at the "low" level and the output 29 is at the "high" level, one output signal 21 of the first 1/2 counter 1 is output as the output of the signal selection circuit, and the output 23 is the output signal 21 of the first 1/2 counter 1. ,
The inverted phase output is output.

At the timing of t ₁ , output 2 of 1/10 counter 3
5 becomes “high” level, and at timing t ₂ ,
The output 24 of the second 1/2 counter 2 is “high”
At timing _t3 when the output 30 of the inverter 32 becomes "high" level, 24,2
The logical product of 5 and 30 is taken, and the input 27 of the flip-flop becomes a "low" level. At this time, the output 28 of the flip-flop becomes "high" level.

Further, the other output 29 of the flip-flop is delayed by the width of the output pulse of the first 1/2 counter.
becomes “low” level at timing _t4 .

By controlling the flip-flop outputs 28 and 29, the signal output to the selector output 23 is
The output 21 of the first 1/2 counter 1 is switched to the output 22 having the opposite phase.

During the period _T1 , the output signal 21 is selected and its inverted signal is output to the output 23 of the selector,
During the period T ₂ , the output signal 22 is selected and its inverted signal is output to the output 23 of the selector.

During the period _T3 , the output signal 23 of the selector is at a "low" level.

Focusing on the output signal 23 of the selector, at the timing _t4 , the output 2 of the first 1/2 counter 1
1 and 22 are switched, and the "low" level continues twice, and the output 23 of the selector is shifted by one pulse of the input 20 of the first 1/2 counter 1, and the pulse count of the entire system is changed. The number is 41, giving a frequency division ratio of 1/41.

The operational constraints of this conventional example include the delay of the second 1/2 counter 2 after the signal is output from the signal selection circuit 4;
Or a delay of 1/10 counter 3, and
NAND gate 9 and inverter 5 delay, and
The delay time of the NAND gate 10, the inverter 7 and the NAND gate 13, or the sum of the delays of the NAND gate 11, the inverter 8 and the NAND gate 31 is the output 2 of the first 1/2 counter 1.
It must be within a period of 1.22. Also, inside the signal selection circuit, NAND gates 15 and 16
The load on the flip-flop is heavy, which is a factor that limits the speed of switching operations.

Relatively low-speed devices such as CMOS (bi-complementary field-effect transistors) have difficulty operating at high speeds.

Figure 3 shows the signal selection circuit of this conventional example in CMOS
Shows the frequency characteristics when made with an integrated circuit.

OBJECTS OF THE INVENTION The present invention provides a signal selection circuit suitable for integrated circuits, which eliminates these drawbacks of the prior art.

Structure of the Invention The present invention provides two types of pulses having opposite phases to each other.
Control of two switching inputs, which are switched in synchronization with the above-mentioned pulses having opposite phases, and an input terminal to which the first and second clock pulses having opposite phases are applied, and the first and second switching input terminals. an input, first and second logic gate circuits, third and fourth logic gate circuits whose output timing is controlled by the first clock pulse, and whose output timing is controlled by the second clock pulse. a fifth logic gate circuit and a selector, the first and second switching control inputs are connected to the inputs of the first logic gate circuit, and the first switching control input is phase-inverted. signal and the second switching control input are connected to an input of the third logic gate circuit, an output of the first logic gate circuit is connected to an input of a fourth logic gate circuit, and the first and second switching control inputs are connected to an input of the third logic gate circuit. The output of the fourth logic gate circuit is connected to the input of the second logic gate circuit, and the output of the second logic gate circuit is connected to the input of the fifth logic gate circuit and the input of the fourth logic gate circuit. input, and also connected to one signal selection input of the selector, and the output of the fifth logic gate circuit is connected to the other signal selection input of the selector,
connecting a selected signal input terminal of the selector to the first and second clock pulse input terminals;
Furthermore, the first clock pulse input terminal is connected to the clock control inputs of the third and fourth logic gate circuits, and the second clock pulse input terminal is connected to the clock control input of the fifth logic gate circuit. It has a connected configuration. This realizes a signal selection circuit that does not malfunction even in high frequency operation.

DESCRIPTION OF EMBODIMENTS FIG. 4 shows the configuration of a first embodiment of the present invention.

In FIG. 4, 51 and 52 are the first and
an input terminal 53,5 to which a second control signal is applied;
4 is an input terminal to which two types of pulses having mutually opposite phases (hereinafter referred to as CK ₁ and CK ₂ , respectively) are applied; 55 is an output terminal of the signal selection circuit; 57, 62
is a NAND gate whose output is controlled by a clock.
When the clock is at "high" level, it is output as NAND, and when it is at "low" level, it becomes high impedance. 60 is an inverter whose output is controlled by a clock, and when the clock is at a "high" level,
It is output from the inverter and becomes high impedance when it is at "low level". 56 is an inverter, 5
8, 59, 61, 63, and 64 are NAND gates. 65 is a pulse applied to the input terminal 53
CK ₁ , 66 is a pulse applied to the input terminal 54
CK ₂ , 67 is the first control signal applied to the input terminal 51, 68 is the second control signal applied to the input terminal 52, 69 is the NAND signal controlled by the clock.
70 is the output of NAND gate 58; 71 is the output of clock-controlled NAND gate 62; 72 is the output of NAND gate 59;
73 is the output of the inverter 60 controlled by the clock, 74 is the output of the NAND gate 63, and 75 is the output of the inverter 60 controlled by the clock.
The output of the NAND gate 61 and 76 are the output of the NAND gate 64.

Input terminal 51 is connected to inverter 56 and
The input terminal 52 is connected to a clock-controlled NAND gate 57 and to a NAND gate 58. The output of inverter 56 is connected to a clock controlled NAND gate 57, which is clock controlled.
The output 69 of the NAND gate 57 is the NAND gate 5
9, the output 72 of 59 is connected to clocked NAND gate 62, clocked inverter 60, and NAND gate 6.
Connected to 1. Output 70 of NAND gate 58
is connected to a clock controlled NAND gate 62 whose output 71 is connected to NAND gate 59. Clock controlled inverter 60
The output 73 and input terminal 53 of NAND
Connected to gate 63, input terminal 54 is NAND
The output 75 of the NAND gate 61 and the output 74 of the NAND gate 63 are connected to the gate 61 .
is connected to the NAND gate 64, and the output 7 of 64
6 is connected to the output terminal 55.

Input terminal 53 is connected to the control clock of NAND gates 57 and 62 which are controlled by the clock, and input terminal 54 is connected to the control clock of inverter 60 which is controlled by the clock.

NAND gates 61, 63 and 64 constitute a selector.

The operation of this embodiment configured as described above will be explained below based on the timing charts of FIGS. 5 and 6.

5 and 6 show the timing of this embodiment, and the indicated points are indicated with the same symbols as in FIG. 4.

65 is the pulse CK ₁ applied to the input terminal 53, and 66 is the pulse applied to the input terminal 54.
It is CK ₂ . 65 and 66 are pulses with mutually opposite phases. 67 is a first control signal applied to the input terminal 51, and 68 is a second control signal applied to the input terminal 52. 69 is the output of the NAND gate 57 controlled by the clock, and 70 is the output of the NAND gate 57 controlled by the clock.
71 is the output of NAND gate 58, and 71 is the output of NAND gate 62 controlled by the clock.
72 is the output of the NAND gate 59, and 73 is the output of the inverter 60 controlled by the clock. 74 is the output of the NAND gate 63;
5 is the output of the NAND gate 61, and 76 is the output of the NAND gate 61.
This is the output of the NAND gate 64, and serves as the output of the selector composed of NAND gates 61, 63, and 64. Reference numerals 72 and 73 are control signals for a selector that selects one of the pulses 65 and 66 having mutually opposite phases.

First, the operation of this embodiment will be explained based on FIG.

When the first control signal 67 is at a "high" level, the output 73 of the clock-controlled inverter 60 is at a "high" level, and the output 72 of the NAND gate 59 is at a "low" level, the output 76 of the selector
Then, signal 65 is selected and output.

At timing _t101 , the first control signal 67 becomes a "low" level, and at timing _t102 , the second control signal 68 becomes a "high" level. The first and second control signals are controlled by a clock.
connected to NAND gate 57 and controlled by a clock via NAND gate 58
Connected to NAND gate 62, 57,6
2 control clock 65 becomes “high” level.
At the timing of t ₁₀₃ , the output 69 of 57 is “low”
level, the output 72 of the NAND gate 59 to which 69 is connected becomes a "high" level, and 7
The output 71 of 62 to which the output 70 of the NAND gate 58 and the output 70 of the NAND gate 58 are connected becomes "low" level. 72 is an inverter 6 controlled by a clock.
0, and at timing _t104 when the control clock 66 of the 60 becomes a "high" level, the output 73 of the 60 becomes a "low" level. Since 72 is now at the "high" level and 73 is at the "low" level, the output 75 of the NAND gate 61 outputs the inverted signal of the input 66, and the output 75 of the NAND gate 63 is at the "low" level.
4 becomes the “high” level, and selector output 7
6, the signal 66 is selected and output, and the signal 6
The selected signal is switched from signal 5 to signal 66.

During the period from timing t ₁₀₃ to t ₁₀₄ , the signals 72,
73 are both at the "high" level, the signal 65 is at the "high" level, and the signal ₆₆ is at the "low" level.
When the signal 65 switches from the signal 65 to the signal 66, the signal 66 is at the "high" level, so the signal 76 becomes the "high" level, which means that the "high" level is output twice in a row, and the signal 65 , the selector output 76 has been reduced by half a pulse compared to the signal 66.

When the second control signal 68 becomes "low" level at timing _t105 , it is controlled by the clock.
The output 69 of the NAND gate 57 is the control clock 6
Timing t ₁₀₆ until 5 becomes “high” level
So it becomes a “high” level.

Next, based on Figure 6, selector output 7
6 will explain the operation of switching from signal 66 to signal 65.

When the first control signal 67 is at a "low" level, the output 73 of the clock-controlled inverter 60 is at a "low" level, and the output 72 of the NAND gate 59 is at a "high" level, the output 76 of the selector
, signal 66 is selected and output.

At timing _t111 , the first control signal 67 becomes "high" level, and at timing _t112 , the second control signal 67 becomes "high" level.
This shows the time when the control signal 68 of the control signal 68 becomes "high" level. The first and second control signals are connected to a clock-controlled NAND gate 57, and
It is connected via NAND gate 58 to a clock controlled NAND gate 62. Output 69 of clock controlled NAND gate 57
is “high” because the signal 67 is “high” level.
level, and does not change at timing _t112 .
The output 70 of the NAND gate 58 goes low at timing _t112 and is controlled by the clock.
The output 71 of the NAND gate 62 is the control clock 6
At timing _t113 when the signal 69 and the signal 71 are connected to the signal 69 and the signal 71, the output 72 of the NAND gate 59 becomes the low level. The output 73 of the inverter 60 controlled by the clock becomes "high" at timing _t114 when the control clock signal 66 becomes "high".
level.

Now, the signal 72 is at the "low" level, and the signal 73 is at the "low" level.
becomes “high” level, so NAND gate 6
The output 75 of 1 becomes “high” level, and the NAND
The output 74 of the gate 63 outputs the inverted signal of the input 65, the signal 65 is selected and outputted to the output 76 of the selector, and the selected signal is switched from signal 66 to signal 65.

During the period from timing t ₁₁₃ to t ₁₁₄ , signals 72 and 7
3 are both at "low" level, and the signals 74 and 75
Since both are at the "high" level, the output 76 of the selector is at the "low" level. timing
When the output 76 of the selector switches from the signal 66 to the signal 65 at t ₁₁₄ , the signal 65 is at the "low" level, so the output 76 of the selector becomes the "low" level, and the "low" level is output twice in a row. It means that it was done. As with the switching from signal 65 to signal 66 described above, when switching from signal 66 to signal 65, the output 76 of the selector is reduced by half a pulse compared to signals 65 and 66, respectively.

When the second control signal 68 goes to the "low" level at timing _t115 , the output 70 of the NAND gate 58 goes to the "high" level.

In this embodiment, pulse signals 65 and 65 having mutually opposite phases are used.
One of the signals 66 can be selected and output using two control signals 67 and 68, and the selected signal can be switched in synchronization with the signals 65 and 66. That is, when switching from signal 65 to signal 66, the state changes from outputting the "high" level of signal 65 to outputting the "high" level of signal 66, and when switching from signal 66 to signal 65, The state changes from the state in which the signal 66 is output at the "low" level to the state in which the signal 65 is output at the "low" level. Therefore, every time there is a switch, the signal 6
5 and 66, the output of this embodiment is reduced by half a pulse.

Because it uses a clock-controlled NAND gate and a clock-controlled inverter,
It is possible to synchronize with the input pulse signals 65 and 66, without creating a delay as seen in the conventional example, and by using a clock-controlled NAND gate 57 or the same 6.
2 and the total delay time of the NAND gate 59,
It is sufficient that the period of the "high" level of the input pulse signal 65 is long, and it is sufficient that the period of the "high" level of the input pulse signal 66 is longer than the delay period of the inverter 60 controlled by the clock. moreover,
Compared to the load of conventional flip-flops,
The load on the NAND gate 59 can be reduced, and high-speed operation is possible.

The fall of the output 71 of the NAND gate 62 controlled by the clock at timing t ₁₀₃ in FIG. 5 may be completed by the time t ₁₀₆ when the output 69 of the NAND gate 57 controlled by the clock rises. It is also controlled by a clock.
The rising edge of the output 69 of the NAND gate 57 is
Since the control signals 51 and 52 both become "high" level, the process may be completed before the output 71 of 62 becomes "high" level. Therefore, when this embodiment is configured with a CMOS integrated circuit, it is possible to reduce the gate width of the P-type transistor among the CMOS transistors 57 and the N-type transistor among the CMOS transistors 62. controlled by each clock
Since the load on the circuit before the NAND gates 57 and 62 can be reduced, even higher speed operation is possible.

As described above, this embodiment is a signal selection circuit that can operate at high speed even in relatively low-speed devices such as CMOS.

A second embodiment of the present invention will be described below. FIG. 7 shows the configuration of a second embodiment of the present invention. In this embodiment, a signal selection circuit is used as a counter for switching the frequency division ratio between 1/40 and 1/41.

In FIG. 7, 200 is a terminal to which an input pulse is applied, 201 is a first 1/2 counter, and 2
02 is a signal selection circuit, 203 is a second 1/2 counter, 204 is a 1/10 counter, and 205 is a
NAND gate, 206 is an inverter, 207 is a pulse applied to the terminal 200, 208 is 1/2
The output of the counter 203 and 209 are the outputs of the 1/10 counter 204.

The configuration of the signal selection circuit 202 is similar to the configuration shown in FIG. 4, so the same symbols are used and the explanation will be omitted.

Input terminal 20 of first 1/2 counter 201
0 is connected, and the two types of pulses with mutually opposite phases outputted from the 1/2 counter 201 become input pulses 65 and 66 of the signal selection circuit 202. The output 76 of the signal selection circuit 202 is connected to the input of the second 1/2 counter 203, and the output 208 of the second 1/2 counter 203 is connected to the input of the 1/10 counter 204. The output 209 of the 1/10 counter 204 and the output 208 of the 1/2 counter 203 are NAND
It is connected to the gate 205 , and its output is connected to the inverter 206 , and the output of the inverter 206 becomes the second control signal 68 of the signal selection circuit 202 .

Next, the operation of this embodiment will be explained using a timing chart.

FIGS. 8 and 9 are timing charts of this embodiment, and the indicated points are indicated by the same symbols as in FIG. 7.

207 is an input of the first 1/2 counter 201, and 65 and 66 are outputs of 201 having opposite phases. 67 is a first control signal of the signal selection circuit 202, and 68 is a second control signal, which is the output of the inverter 206. 69 is the output of the NAND gate 57 controlled by the clock, and 70 is the output of the NAND gate 57 controlled by the clock.
The output of NAND gate 58, 71 is the output of NAND gate 62 controlled by the clock, 72 is
Output of NAND gate 59, 73 is output of inverter 60 controlled by clock, 74 is NAND
The output of the gate 63, 75 is the output of the NAND gate 61, 76 is the output of the NAND gate 64,
This is the output of the signal selection circuit 202. 208 is the second
209 is the output of the 1/10 counter.

First, the operation of this embodiment will be explained based on FIG.

When the first control signal 67 is at a "high" level, the output 73 of the clock-controlled inverter 60 is at a "high" level, and the output 72 of the NAND gate 59 is at a "low" level, the signal 65 is selected;
It is output to the output 76 of the signal selection circuit 202. At timing t ₂₂₁ , the first control signal 67 becomes “low” level, and at timing t ₂₂₂ , it becomes 1/1.
When the output 208 of the 2 counter 203 and the output 209 of the 1/10 counter 204 both become "high" level, and the second control signal 68 becomes "high" level, the NAND gate 57 controlled by the clock,
At timing t ₂₂₃ when the control clock 65 of the same 62 becomes "high" level, the output 69 of the NAND gate 57 controlled by the clock is "low" level, the output 72 of the NAND gate 59 is "high" level, and the output 69 of the NAND gate 57 controlled by the clock is "low" level. The output 71 becomes a "low" level.
The output 73 of the inverter 60, which is controlled by the clock to which the output signal 72 is connected, is output at the timing when the control clock 66 goes high.
It becomes “low” level at t ₂₂₄ .

Since the signal 72 is at the "high" level and the signal 73 is at the "low" level, the signal 66 is selected.
This becomes the output 76 of the signal selection circuit, and the selected signal is switched from signal 65 to signal 66.

During the period from timing t ₂₂₃ to t ₂₂₄ , the signals 72 and 73 are both at “high” level, and the signal 76 is at “high” level, and when the signal selected at timing t ₂₂₄ is switched to signal 66, signal 66
Since the signal 76 is at the "high" level, the signal 76 becomes the "high" level, which means that the "high" level is output twice in succession. This means that one extra pulse is counted based on the input 207 of the first 1/2 counter 201.

At timing t ₂₂₅ , second 1/2 counter 2
When the output 208 of 03 becomes "low" level, the second control signal 68 becomes "low" level, and since the signal 65 is "high" level, the signal 69 becomes "high" level.

Next, based on FIG. 9, from signal 66 to signal 6
The switching operation to 5 will be explained.

When the first control signal 67 is at a "low" level, the output 73 of the clock-controlled inverter 60 is at a "low" level, and the output 72 of the NAND gate 59 is at a "low" level.
When is at the "high" level, the signal 66 is selected and output to the output 76 of the signal selection circuit.

At timing t ₂₃₁ , the first control signal 67 becomes “high” level, and at timing t ₂₃₂ , the second control signal 67 becomes “high” level.
This shows the time when the control signal 68 of the control signal 68 becomes "high" level.

When the signals 67 and 68 both become "high" level at timing t ₂₃₂ , the output 70 of the NAND gate 58 becomes "low" level, and since the signal 65 is "high" level, it is controlled by the clock.
The output 71 of the NAND gate 62 becomes "high" level. NAND gate 5 controlled by clock
Since the output 69 of 7 is already at the "high" level, the NAND gate 59 which receives each signal 69 and 71 as input
The output 72 of the inverter 60 becomes "low" level, and at timing _t233 when the signal 66 becomes "high" level, the output 73 of the inverter 60 controlled by the clock becomes "high" level. Signal 72 is “low” level,
Since the signal 73 becomes "high" level, the signal 65 is selected as the output 76 of the signal selection circuit 202, and the selected signal is switched from the signal 66 to the signal 65.

During the period from timing t ₂₃₂ to t ₂₃₃ , signals 72 and 7
3 are both at "low" level, and the signal selection circuit 20
The output 76 of 2 becomes a "low" level. When the signal 66 is switched to the signal 65 at timing t ₂₃₃ , the signal 65 is at the "low" level, so the output 76 becomes the "low" level, meaning that the "low" level is output twice in a row. .

Similar to the switching from signal 65 to signal 66 described above, when switching from signal 66 to signal 65,
Based on the input 207 of the first 1/2 counter 201, one extra pulse is counted.

At timing t ₂₃₄ , second 1/2 counter 2
When the output 208 of 03 becomes "low" level, the second control signal 68 becomes "low" level,
The output 70 of the NAND gate 58 becomes "high" level.

Looking at the entire system of the embodiment shown in FIG.
2 1/2 counters, 1 1/10 counter
The frequency of the input pulse 207 is divided by 1/40. However, as described above, each time the signal selection circuit 202 switches the output from the signal 65 to the signal 66 or from the signal 66 to the signal 65,
Since one extra pulse of the input pulse 207 is counted, the frequency of the input clock signal 207 is divided by 1/41 when switching is performed. If the first control signal 67 is fixed at the "high" level or "low" level, the signal selection circuit 202 will not switch the output, and this system will have a frequency division ratio of 1/40. The coefficient becomes 1/41, and coefficient switching of 1/40 and 1/41 can be performed.

As described in the first embodiment of the present invention, the signal selection circuit of the present invention is capable of high-speed operation, and by using this, the two-coefficient frequency divider of the second embodiment can It operates well even when the frequency is high.

FIG. 10 shows frequency characteristics when the second embodiment is constructed using a CMOS integrated circuit.

Note that in the first embodiment, the configuration is made of NAND gates, but it may be configured using NOR gates.

In addition, in the second embodiment, the frequency division ratio is 1/40,
The counter was designed to switch 1/41, but the arbitrary division ratio 1/N, 1/(N+1) (N is a positive integer)
It may also be a counter that performs switching.

Effects of the Invention According to the present invention, by using a logic gate controlled by a clock, the operation from receiving a control signal to switching the selected signal has a margin with respect to the frequency of the signal. Because this process is performed simultaneously, it is possible to switch the selected signal even with high-frequency signals, and even if relatively slow devices such as CMOS devices are used, good frequency characteristics can be obtained without malfunction. In particular, it is possible to provide a signal selection circuit suitable for integrated circuits.

[Brief explanation of the drawing]

Figure 1 is a configuration diagram of a conventional signal selection circuit;
The figure shows the timing chart of the conventional example shown in Fig. 1, and the timing chart of the conventional example shown in Fig. 3.
The figure shows the frequency characteristics of the conventional example shown in Fig. 1, and Fig. 4 shows the frequency characteristics of the conventional example.
The configuration diagram of the first embodiment of the present invention, FIGS. 5 and 6 are timing charts of the first embodiment of the present invention,
FIG. 7 is a block diagram of the second embodiment of the present invention;
9 is a timing chart of the second embodiment of the present invention, and FIG. 10 is a diagram showing the frequency characteristics of the second embodiment of the present invention. 51-54...Input terminal, 55...Output terminal, 56
...Inverter, 57, 62... NAND gate controlled by clock, 60... Inverter controlled by clock, 58, 59, 61, 63, 64...
NAND gate.

Claims (1)

[Claims] 1. An input terminal to which first and second clock pulses having an opposite phase relationship are applied;
a switching control input, first and second logic gate circuits, third and fourth logic gate circuits whose output timing is controlled by the first clock pulse, and whose output timing is controlled by the second clock pulse. and a selector, the first and second switching control inputs being connected to the inputs of the first logic gate circuit,
A signal obtained by inverting the phase of the first switching control input and the second switching control input are connected to the input of the third logic gate circuit, and the output of the first logic gate circuit is connected to the fourth logic gate. Connect to the input of the circuit,
The outputs of the third and fourth logic gate circuits are connected to the inputs of the second logic gate circuit;
The output of the logic gate circuit is connected to the input of the fifth logic gate circuit and the input of the fourth logic gate circuit, and also connected to one signal selection input of the selector, and the output of the other logic gate circuit of the selector is connected to the input of the fifth logic gate circuit and the fourth logic gate circuit. The selection input is connected to the output of the fifth logic gate circuit, the selected signal input terminal of the selector is connected to the first and second clock pulse input terminals, and the third and fourth clock pulse input terminals are connected to the selection input. The first clock pulse input terminal is connected to the clock control input of the fifth logic gate circuit, and the second clock pulse input terminal is connected to the clock control input of the fifth logic gate circuit. selection circuit. 2. The signal selection circuit according to claim 1, wherein the first, second, third, and fourth logic gate circuits are NAND gates, and the fifth logic gate circuit is an inverter.