JPH0260137A - Board for semiconductor element mounting use - Google Patents

Board for semiconductor element mounting use

Info

Publication number
JPH0260137A
JPH0260137A JP21043288A JP21043288A JPH0260137A JP H0260137 A JPH0260137 A JP H0260137A JP 21043288 A JP21043288 A JP 21043288A JP 21043288 A JP21043288 A JP 21043288A JP H0260137 A JPH0260137 A JP H0260137A
Authority
JP
Japan
Prior art keywords
copper foil
insulating layer
semiconductor element
mounting
resin film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21043288A
Other languages
Japanese (ja)
Inventor
Hiroshi Waki
脇 浩
Nobuhiro Fukuda
福田 信弘
Shunji Yoshida
芳田 俊爾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsui Toatsu Chemicals Inc
Original Assignee
Mitsui Toatsu Chemicals Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsui Toatsu Chemicals Inc filed Critical Mitsui Toatsu Chemicals Inc
Priority to JP21043288A priority Critical patent/JPH0260137A/en
Publication of JPH0260137A publication Critical patent/JPH0260137A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0313Organic insulating material
    • H05K1/0353Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
    • H05K1/0373Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement containing additives, e.g. fillers

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To obtain a copper foil suitable for a board for semiconductor element mounting use by a method wherein an insulating layer consisting of an inorganic substance is formed on the copper foil. CONSTITUTION:An insulating layer 2 consisting of an inorganic substance is formed on a copper foil 1. Materials usable for the formation of the insulating layer consisting of this inorganic substance are an oxide, a nitride, a carbide and the like. Concretely, such materials having electrical insulation properties as an Si oxide, an Al oxide, a titanium oxide, a tantalum oxide, an Si nitride, an Al nitride and an Si carbide can be effectively used. In such a way, as the insulating layer consisting of the inorganic substance is formed on the copper foil, a copper foil suitable for a board for semiconductor element mounting use can be obtained.

Description

【発明の詳細な説明】 〔技術分野〕 本発明は半導体素子実装用基板に関するものであり、と
(に、接着剤を不要とする構造の半導体素子実装用基板
に好適な銅箔およびそれを使用した半導体素子の実装用
基板に関する。
[Detailed Description of the Invention] [Technical Field] The present invention relates to a substrate for mounting semiconductor elements, and more particularly, a copper foil suitable for a substrate for mounting semiconductor elements having a structure that does not require an adhesive, and its use. The present invention relates to a substrate for mounting semiconductor devices.

〔従来技術とその課題〕[Conventional technology and its issues]

近年、半導体素子を基板に実装する技術の進歩は急激で
ある。特にテープ自動配線接続(TapeAutoma
ted Bonding 、以下TABと略称する)は
集積回路を形成された半導体素子(以下ICチップと略
称する)を半導体素子実装用の回路基板にワイヤボンデ
ィングなしで、接続する技術であり、500〜600個
と云う多数の外部接続配線数を有するICチップの配線
接続を一度に可能にするため、高密度の実装技術が必要
とされている現在、研究開発が活発に進められている。
In recent years, there has been rapid progress in technology for mounting semiconductor elements on substrates. Especially tape automatic wiring connection (TapeAutoma)
ted Bonding (hereinafter abbreviated as TAB) is a technology that connects semiconductor elements formed with integrated circuits (hereinafter abbreviated as IC chips) to a circuit board for mounting semiconductor elements without wire bonding. Currently, research and development are actively progressing as high-density packaging technology is required to enable wiring connections for IC chips having such a large number of external connection wirings at once.

TABに用いる基板の方式には二層構造と二層構造があ
るが、いずれの構造においても第4図a(二層構造)お
よび第4図b(二層構造)に示されるように、ICチッ
プが実装される位置において樹脂フィルム3は穴あけ加
工を施さねばならない、これは、耐熱性の樹脂フィルム
といえども、ICチップ実装時の温度に耐えることが困
難であるからである。
There are two types of substrates used for TAB: two-layer structure and two-layer structure. In both structures, as shown in Figure 4a (two-layer structure) and Figure 4b (two-layer structure), IC The resin film 3 must be perforated at the location where the chip is to be mounted. This is because even a heat-resistant resin film has difficulty withstanding the temperature at which the IC chip is mounted.

しかして、穴あけ加工は、二層構造と三層構造において
、それぞれ異なる方式で行われている。
Therefore, drilling is performed using different methods for the two-layer structure and the three-layer structure.

二層構造のTABにおいては、樹脂フィルムはエツチン
グ加工により穴あけ加工が行われている。
In a TAB with a two-layer structure, holes are formed in the resin film by etching.

しかしながら、耐熱性の樹脂フィルムの場合、このエツ
チングは困難である。−船釣にTABに利用される耐熱
性の樹脂フィルムは耐薬品性にもすぐれているからであ
る。これに対して、三層構造のTABにおいては、あら
かじめ型抜きやパンチング等により穴あけ加工を行うこ
とができるので、従来技術においては、もっばら、この
三層構造のTABが半導体の実装用に用いられてきた。
However, in the case of heat-resistant resin films, this etching is difficult. - This is because the heat-resistant resin film used for TAB for boat fishing also has excellent chemical resistance. On the other hand, in the case of a TAB with a three-layer structure, holes can be formed in advance by die-cutting, punching, etc., so in the conventional technology, this TAB with a three-layer structure is mainly used for mounting semiconductors. I've been exposed to it.

しかしながら、この三層構造のTABは、−船釣に銅箔
と耐熱性の樹脂フィルムを接着剤で貼り合わせたもので
あり、耐熱性の低い接着剤を用いているために、TAB
としての耐熱性は樹脂フィルムの耐熱性よりも低下する
という大きい問題点を有している。このために、接着剤
を不要にする構造のTABによる実装技術の開発が望ま
れており、従来は、接着剤が不要である二層構造におい
て、耐熱性の樹脂フィルムのエンチング技術が盛んに検
討されてきた。
However, this three-layer structure TAB is made by bonding copper foil and heat-resistant resin film with adhesive, and because it uses an adhesive with low heat resistance, TAB
A major problem is that the heat resistance of the resin film is lower than that of the resin film. For this reason, it is desired to develop mounting technology using TAB with a structure that eliminates the need for adhesives, and conventionally, in the case of two-layer structures that do not require adhesives, technology for etching heat-resistant resin films has been actively studied. It has been.

本発明者等は、エツチング技術そのものを不要にする技
術を開発すべく、TABの実装工程を鋭意検討した結果
、ICチップの実装において、必要とされる熱負荷に耐
えるには、500 ’Cにおいて、約1秒の耐熱性を有
すれば、実質的に充分であり、該耐熱性は特定の絶縁層
を形成することにより与えられることを見出した0本発
明はかかる知見に基づきなされるに到ったものである。
In order to develop a technology that eliminates the need for etching technology itself, the inventors of the present invention have carefully studied the TAB mounting process. It has been found that a heat resistance of about 1 second is substantially sufficient, and that this heat resistance can be provided by forming a specific insulating layer.The present invention was made based on this knowledge. This is what happened.

〔課題を解決するための手段〕[Means to solve the problem]

すなわち、本発明は、 銅箔上に、無機物質からなる絶縁層を形成したことを特
徴とする半導体素子の実装用基板に好適な銅箔、であり
、また、 銅箔上に、無機物質からなる絶縁層を形成し、さらに咳
vA縁層の上に樹脂フィルム層を形成してなることを特
徴とする半導体素子の実装用基板、である。
That is, the present invention provides a copper foil suitable for a substrate for mounting a semiconductor element, characterized in that an insulating layer made of an inorganic substance is formed on the copper foil, and a copper foil made of an inorganic substance is formed on the copper foil. This is a substrate for mounting a semiconductor element, characterized in that an insulating layer is formed thereon, and a resin film layer is further formed on the edge layer.

〔発明の開示〕[Disclosure of the invention]

本発明は、第1図に例示したように、銅箔1上に、無機
物質からなる絶縁層2を形成したことを特徴とする半導
体素子の実装用基板に好適な銅箔、であり、また、第2
図Cに示したように、銅箔1上に、無機物質からなる絶
縁N2を形成し、さらに該絶縁層の上に樹脂フィルム層
3を形成してなる半導体素子の実装用基板、である。
As illustrated in FIG. 1, the present invention is a copper foil suitable for a substrate for mounting semiconductor elements, characterized in that an insulating layer 2 made of an inorganic substance is formed on a copper foil 1, and , second
As shown in FIG. C, this is a substrate for mounting a semiconductor element, in which an insulating layer N2 made of an inorganic material is formed on a copper foil 1, and a resin film layer 3 is further formed on the insulating layer.

本発明の無機物質からなる絶縁層の形成に用いることの
できる材料は酸化物、窒化物、炭化物等であり、具体的
には、酸化珪素、酸化アルミ、酸化チタン、酸化タンタ
ル、窒化珪素、窒化アルミ、炭化珪素等の電気絶縁性の
材料を有効に用いることができる。絶縁層を銅箔上に形
成するには、物理的な手法、化学的な手法のいずれでも
よい。
Materials that can be used to form the insulating layer made of an inorganic substance of the present invention include oxides, nitrides, carbides, etc., and specifically, silicon oxide, aluminum oxide, titanium oxide, tantalum oxide, silicon nitride, and nitride. Electrically insulating materials such as aluminum and silicon carbide can be effectively used. In order to form the insulating layer on the copper foil, either a physical method or a chemical method may be used.

しかして、物理的な手法としては、スパッタリングや薄
着があり、化学的な手法としては、化学気相堆積法(C
VD法)、プラズマ化学気相堆積法(PCVD法)のよ
うな気相成長、ゾルゲル法、浸漬法のように液状の材料
からの薄膜形成等の手法を有効に用いることができる。
However, physical methods include sputtering and thin deposition, and chemical methods include chemical vapor deposition (Chemical vapor deposition).
Methods such as vapor phase growth such as VD method), plasma chemical vapor deposition method (PCVD method), sol-gel method, and thin film formation from a liquid material such as immersion method can be effectively used.

該絶縁層はTABプロセスにおける熱負荷に耐える性質
、好ましくは上記したごとり500℃において1秒間の
耐熱性を付与するものであり、この為に、絶縁層の厚み
としては、0.01〜20us 、好ましくは、0.1
〜15μm程度である0本発明は、一つには、以上説明
したように、銅箔1の上に、無機物質からなる絶縁層2
を形成した半導体素子の実装用基板に好適な銅箔である
The insulating layer has the property of being able to withstand the heat load in the TAB process, preferably providing heat resistance for 1 second at 500°C as described above, and for this reason, the thickness of the insulating layer is 0.01 to 20 us. , preferably 0.1
As explained above, the present invention has an insulating layer 2 made of an inorganic material on a copper foil 1.
This copper foil is suitable for mounting substrates for semiconductor devices formed with .

以下、本発明の好ましい実施の態様を第2図において説
明する。第2図aにおいて、銅箔1上に0.1〜15μ
−程度の膜厚に、無機物質からなる絶縁層2を形成する
。これが本発明の一つたる半導体素子の実装用基板に好
適な銅箔であるが、さらに、該絶縁層上に、第2図すに
示すように、樹脂フィルムのワニスや樹脂フィルムの前
駆体等3゜を塗布厚み、10〜200μm、好ましくは
15〜150μm、特に好ましくは、20〜100μm
程度の厚みに塗布形成する。該樹脂フィルムのワニスや
樹脂フィルムの前駆体等を常法に従い硬化処理し、第2
図Cに示したような樹脂フィルム3を該絶縁層上に形成
する。これは、本発明の他の一つたる半導体素子の実装
用基板である。なお、絶縁層は必ずしも銅箔上に一面に
設ける必要はなく、第3図に示したように、場合によっ
ては、ICチップが実装される位置に対応する部分だけ
に設けてもよい。
Hereinafter, a preferred embodiment of the present invention will be explained with reference to FIG. In Figure 2 a, 0.1 to 15 μm is applied on copper foil 1.
An insulating layer 2 made of an inorganic material is formed to a thickness of approximately -. This is a copper foil suitable for a substrate for mounting a semiconductor element, which is one of the aspects of the present invention. Furthermore, as shown in FIG. 2, a resin film varnish, a resin film precursor, etc. 3° is the coating thickness, 10 to 200 μm, preferably 15 to 150 μm, particularly preferably 20 to 100 μm.
Coat and form to a certain thickness. The varnish of the resin film, the precursor of the resin film, etc. are cured according to a conventional method, and the second
A resin film 3 as shown in Figure C is formed on the insulating layer. This is a substrate for mounting a semiconductor element, which is another aspect of the present invention. Note that the insulating layer does not necessarily need to be provided all over the copper foil, and may be provided only on the portion corresponding to the position where the IC chip is mounted, as shown in FIG. 3, depending on the case.

第2図dは本発明の半導体素子の実装用基板から、IC
チップを実装できるように銅箔1の不必要な部分を常法
により除去したところの断面図であり、本発明の接着剤
を不要にする構造のTABの断面構造を表している。第
2図eは最終的に、ICチップ4を実装した時の断面図
であり、本発明の適用例を示しているのである。なお、
第1図ならびに第2図において、縦、横のサイズは任意
に選択されており、とくに断面図においては、説明を容
易にするために、材料の厚みを拡大強調していることに
注意されたい。
FIG. 2d shows an IC
This is a cross-sectional view of the copper foil 1 in which an unnecessary portion has been removed by a conventional method so that a chip can be mounted, and represents the cross-sectional structure of the TAB of the present invention, which has a structure that eliminates the need for an adhesive. FIG. 2e is a cross-sectional view when the IC chip 4 is finally mounted, and shows an example of application of the present invention. In addition,
Please note that the vertical and horizontal sizes in Figures 1 and 2 have been arbitrarily selected, and the thickness of the material has been enlarged and emphasized for ease of explanation, especially in cross-sectional views. .

本発明は、その趣旨において、銅箔ならびに好ましくは
耐熱性の樹脂フィルムについては特に、限定されるもの
ではない、従来技術において、利用されている材料であ
れば、如何なるものをも有効に用いることができる。た
とえば、銅箔においては、圧延w4箔、電解iV3等を
有効に用いることができる。また、好ましくは耐熱性の
樹脂フィルムとしてはポリイミド、ポリアミドイミド、
ポリパラバン酸、ポリヒダントイン、ポリベンゾイミダ
ゾール等の樹脂フィルムのワニスや樹脂フィルムの前駆
体等を有効に利用できる。
In its spirit, the present invention is not particularly limited to the copper foil and preferably the heat-resistant resin film; any materials that have been used in the prior art may be effectively used. Can be done. For example, as for copper foil, rolled W4 foil, electrolytic IV3 foil, etc. can be effectively used. Preferably, the heat-resistant resin film is made of polyimide, polyamideimide,
Resin film varnishes, resin film precursors, etc. such as polyparabanic acid, polyhydantoin, and polybenzimidazole can be effectively used.

〔実施例〕〔Example〕

以下、実施例により、本発明の実施の態様をさらに詳細
に説明する。
Hereinafter, embodiments of the present invention will be explained in more detail with reference to Examples.

(実施例1〕 35μmの圧延銅箔の上に、絶縁層として酸化珪素をス
パッタリングにより膜厚0.2μm形成し、第1図に示
したような半導体素子の実装用基板に好適な銅箔を得た
。この炭化珪素層の上から、ポリイミドの前駆体である
ポリアミド酸ワニスを100μmの塗布厚みに塗布した
のち、イミド化により硬化させ、耐熱性のポリイミドフ
ィルムを形成し第2図Cに示したような半導体素子の実
装用基板を得た。ついで、fINを塩化第二鉄溶液を用
いてエツチング除去して、回路を形成した。
(Example 1) Silicon oxide was formed as an insulating layer on a 35 μm rolled copper foil to a thickness of 0.2 μm by sputtering to form a copper foil suitable for mounting a semiconductor element as shown in FIG. A polyamic acid varnish, which is a precursor of polyimide, was applied onto the silicon carbide layer to a thickness of 100 μm, and then cured by imidization to form a heat-resistant polyimide film, as shown in Figure 2C. A substrate for mounting a semiconductor element was obtained.FIN was then etched away using a ferric chloride solution to form a circuit.

該回路にICチップを実装する代わりに、500℃に加
熱した銅の棒を1秒間接触させて、耐熱性をテストした
。テスト後、耐熱性フィルムには外観ならびに電気的な
性質の劣化は全く観察されなかった。すなわち、本発明
の半導体素子の実装用基板はICチップの実装に充分耐
える耐熱性を有していることが確認された。
Instead of mounting an IC chip on the circuit, heat resistance was tested by contacting it with a copper rod heated to 500° C. for 1 second. After the test, no deterioration in the appearance or electrical properties of the heat-resistant film was observed. That is, it was confirmed that the substrate for mounting a semiconductor element of the present invention has sufficient heat resistance to withstand mounting of an IC chip.

〔実施例2〕 テトラエトキシシラン溶液を35μmの電解銅箔上に塗
布し、溶媒除去後、加熱焼成して酸化珪素とするゾルゲ
ル法により膜厚10pmの酸化珪素薄膜を絶縁層として
形成し半導体素子の実装用基板に好適な銅箔を得た。該
薄膜上にポリイミドのクロルフェノール溶液を75μm
の塗布厚みに塗布したのち、溶媒を加熱除去して、耐熱
性のポリイミドフィルムを形成し半導体素子の実装用基
板を得た。ついで、銅箔をエツチング除去して、回路を
形成した。実施例!と同じ耐熱性のテストを実施し、同
様の結果を得たことにより、ゾルゲル法で形成される酸
化珪素も本発明において、有効であった。
[Example 2] A silicon oxide thin film with a thickness of 10 pm was formed as an insulating layer by a sol-gel method in which a tetraethoxysilane solution was applied on a 35 μm electrolytic copper foil, the solvent was removed, and the silicon oxide was formed by heating and baking to form a semiconductor device. We obtained a copper foil suitable for the mounting board. A 75 μm thick polyimide chlorophenol solution was applied onto the thin film.
The solvent was removed by heating to form a heat-resistant polyimide film to obtain a substrate for mounting a semiconductor element. The copper foil was then etched away to form a circuit. Example! The same heat resistance test was conducted and similar results were obtained, indicating that silicon oxide formed by the sol-gel method was also effective in the present invention.

〔発明の効果〕〔Effect of the invention〕

以上の実施例から明らかなように、本発明は接着剤を不
要にする構造の基板を提供するもので、従来のTAB技
術において、困難であった耐熱性の樹脂フィルムのエツ
チングを不要とするものであるから、今後のTAB技術
を大幅に進展させ、高密度実装技術にきわめて、貢献す
るものであり、その産業上の利用可能性は極めて大きい
と言わざるを得ないのである。
As is clear from the above examples, the present invention provides a substrate with a structure that eliminates the need for adhesives, and eliminates the need for etching a heat-resistant resin film, which was difficult in conventional TAB technology. Therefore, it must be said that this technology will significantly advance TAB technology in the future and contribute significantly to high-density packaging technology, and its industrial applicability is extremely large.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の実施の態様の一例を示す断面図である
。第2図a〜第2図eは本発明をTABに使用するとき
の実施の態様の一例を示す断面図である。第3図は本発
明の別の実施の態様を示すものであって断面構造を模式
的に表した断面図であり、第4図aおよび第4図すは従
来技術による例を示す断面図である0図中、1−・−・
−・−・−胴箔、2・−・・−・・−・・・・無機物質
の絶縁層、3−−−−−−−−−・−耐熱性の樹脂フィ
ルム、3゛   樹脂フィルムのワニスや樹脂フィルム
の前駆体等、4−・−・・−・・−ICチップ、5−・
・−・−・・・−接着剤、を示す。 第1図 第2図 第3図 第4図
FIG. 1 is a sectional view showing an example of an embodiment of the present invention. FIGS. 2a to 2e are cross-sectional views showing an example of an embodiment when the present invention is used in a TAB. FIG. 3 shows another embodiment of the present invention, and is a sectional view schematically showing the cross-sectional structure, and FIG. 4a and FIG. In a certain 0 diagram, 1-・-・
−・−・−Body foil, 2・−・・−・・−・・Insulating layer of inorganic material, 3−−−−−−−−・−Heat resistant resin film, 3゛ Resin film Precursors for varnish and resin films, etc., 4-・--・--IC chips, 5--
・-・-・・・-Indicates adhesive. Figure 1 Figure 2 Figure 3 Figure 4

Claims (2)

【特許請求の範囲】[Claims] (1)銅箔上に、無機物質からなる絶縁層を形成したこ
とを特徴とする半導体素子の実装用基板に好適な銅箔。
(1) A copper foil suitable for a substrate for mounting semiconductor devices, characterized in that an insulating layer made of an inorganic substance is formed on the copper foil.
(2)銅箔上に、無機物質からなる絶縁層を形成し、さ
らに該絶縁層の上に樹脂フィルム層を形成してなること
を特徴とする半導体素子の実装用基板。
(2) A substrate for mounting a semiconductor element, characterized in that an insulating layer made of an inorganic substance is formed on a copper foil, and a resin film layer is further formed on the insulating layer.
JP21043288A 1988-08-26 1988-08-26 Board for semiconductor element mounting use Pending JPH0260137A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21043288A JPH0260137A (en) 1988-08-26 1988-08-26 Board for semiconductor element mounting use

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21043288A JPH0260137A (en) 1988-08-26 1988-08-26 Board for semiconductor element mounting use

Publications (1)

Publication Number Publication Date
JPH0260137A true JPH0260137A (en) 1990-02-28

Family

ID=16589224

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21043288A Pending JPH0260137A (en) 1988-08-26 1988-08-26 Board for semiconductor element mounting use

Country Status (1)

Country Link
JP (1) JPH0260137A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0260138A (en) * 1988-08-26 1990-02-28 Mitsui Toatsu Chem Inc Board for semiconductor element mounting use

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5848954A (en) * 1981-09-18 1983-03-23 Sumitomo Electric Ind Ltd Substrate for tape carrier type integrated circuit
JPH01133729A (en) * 1987-11-19 1989-05-25 Nitto Denko Corp Conductive laminated film
JPH0260138A (en) * 1988-08-26 1990-02-28 Mitsui Toatsu Chem Inc Board for semiconductor element mounting use

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5848954A (en) * 1981-09-18 1983-03-23 Sumitomo Electric Ind Ltd Substrate for tape carrier type integrated circuit
JPH01133729A (en) * 1987-11-19 1989-05-25 Nitto Denko Corp Conductive laminated film
JPH0260138A (en) * 1988-08-26 1990-02-28 Mitsui Toatsu Chem Inc Board for semiconductor element mounting use

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0260138A (en) * 1988-08-26 1990-02-28 Mitsui Toatsu Chem Inc Board for semiconductor element mounting use

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