JPH0260196B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention (Field of Industrial Application) The present invention relates to a display control device that can change display colors for each screen in a multi-window display system.

(Prior Art) High-performance display devices such as workstations are required to have a function of displaying a plurality of screen images on a single display device (for example, a CRT) by dividing or overlapping the screens.

In order to display multiple screen images on one CRT, multiple screen images are developed in a memory called a window buffer, and these screen images are superimposed or displayed simultaneously to create an image of the entire display screen. is temporarily created in a memory called a frame buffer. Conventionally, multi-window display was realized by reading out the memory in synchronization with raster scanning of a CRT. The display screen image is created by transferring the whole or part of the screen image developed on the window buffer to a designated area on the frame buffer.

Several methods have been proposed for realizing these functions, depending on the physical arrangement of the frame buffer and the window buffer. However, as mentioned above, when all or part of a plurality of screen images developed on a window buffer is displayed, the images are displayed in whole or in part according to the position of the images within the display screen and the state of overlap between the screen images. By transferring to the frame buffer, it can be assumed that all display screen images are created using the same method logically.

FIG. 1 is a diagram showing an example of a conventional method, in which 1 is a window buffer in which multiple screen images are expanded, 11, 12, and 13 are each screen image, and 11
1, 121, 131 are screen images 11, 12,
13 partial images, 2 frame buffers, 2
1, 22, 23 are partial images 111, 121,
131 is the partial display image transferred to frame buffer 2, 3 is the CRT synchronization signal generation circuit
CRTC, 31 is an access control signal line for frame buffer 2, 32 is a synchronization signal line for CRT, 4 is transfer hardware for transferring image data from window buffer 1 to frame buffer 2, 5 is transfer hardware
It is a CRT.

When the display screen image is not changed, such as updating the screen image, enlarging/reducing or scrolling a partial image, simply change the frame buffer 2.
is simply read out according to the CRT's raster scanning timing.

On the other hand, if it becomes necessary to change the display screen image, for example, if the contents of the screen image 12 are modified, the partial image 121 is transferred to the area of the partial display image 22 on the frame buffer. In addition, in the example of FIG. 1, the partial display image 22
Since the partial display image 21 is superimposed on the screen image 11, the partial image 111 must be transferred again to the area of the partial display image 21 on the frame buffer even if there is no change in the contents of the screen image 11.

Alternatively, in a region of the partial display image 22 of the screen image 12 that is other than the part that is not visible due to the superimposition of another partial display image, the partial image 121 corresponding to that region is cut out and a window is displayed. Must be transferred from Batu Hua.

To perform the above operations, the transfer time _t of the image from the window buffer 1 to the frame buffer 2, the size of the partial image, the position on the window buffer or frame buffer, and the other partial images are required. It takes time t _n to manage data related to partial images, such as the relationship of overlap with other images.

Even if the image transfer is performed using hardware,
_tt requires approximately 40 to 100ms/screen.

For color display, if one screen is composed of multiple planes and multiple partial images are superimposed, it takes a very long time to update the display screen.

For example, if one screen is composed of 4 planes and 10 partial images overlap, and if the screen located at the lowest position is rewritten, the partial image overlapping the partial image is retransferred. ,
It takes 1.6 to 4.0 seconds to update the display screen.

Furthermore, if there are many screens, the amount of information to be managed will be enormous, and the control time will also be extremely long.

Therefore, in a workstation or the like, if a single processor performs anything other than display control, the performance will drop significantly. For this reason, a processor dedicated to display control is generally provided.

(Problems to be Solved by the Invention) As described above, the conventional method has the drawback of requiring a processor dedicated to display control, hardware for image data transfer, and the like. Also,
For color display, a color lookup table (not shown in FIG. 1) is generally provided on the output side of the frame buffer 2.

However, the lookup table affects the entire display screen, so if you rewrite the lookup table to change the color of a partial image, the color of the entire display screen will change, not just that partial image. It has the disadvantage of changing.

Structure of the Invention (Means for Solving the Problems) In order to solve these drawbacks, the present invention reads out a plurality of areas on the wind buffer simultaneously, and outputs the signals read out from the areas to a specific lookup table. The connection relationship between the wind buffer and lookup table is dynamically switched so that

(Operation) By doing this, only the color of a partial image in a part of the display screen can be changed by changing the contents of the lookup table.

(Embodiment) Fig. 2 shows the configuration of an embodiment of the present invention, in which 6 is a multi-window control unit MWU;
Display only a partial image of the screen image on CRT
The image is read out in synchronization with the display timing of the CRT so that it is displayed at a predetermined position above, and superimposition control between multiple partial images is performed. 61 is the above
A window buffer access signal line consisting of an address signal line and a control signal line for the MWU to access the window buffer; 62 is a window selection signal line that notifies the identifier of the window to be displayed; 1a, 1b, 1c and 1d are window buffers that can be read simultaneously, 1
1a, 11b, 11c, 11d are screen image planes 111a, 111b, 111 constituting one screen image 11 (not shown);
c, 111d is a partial image plane specified within the screen image plane, 12a, 1
2b is screen image 12 (not shown in the figure)
Screen image plane 121a, 1 that constitutes
21b is a partial image plane specified within the screen image plane, 13a is a screen image plane that constitutes the screen image 13 (not shown), and 131a is a partial image specified within the screen image plane. plane, 7 is the output data line from the wind buffer,
70 is wind buffer 1a, 1b, 1c, 1d
711 is an output signal line of the selection circuit 70;
a, 7b, 7c, 7d, and 7e are lookup tables, 712 is the output signal line of the lookup table, and R, G, and B are D/A converters corresponding to red, green, and yellow signal lines, respectively. be.

CRTC3 generates a frame buffer access signal, notifies it to MWU6 via signal line 31, and at the same time
It generates a synchronization signal for the CRT and notifies it to the CRT 5 via the signal line 32. The frame buffer access signal is a two-dimensional coordinate expressed by X and Y of a certain point on the display screen. generated.

The following data regarding the screen (hereinafter referred to as screen address data) is set in the MWU6.

Data regarding the screen image on the window buffer 1, including the position and size of the screen image within the window buffer 1, the number of planes and plane numbers of the screen image that composes the screen image, and the data to be cut out within the screen image. Data related to a partial image, such as the position and size of the partial image within the screen image; Data related to a partial display image in which the partial image is displayed on a CRT screen, such as the position of the partial display image on the display screen, and the partial display image. Overlapping relationship between CRT
Plain buffer address (X,
The MWU 6 determines in which partial display image on the window buffer Y) exists in accordance with the address data. The frame buffer address (X, Y) is converted to the window buffer address using screen address data regarding the screen image including the corresponding partial display image.

If two or more partial images overlap on the display screen, check the frame buffer address (X,
Y) to the window buffer address is executed.

In this way, when partial display images overlap on the display screen, addresses on multiple window buffers are converted from one frame buffer address (X, Y), but the overlap between multiple partial images According to the data representing the relationship, only the address on the window buffer of the partial image that overlaps the top most among the addresses (X, Y) on the display screen is selected and notified to the window buffer 1.

In the example of FIG. 2, the partial display image 115 overlaps 125 at the point (X, Y) position, so
The address on the window buffer of the partial image 111 is connected to the signal line 61 on the window buffer 1 (1a,
1b, 1c, and 1d). At the same time, the MWU notifies the lookup table selection circuit 70 via the signal line 62 that the partial image 111 has been selected.

As a result, four partial image planes 111a, 111b, 111c, and 111d constituting the partial image 111 are simultaneously read out from the window buffer 1, and the lookup table selection circuit 7
0 is notified of the output of that plane.

The selection circuit 70 selects the entry of the lookup table assigned to the screen image 11 including the partial image 111 and the four partial image planes 1 according to the information notified through the signal line 62.
11a, 111b, 111c, and 111d are combined.

In the example of FIG. 2, the partial image 111 has four planes 111a, 111b, 111c, and 111d.
Therefore, a 4-bit signal is notified to the selection circuit 70, and the 16 entries represented by the 4 bits are sent to the lookup tables 7a, 7b, 7.
c, 7d and 7e.

Also, the partial image 112 has two planes 1
21a and 121b, a 2-bit signal (planes 1a and 1b only) is notified to the selection circuit 70, and four entries represented by the 2 bits are selected as the lookup table for the partial image 121.

The information necessary for the above-described mapping of partial image planes and lookup tables, which is performed for each partial image, is set in the lookup table selection circuit 70 in advance. The actual switching of the correspondence is performed by a signal indicating the currently selected window identifier notified from the MWU via the signal line 62.

The output signal of the lookup table entry accessed on the output signal line 711 is output on the signal line 712.
The signals are sent to D/A converters R, G, and B, respectively, and converted into red, green, and blue analog signals and sent to the CRT 5.

In the above explanation, for the sake of simplicity, the number of planes in the wind buffer is 4, the number of screen images to be developed on the window buffer is 3, and the number of lookup tables is 5. Of course.

Figure 3 shows the multi-window control unit MWU6.
In this specific example, 311 is an x-coordinate signal line indicating the coordinate value in the horizontal direction (hereinafter referred to as the X direction) of the display screen on the CRT, and 312 is the coordinate value in the vertical direction (hereinafter referred to as the Y direction). The y-coordinate signal line 313 indicates a value, and the display clock signal line 313 indicates a sample timing signal for each dot on the display screen on the CRT.The above three signals are generated from the CRTC3.

611, 612, 613, and 614 specify the position on the display screen where the partial image is displayed.
Points (X ₁ , Y ₁ ) and (X ₂ , Y ₂ ) are set,
The two-dimensional coordinates (X, Y) on the current display screen synchronized with the raster scan of the CRT (hereinafter referred to as frame buffer address) represented by signal lines 311 and 312 are compared with the set value, and the frame buffer is determined. 621, 622, 623, 62, which is an address window detection circuit AWC that detects that the address (X, Y) exists within the area where the partial image is displayed on the display screen;
4 is an address conversion circuit that indicates that the frame buffer address (X, Y) exists within the area defined by (X ₁ , Y ₁ ) and (X ₂ , Y ₂ ) set in each circuit AWC. The window detection signal lines 651, 652, 653, 654 notify the window detection signal lines 624, 622, 623, 62 (described later).
Address translation circuits ATC, 671, 672, and 67, each activated in 4 and generating the address of the partial image developed on the window buffer.
3,674 is address conversion circuit ATC651,6
52, 653, and 654 are address signal lines that notify the addresses on the window buffer that are output respectively, and 68 is address signal line 671, 672, and 67.
This is a multiplexer circuit that selects one of 3,674 images depending on the degree of overlapping of partial images on the display screen.

To operate this, screen address data is set in each of the circuits described above in advance. Specifically, the position and size of the screen image within the window buffer, the number and plane number of the screen images that make up the screen image, the position and size of the partial image within the screen image, and the like for each screen image. Address conversion circuit ATC65
1,652, 653 and 654, respectively.

Address window detection circuit detects the position of the partial display image on the display screen (on CRT)
Set to AEC611, 612, 613 and 614 respectively.

The overlapping relationship between the partial display images on the display screen is set in the multiplexer circuit 68.

For example, screen address data regarding screen image 11 is set in address window detection circuit 611 and address conversion circuit 651, and screen address data regarding screen images 12 and 13 is similarly set in address window detection circuit 612, 613 and address conversion circuit 652, 653 respectively. Further, data representing the overlapping relationship on the display screen of the partial display images obtained from each of the three screen images is set in the multiplexer circuit 68.

The frame buffer addresses (X, Y) generated by CRTC3 are synchronized with the raster scanning of the CRT and sequentially represent the addresses of points to the right from the upper left point on the display screen.

Partial image 1 set in the address window detection circuit AWC611 as raster scanning progresses
When it is detected that the frame buffer address (X, Y) is included within the range of addresses (X ₁ , Y ₁ ) and (X ₂ , Y ₂ ) indicating the display area No. 11, the window detection signal line 621 is address conversion circuit ATC
651 is activated to perform address translation.

The address conversion circuit ATC651 includes each plane 11a of the screen image 11 on the window buffer,
Each partial image 1 of 11b, 11c and 11d
Addresses for the same points in 11a, 111b, 111c and 111d are generated simultaneously, and the address data is notified to multiplexer circuit 68 via address signal line 671.

Since window detection signal lines 621, 622, 623, and 624 are connected to the multiplexer circuit 68, the most A signal line that notifies the address of the partial image overlapping above is selected and connected to the signal line 61. Data representing the partial image selected by the multiplexer circuit 68 is carried on the signal line 62.

As raster scanning further progresses, partial images 111 and 121 overlap on the display screen, and 111
When the CRTC3 generates a frame buffer address (X, Y) corresponding to the area where It is detected that it is within the area of images 111 and 121.

As a result, window detection signal lines 621 and 622
activates the address translation circuits 651 and 652, respectively, to perform address translation.

The address conversion circuits ATC651 and 652 are for each plane 11a, 11b, 11 of the screen image 11.
Each partial image 111a, 11 of c and 11d
Address data of the same point in 1b, 111c and 111d and each plane 12 of the screen image 12
Each partial image 121a, 121b of a, 12b
Generate address data for the same point within each.

Two address data are on the address signal line 671
and 672, the multiplexer circuit 68 is notified. The multiplexer circuit is informed that partial image 111 is above 121, so it selects address signal line 671 and connects it to signal line 61. Furthermore, data (window identifier) indicating that the selected partial image is 111 is placed on the signal line 62.

Thereafter, as the raster scan progresses, the same operation as above is performed to read the partial images on the window buffer at the timing corresponding to the dots on the CRT display screen, and at the same time control the overlapping relationship between the partial images. At the same time, multiple screen images are displayed on the display screen.

In the above description, for the sake of simplicity, the number of address window detection circuits, address conversion circuits, and signal lines provided corresponding to the number of circuits is four, but the number can be increased as necessary.

FIG _. 4 shows a specific embodiment of the address window detection circuit 611, ₆₁₂ , ₆₁₃ or ₆₁₄ in FIG. These are the values of the x and y coordinates of the two vertices (X ₁ , Y ₁ ) and (X ₂ , Y ₂ ) of

CMP1 is a comparison circuit that compares the x-coordinate value of the frame buffer address notified by the signal line 311 with _X1 , CMP2 is a comparison circuit that compares the x-coordinate value of the frame buffer address with _X2 , CMP3
is the y-coordinate value of the frame buffer address and
A comparison circuit that compares Y ₁ , CMP4 a comparison circuit that compares the y-coordinate value of the frame buffer address and Y ₂ , and Q ₁ , Q ₂ , Q ₃ and Q ₄ the above comparison circuits.
CMP1, CMP2, CMP3, CMP4 output terminals,
R ₁ , R ₂ , R ₃ , R ₄ are reset terminals of the comparison circuit, and when these terminals are turned on, output terminals Q ₁ , Q ₂ , Q ₃ ,
The state of Q ₄ is off. D ₁ and D ₂ are the two data input terminals of the comparison circuit, CLK1, CLK2,
CLK3 and CLK4 are the clock terminals of the comparator circuit, and the two data input terminals _D1 are connected to each other at the rising edge of the timing pulse applied to these terminals.
and the value given to D ₂ and output the result to the output terminal. 6111, 6113 are
AND gate, 6112 is an OR gate, FF1 is a flip-flop, CLK5 is the clock terminal of flip-flop FF1, signal lines 6114, 61
Reference numerals 15, 6116, 6117, and 6118 are output signal lines from the address window detection circuit AWC, which correspond to the window detection signal lines of each address window detection circuit in FIG.

The comparison circuit is activated by the clock on the display clock signal line 313, and the frame buffer address (X, Y) and the coordinate values (X ₁ , Y ₁ ) and (X ₂ , _Y2 ).

Comparison circuit CMP1 compares X and _X1 , CMP2 compares X and
_CMP3 compares Y and _Y1 , and CMP4 compares Y and _Y2 . Specifically, the value of the terminal D ₁ and the value of the terminal D ₂ are compared, and when D ₂ ≦D ₁ , the output terminal Q ₁ , Q ₂ , Q ₃ , or Q ₄ of each comparison circuit is turned on.

Here, it is assumed that the window (not shown) includes two vertices (X ₁ , Y ₁ ) and (X ₂ , Y ₂ ).

Therefore, the comparison circuits CMP2 and CMP4 actually compare X and X ₂ +1, and Y and Y ₂ +1, respectively.

In the example shown in Figure 4, when output terminals Q ₁ and Q ₃ of comparison circuits CMP1 and CMP3 are both on, the frame buffer address (X, Y) represents a dot included in the window. So AND
The conditions of circuit 6111 are satisfied.

As a result, flip-flop FF1 is set,
Its output terminal Q is turned on. As the CRT raster scan further progresses, the frame buffer address (X, Y) at which CRTC3 is generated changes, and when that address (X, Y) indicates the position of a dot outside the window, either CMP2 or CMP4 is Output terminal Q ₂
Or Q ₄ is turned on. As a result, OR circuit 6
Condition 112 is satisfied and flip-flop FF1
is reset, and the output terminal Q of flip-flop FF1 changes from on to off, and changes from off to on. In other words, the on state of the terminal Q of FF1 indicates that the frame buffer address (X, Y) is within the window, and conversely, the on state of the terminal Q indicates that the frame buffer address (X, Y) is outside the window. represent.

The condition that Q ₂ of CMP2 and Q ₃ of CMP3 are both on is the condition that the value of X of the frame buffer address (X, Y) is X≧X ₂ +1 and the value of Y is Y ₁ ≦Y≦Y ₂ corresponds to This condition indicates that the Y coordinate value of the frame buffer address (X, Y) is within the vertical region of the window, but the X coordinate value is outside the window's horizontal direction. The situation is AND
This corresponds to the on state of the output signal line 6117 of the circuit 6113.

The state of the signal line 6117 is transmitted to the address conversion circuit 651, which will be described next, so that when the frame buffer address (X, Y) again indicates the coordinate value of a dot in the window, the value of Y will change to the previous Y value. Used to notify that the value has been increased by 1.

A signal line 6114 notifies the address translation circuit ATC of starting address translation processing.

A signal line 6115 instructs the address conversion circuit ATC to stop address conversion processing.

A signal line 6116 notifies address conversion circuit ATC of address conversion timing for each display dot.

The signal line 6117 notifies that the y-coordinate value of the frame buffer address will be incremented by +1 the next time the address conversion circuit is activated.

The signal line 6118 notifies that the scanning of the window in the y direction is completed and that the y coordinate value of the frame buffer address has returned to the initial value when the address conversion circuit ATC is activated next time.

The operation results of the address window detection circuit described above are the output signal lines 6114, 6115, 6
The address conversion circuit ATC 651 is notified by 116, 6117 and 6118.

FIG. 5 shows one of the partial images 111 in the screen image 11 developed on the window buffer 1.
This is a diagram for explaining the generation of addresses on the window buffer 1 for two partial image planes 111a, where (x _s , y _s ) is one of the two vertices of one screen image plane 11a in the screen image 11. One is the two-dimensional coordinate value of the position that is the origin.

Now, for ease of explanation, one wind buffer 1a, 1b, 1c, 1d of wind buffer 1
are one-dimensional continuous addresses, and a two-dimensional screen image is secured in a continuous address area in one window buffer plane of the window buffer 1.

a _s corresponds to the two-dimensional coordinates (x _s , y _s ) of the first vertex of one screen image plane 1a (or 1b, 1c, 1d) of the screen image 11,
This is the actual one-dimensional address on the wind buffer.

Similarly, (x _p , y _p ) are the two-dimensional coordinates of the first vertex of the partial image plane 111a, and (x _{o ,} y p ) are the two-dimensional coordinates of the first vertex of the partial image plane 111a.
y _o ) is the two-dimensional coordinate of the second vertex of the partial image, and (x _e , y _e ) is the screen image plane 11a.
is the two-dimensional coordinate value of the second vertex of .

The frame buffer address (X, Y) where CRTC3 occurs is the first vertex on the window (X ₁ , Y ₁ )
Wind buffer 1a address when it matches
The address conversion circuit ATC generates a _s , and in the same way, the coordinate values (X, Y) representing the dot on the window are sequentially converted into window buttons until they match the second vertex (X ₂ , Y ₂ ) on the window. The procedure for converting into the one-dimensional address a(x _i , y _i ) of the address space 1a will be explained below.

x _p -x _s = d _x (dot)...(1) x _p -x _s +1 = d _y (dot)...(2) If
The one-dimensional address a(x _p , y _p ) on the wind buffer corresponding to the two-dimensional coordinates (x _p , y _p ) of the vertex of is expressed by the formula
It can be expressed as (3).

a (x _p , y _p ) = a _s + d _y × (y _p − y _{s )} + d _{x …} (3) Similarly, the two-dimensional coordinates ( The one-dimensional address a(x _i , y _p ) on the window buffer of x _i , y _p ) can be expressed by equation (4).

a (x _i , y _p ) = a _s + d _y × (y _p − y _s ) + d _x + i …(4) Find the number of the line containing the point (x _p , y _p ) or (x _i , y _p ). 0, the address a(x _i , y _j ) on the window buffer of the point (x _i , y _j ) on the j-th line can be expressed by equation (5).

a(x _i , y _j )=a _s +d _y ×(y _p +j−y _s )+d _x +i
(5) Equation (5) uses variables i and j to represent the one-dimensional address on the window buffer of an arbitrary dot in the partial image. Equation (5) can be expressed as Equation (6) from Equations (1) and (2).

a(x _i , y _j )=a _s +(x _e −x _s +1) ×(y _p −y _s +j) +(x _p −x _s )+i = a _s +(x _e −x _s +1) ×(y _p −y _s ) +(x _e −x _s +1)×j+(x _p −x _s )+i …(6) Here, if the address of the wind buffer 1a is managed two-dimensionally The address of the expression
It is possible to express it as (7) and (8).

a _x = x _p + i ... (7) a _y = y _p + j ... (8) It is very easy to realize the functions of equations (7) and (8) with hardware. Equation (6) can also be implemented in hardware relatively easily.

Note that equations (6), (7), and (8) represent the window buffer address of one plane, but for color display, it is necessary to read multiple window buffers at the same time. . To do this, it is necessary to set the number of planes that make up the screen image and the identifier of that plane in the address conversion circuit ATC for each window.

Then, at the same time as the window buffer address conversion circuit ATC expressed by equation (6) or equations (7) and (8) is generated, a mechanism is provided to notify the window buffer of the designation information of the window buffer to be read in parallel.

FIG. 6 shows an example of the hardware configuration for realizing the above formula (6), in which the address conversion circuit ATC65 is used.
1 shows details of the first embodiment. The same applies to other address conversion circuits ATC652, 653 and 654.

80 is a counter that generates the value of the variable i of the fifth term on the right side of equation (6), and 81 is the partial image plane 11a.
A register 82 is a register for setting the x-coordinate value x _p of the two-dimensional coordinate value ₍ x _p , y _p ) of the first vertex of the screen image plane 11a;
A _register 83 sets the x coordinate value _{x e of} the two-dimensional coordinate value (x _e , y _e ) of the second vertex of the screen image plane 11a _; to 1
84 is a register for setting the y-coordinate value _{y p of} the two-dimensional coordinate value (x _p , y _p ) of the first vertex of the partial image plane 111a, 85 is a screen image plane A register for setting the negative value of the y coordinate value y _s of the two-dimensional coordinate value (x _s , y _s ) of the first vertex of the screen image plane 11 a - y _s , 86 is the two-dimensional coordinate value of the first vertex of the screen image plane 11 a A register for setting the one-dimensional address a _s on the window buffer corresponding to the coordinate value (x _s , y _s ); 97 is a register for setting the number of planes composing the screen image and the identifier of the plane; 87, 88 ,89,
90, 94, 95, and 96 are adders, 91 is a multiplier, 92 is a register with a gate function that accumulates the output of the adder 90, and 93 is the timing for changing the variable j in the third term on the right side of equation (6). This is the timing circuit that generates the .

In the operation of the address conversion circuit ATC shown in FIG.
The values set in and 86 are constants that are independent of the sample timing of display dots generated by CRTC3.

Therefore, when a predetermined constant is set in the register, the adders 87, 88, 89, 94 and the multiplier 91 operate independently with respect to the sample timing of the display dot.

The timing circuit 93 generates a timing pulse only when a pulse is applied through the signal line 6117 of the address window detection circuit AWC 611 shown in FIG. The timing pulse is generated when the frame buffer address (X, Y) generated by the CRTC3 leaves the address range in the horizontal direction (x direction) of the window on the display screen. For expressions in which Y) is within the window address range, the value of Y at that address is +1
has been done.

That is, the third term of equation (6) is realized by the adder 90, the gated register 92, and the timing circuit 93. Since the adder 95 has already calculated the first, second, and fourth terms on the right side of equation (6), the adder 95 calculates the first to fourth terms on the right side of equation (6). The result of the calculation is obtained.

By adding i corresponding to the output value of the counter 80 to the calculation result by the adder 96, the calculation of equation (6) is completed. Note that the number of planes constituting the screen image and the identifier of the plane are added to the adder 96 and output to the signal line 671.

Counter 80 is an address window detection circuit
AWC611 signal lines 6114, 6115, 61
16. The counter 80 is connected to the signal line 6
The counter 115 is reset when the signal line 6114 is turned on, and counting starts with the signal line 6114 turned on.

Counting is signal line 6116 (also signal 313)
This is done by a sample timing signal (pulse) of display dots generated by CRTC3 applied through the display dot.

The address signal a(x _i , y _j ) of the window buffer 1, which is the output of the adder 96, is sent to the multiplexer circuit 68 via the signal line 671 together with the plane identifier to be read out at the same time. The circuit 68 adds signals necessary for window buffer access to the address signal a(x _i , y _j ), performs window buffer access, and reads a predetermined dot from the window buffer.

Similarly, the frame buffer address (X, Y) generated by CRTC3 changes, and if the windows overlap, control signals from multiple address window detection circuits AWC are transmitted to signal lines 621 and 621.
22, 623 or 624. The signal is notified to the address conversion circuit ATC.

Each address conversion circuit ATC performs address conversion according to preset data regarding the layout positions of screen images and partial images, and generates one-dimensional addresses a(x _i , y _j ) on the window buffer, respectively. . The addresses a(x _i , y _j ) are each sent to a multiplexer circuit 68. The circuit selects only the one-dimensional address a(x _i , y _j ) on the window buffer corresponding to the window located at the top according to preset data defining the relationship of overlapping windows.

As described above, a signal necessary for window buffer access is added to the address signal a(x _i , y _j ) and sent to the window buffer, and a predetermined dot is read out.

In the above explanation, for simplicity, the number of address window detection circuits AWC and address translation circuits ATC is assumed to be four, but since the scale of these circuits is small, by implementing LSI, several dozen or more of these circuits can be reduced to one. It is possible to fit it into one chip.

Further, as for the circuits shown in the embodiments of the address window detection circuit AWC and the address translation circuit ATC, it goes without saying that other circuit systems may be used as long as the same functions can be realized. When the address of the window buffer 1 is managed as a two-dimensional address, address conversion is expressed by equations (7) and (8), and the hardware for realizing this is simple and need not be shown by example.

FIG. 7 shows an embodiment of the lookup table selection circuit 70 in FIG.
A latch circuit 71d temporarily holds the state of the signal line 7, and is provided for each window displayed on the display screen. 72a, 72b, 72c, and 72d are mapping circuits that associate the values temporarily held in the latch circuits 71a, 71b, 71c, and 71d with the lookup table entries for each window;
f is a decoding circuit that decodes the identifier of the selected window notified by the signal line 62, 73 is a selection signal line that notifies each latch circuit and mapping circuit of the output signal of the decoding circuit 71f, and 711 is a lookup table access. It is a signal line.

In FIG. 2, when the partial image 111 is selected, the output signal line 7 of the wind buffer is 4.
Latch circuits 71a, 71b, 7
Notify 1c, 71d.

On the other hand, the decoding circuit 71f
It is determined that the bit data is a dot included in the partial image 111, and the partial image 111 is
latch circuit (here 71a) assigned for
) latches the 4-bit data. Further, a mapping circuit 72a generates a lookup table entry corresponding to the 4-bit value latched in the latch circuit 71a. In this example, since the partial image consists of four planes, up to 16 lookup table entries are set in the mapping circuit 72a.

The lookup table entries output from the mapping circuit 72a are transferred to the lookup tables 7a, 7b, 7c, 7d, and 7e (shown in FIG. 2) via the lookup table access signal line 711.
is notified and the value of the corresponding entry is read.
The values are D/corresponding to red, green, and blue shown in Figure 2.
The signal is input to the A converter and causes the CRT to emit light.

In the above explanation, the number of latch circuits and mapping circuits is four, but it goes without saying that in reality, a larger number may be prepared depending on the number of windows.

Effects of the Invention As explained above, according to the present invention, one
For multi-window display systems that simultaneously display part or all of screen images on a CRT, it is possible to update, move, enlarge, change the overlapping state of displayed images, scroll, etc.
We provide a display control device that can reconfigure the display screen in response to a change in display content by simply changing the information set in the hardware, and at the same time allocate a lookup table for each window.
It is possible to switch in synchronization with the raster scanning of the CRT and by detecting a coincidence between the scanning timing and the window position. As a result, operations such as moving, enlarging, reducing, changing superimposition, scrolling within a window, etc. for each window can be performed very easily, and there is an advantage that even faster processing is possible. Another advantage is that the combination of display colors for a particular window can be changed independently.

Therefore, by applying the present invention to a device having a high-performance display device such as a workstation, it is expected that the performance of the device will be improved and the price will be significantly reduced.

[Brief explanation of drawings]

FIG. 1 shows an example of a conventional system, FIG. 2 shows a configuration of an embodiment of the present invention, and FIG. 3 shows a specific embodiment of a multi-window control unit MWU.
FIG. 4 shows a specific embodiment of the address window detection circuit, and FIG. 5 shows the generation of a window buffer address for one partial image plane in a partial image in the screen image developed on the window buffer. FIG. 6 shows an embodiment of an address conversion circuit, and FIG. 7 shows an embodiment of a lookup table selection circuit. 1... Wind buffer, 11, 12, 13...
... Screen image, 111, 121, 131 ... Partial image, 2 ... Frame buffer, 21, 2
2, 23... Partial display image, 3... CRTC,
31...Frame buffer access control signal line,
32...Synchronization signal line, 4...Hardware for image data transfer, 5...CRT, 6...Multi-window control unit, 61...Window buffer address signal line, 62...Window selection signal line,
1a, 1b, 1c, 1d...Wind buffer that can be read simultaneously, 11a, 11b, 11c, 11
d...Screen image planes forming the screen image 11, 12a, 12b...Screen image 12
A screen image plane 111a, 1 that constitutes
11b, 111c, 111d, 121a, 121
b, 131a...partial image plane, 13a
... Screen image plane constituting the screen image 13, 7... Output data line, 70... Lookup table selection circuit, 711... Selection circuit 70
Output signal lines 7a, 7b, 7c, 7d, 7e...
...Lookup table, 712...Lookup table output signal line, R, G, B...D/A
Converter, 311...x coordinate signal line, 312...
...Y coordinate signal line, 313... Display clock signal line, 611, 612, 613, 614... Address window detection circuit AWC, 621, 622, 6
23,624...window detection signal line, 651,
652, 653, 654...address conversion circuit,
671, 672, 673, 674...Address signal line for notifying the window buffer address, 68
...Multiplexer circuit, CMP1, CMP2,
CMP3, CMP4... Comparison circuit, Q ₁ , Q ₂ , Q ₃ ,
Q ₄ ... Comparison circuit CMP1, CMP2, CMP3,
Output terminal of CMP4, D ₁ , D ₂ ... Input terminal of comparison circuit, CLK1, CLK2, CLK3, CLK4 ... Clock terminal of comparison circuit CMP1, CMP2, CMP3, CMP4, R ₁ , R ₂ , R ₃ , R ₄ ... Comparison circuit CMP
1. CMP2, CMP3, CMP4 reset terminals,
6111, 6113...AND gate, 6112
...OR gate, FF1...flip-flop,
CLK5...FF1 clock terminal, 6114,6
115, 6116, 6117, 6118...Output signal lines of address window detection circuit AWC, (x _s ,
y _s )...the first vertex of the screen image plane,
(x _p , y _p )...the first vertex of the partial image, (x _o ,
y _o )...Second vertex of partial image, (x _e , y _e )
...The second vertex of the screen image plane, a _s ...
The value displayed as the primary address of (x _s , y _s ), 80...
Counter of variable i, 81, 82, 83, 84, 8
5, 86, 97...Register, 87, 88, 8
9, 90, 94, 95, 96...adder, 91...
...multiplier, 92...gated register, 93...
...Timing circuit, 71a, 71b, 71c, 7
1d...mapping circuit, 71f...decoding circuit.

Claims (1)

[Claims] 1. In order to simultaneously display a plurality of screen images on a display device of the type that performs raster scanning and displays images in dots, it has a window buffer that stores a plurality of screen images developed into dots. In a multi-window display system, a timing at which a control device of the display device raster scans the position on the display screen of a window displayed on the display screen of a display device of the type that performs the raster scan and displays images in dots; , generate an address on the window buffer where the screen image developed on the window buffer to be displayed in the window is placed, or arrange multiple windows so that they overlap on the display screen. (b) means for generating multiple addresses on the window buffer of multiple screen images corresponding to multiple applicable windows; b. among the addresses generated in step a above, the highest address on the display screen; c. means for reading out the contents of the window buffer specified by the address selected in b. above; d. means for accessing a lookup table for displaying a color corresponding to the content according to the content; e. preparing the lookup table for each window; means for detecting a coincidence between the position of the window on the display screen and the timing of raster scanning by the control device of the display device, and detecting the window located at the highest position on the display screen among the means of b. 1. A multi-window color display control device, comprising: means for switching lookup tables prepared for each window, which are to be accessed according to contents read from a window buffer.