JPH0260224A - Monostable multivibrator circuit - Google Patents

Abstract

PURPOSE:To allow a pulse width to be highly precise by inputting the output of a gate circuit to the clock input terminal of a counter, connecting the output to the input terminal of an R-S flip flop and the reset input terminal of the counter and deciding the pulse width through the use of a clock signal. CONSTITUTION:The counter 14 counts the rise of an output signal (e) inputted from the gate circuit 13. When the logical value of the output signal (f) goes to '0', the output signal (b) of a NAND gate 16 goes to a logical value '1' and accordingly the output signal (c) of a NAND gate 15 goes to the logical value '1'. Consequently, the gate circuit 13 is closed, and the supply of the clock signal to the counter 14 stops. On the other hand, the output signal (f) of the counter 14 is fed back to an MR terminal and the counter 14 is reset. By such an operation, the pulse of the pulse width tw, which is decided by the counted value of the prescribed clock, is outputted from the output terminal 18 of R-SFF12 as the output signal (b).

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a logic circuit used in an information processing device,
In particular, it relates to a monostable multivibrator circuit that creates pulses with a constant pulse width.

[Conventional technology]

There is a monostable multivibrator circuit that outputs a pulse with a constant pulse width. The pulse width in this monostable multivibrator circuit is set by appropriately setting the values of capacitance C and resistance R.

FIG. 3 shows such a monostable multivibrator circuit. First, close switch S and power supply V
Charge the capacitance C with . In this state, the switch S is opened (and the charge charged in the capacitance C is discharged through the resistor R, so the discharge waveform is
As shown in the figure, it becomes a voltage signal determined by the time constant of CR. When this waveform is input to the gate 11 and the input voltage is higher than the threshold voltage Vth of the gate 11, the output X becomes a logical value "1". On the other hand, when it is lower than the threshold voltage Vth, the output X is a logical value “0”
As a result, a pulse with a pulse width tw is obtained.

That is, the pulse width tw is determined by the time when the discharge waveform A of CR exceeds the threshold voltage Vth, and a desired pulse width can be obtained by appropriately selecting the values of the capacitance C and the resistance R.

[Problem to be solved by the invention]

However, in such conventional monostable multivibrator circuits, the pulse width is set by appropriately selecting the values of the resistance R and capacitance C.
Pulse width fluctuations are very large. Further, the threshold voltage vth changes due to manufacturing variations in the gate 11, temperature, power supply voltage, etc., and on the other hand, the capacitance C and the resistance R also change due to manufacturing variations, temperature, etc. Therefore, the pulse width of the output X will also change due to these fluctuations.

In particular, when trying to obtain a wide pulse width, the value of CR must be set large, but in that case, the discharge waveform A
The threshold voltage V
Variations in t h % capacitance C and resistance R will cause large variations in pulse width.

Furthermore, since the conventional monostable multivibrator circuit uses a capacitance C, it is very difficult to integrate it into an LSI.

[Means to solve the problem]

The monostable multivibrator circuit of the present invention inputs a trigger signal and outputs a pulse signal with a predetermined pulse width.
Consists of an S flip-flop, a counter for determining a predetermined pulse width based on a clock signal, and a gate circuit for providing a clock signal to the counter, and a trigger signal is input to one input terminal of the R-S flip-flop. The output of the gate circuit is input to the clock input terminal of the counter, and the output of the counter is connected to the other input terminal of the R-S flip-flop and the reset input terminal of the counter.

[Effect]

Thereby, the pulse width of the pulse signal becomes a pulse width corresponding to the time from when the trigger signal is input until the clock signal of the count value determined by the counter is counted.

Absolute excuse] Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. The monostable multivibrator circuit of the present invention includes an R-S flip-flop 12 (hereinafter simply referred to as R-5FF12), a gate circuit 13, and a counter 14. R-
The 5FF 12 is composed of two 2-input NAND games (15 and 16), which feed back their output signals to each other. The trigger signal a is input to the input terminal 17, and a pulse signal with a predetermined pulse width is output from the output terminal 18.

The gate circuit 13 is a 2-input AND circuit, and R-3FF
The output signal C from the output terminal of the 12 Nant gates 15 and the clock signal d are input.

Then, when the logical values of both signals c and d are "1", an output signal e whose logical value is "1" is output. Therefore, when the signal C has the logical value "1", the output signal e becomes the clock signal d, and the signal C has the logical value "0".
When this is the case, the output signal e becomes a signal with a logical value of "0".

The counter 14 inputs the signal e and counts the number of clocks when the signal e is the clock signal d. That is,
It is configured such that the rise of the input waveform of the signal e input to the input terminal CLK is counted, and when the count value reaches a predetermined value, the output signal f becomes a logical value "0".

Note that the output signal f is input to the MR terminal i, and the output signal f
When becomes the logical value "0", the counter 14 is reset and the output signal f becomes the logical value "1" again.

FIG. 2 is a timing diagram showing signal waveforms at various parts of the monostable multivibrator circuit of the present invention shown in FIG.

Now, point 1. Assume that the trigger signal a is given as a logical value "0". When the counter 14 is in the reset state, its output signal f is a logic value "1", and the output signal C of the Nant gate 15 is a logic value "0." Therefore, the output signal of the Nant gate 16 is The logical value is "1". Therefore, the output signal of the Nant gate 15, which is the feedback signal from the Nant gate 16, is in the state of logic value "1", and the logic value "
Since the trigger signal a of 0'' is given, the output signal C of the Nant gate 15 has a logical value of 1.

On the other hand, when the output signal C becomes the logic value "1", the Nant gate 16 which is feeding back the output signal C has the logic value "1" since the output signal f also has the logic value "1". 0''.

Since the output signal C with the logical value "1" is input to the gate circuit 13, the gate circuit 13 opens and the clock signal d
is output to the counter 14 as an output signal e,
Become.

The counter 14 counts the rising edge of the input output signal e. Now, assuming that the predetermined count value is 8, the counter 14 finishes counting eight clock signals d at a time t.
1, the logical value of the output signal f is set to "0". When the logic value of the output signal f becomes "0", the output signal S of the Nant gate 16 becomes the logic value "1", and thereby the output signal C of the Nant gate 15 becomes the logic value "0". Therefore, the gate circuit 13 is closed and the supply of the clock signal d to the counter 14 is stopped. On the other hand, as the logic value of the output signal f of the counter 14 becomes "0", it is fed back to the MR terminal, the counter 14 is reset, and the output signal f becomes the logic value "1" again. .

By the above operation, the output terminal 18 of R-3FF l2
From then on, the pulse width 1. is determined by the count value of the predetermined clock of the counter 14. The pulses will be output as the output signal. Generally, the period of the clock signal can be created with high precision, so the pulse width t can also be created with high precision.

〔Effect of the invention〕

As described above, according to the present invention, the pulse width is determined not by capacitance and resistance, but by using the tarok signal.
The pulse width can be made highly accurate. Furthermore, since it is configured with gate circuits, NAND circuits, etc., it can be easily integrated into an LSI.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is an explanatory diagram of the operation of the monostable multivibrator circuit of the present invention,
Figure 3 shows a conventional monostable multi-byte. FIG. 4, which is a block diagram of the break circuit, is an explanatory diagram of the operation of a conventional example. 12...R-S flip-flop, 13...
...Gate circuit, 14...Counter, 15.1
6... Nantes gate, 17... Input terminal, 18... Output terminal. Applicant: NEC Corporation Representative: Patent Attorney: Umeo Yamauchi Figure 1 Figure 2 t.

Claims (1)

[Claims] an R-S flip-flop that receives a trigger signal and outputs a pulse signal with a predetermined pulse width; a counter that determines a predetermined pulse width of the pulse signal based on a clock signal; and a gate circuit for applying the trigger signal to the R-
The output of the gate circuit is input to one input terminal of the S flip-flop, and the output of the counter is input to the other input terminal of the R-S flip-flop and the reset input terminal of the counter. A monostable multivibrator circuit characterized by being connected to.