JPH0260275B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a schedule display device that displays preset schedule information.

[Prior art and its problems] In recent years, a plurality of pieces of schedule information consisting of time data and message data have been stored in a memory in advance, and an alarm sound is generated each time the scheduled time in the memory is reached. A schedule display device has been put into practical use. By heart,
Since the memory for storing schedule information is limited in the number of schedules that can be stored, by erasing old schedules, new schedules can be written, and the memory can be used effectively. For example, Japanese Patent Application Laid-Open No. 55-33646 discloses that a plurality of alarm time memories are provided, and each alarm time memory stores data indicating whether or not to erase the stored alarm time when an alarm matches. A technique is disclosed in which a memory is provided, and in the case of an alarm time that is used only once, the alarm time is cleared when the alarm times coincide and an alarm notification is made.

However, if you store the start time of a meeting, meeting time, etc. as alarm time information in the scheduler, and you do not notice that the alarm time has arrived (for example, if you turn off the alarm sound or Even if you are far away and cannot hear the alarm sound, or even if you know that it is the alarm time by the alarm sound,
There may be times when you cannot make it in time due to other errands, etc. In such cases, check the alarm time and the errand when you notice that there is a meeting, meeting, etc., and when the other errand is finished. However, if the alarm time and schedule contents are erased when the alarms match, as in the above-mentioned published technique, confirmation cannot be made, and there is a drawback that the start time, meeting time, location, etc. are lost.

On the other hand, if you keep the alarm time even when the alarm time arrives, this problem will be solved, but you will not be able to store a new schedule, and you will have to search all schedules with a switch etc. This has the drawback of requiring troublesome switch operations such as erasing unnecessary schedules and storing new schedules.

[Object of the Invention] This invention was made in view of the above-mentioned circumstances, and its purpose is to make it possible to check the schedule later without erasing it even if the schedule times match, and to To provide a schedule display device capable of saving memory without wasting memory.

[Summary of the Invention] In order to achieve the above-mentioned object, the present invention makes it possible to check schedule information even after the schedule times match, and erases unnecessary schedule information when the date changes. The gist of this is that we have done so.

[Configuration of Embodiment] The present invention will be specifically described below based on an embodiment shown in the drawings. FIG. 1 shows a block circuit diagram of an electronic wristwatch to which the present invention is applied. This electronic watch operates using an 8-bit microprogram control system, and the ROM (read-only memory) 1 stores microprograms that control all operations of this electronic watch and uses microinstructions.
Outputs OP, DO, and NA in parallel. Here, the microinstruction OP is input to the instruction decoder 2, which decodes it and gives it to the R/W input terminal of the RAM (random access memory) 3 as a data read/write command. It is given as an operation instruction to the S input terminal of . Also, the microinstruction DO is sent via the data bus.
The data is input to the Addr input terminal of the RAM 3 as address data, and is input as numerical data to the DI2 input terminal of the calculation section 4, and further input to the address control section 5. Further, the microinstruction NA is next address data input to the address control unit 5, and the address data output from the address control unit 5 is applied to the Addr input terminal of the ROM1.

The RAM 3 has a configuration including a number register, an arithmetic register, etc., and is used for timekeeping processing, key input processing, arithmetic processing, etc., and executes data writing and reading operations under the control of the instruction decoder 2.
Then, the data read from the DO output terminal of RAM3 is transferred to the DI1 input terminal and DI2 of the calculation unit 4.
The signal is applied to the input terminal and displayed on the display section 7 via the display control section 6. The calculation unit 4 executes various calculations according to calculation instructions from the instruction decoder 2, and the calculation result data is stored in the RAM 3.
It is given to the DI input terminal and read into RAM3. Further, when executing a jump calculation, the calculation section 4 outputs a signal indicating the presence or absence of data as a result of the calculation and a signal indicating the presence or absence of carry occurrence, respectively, and supplies them to the address control section 5 to convert the address of the ROM 1. Further, a 16Hz time clock obtained by frequency dividing the reference clock signal from the oscillator 8 by the frequency dividing circuit 9 is input to the address control section 5, and according to this 16Hz signal, 1/ The time measurement process is executed by interrupting once every 16 seconds. Further, the predetermined frequency signal output from the frequency dividing circuit 9 is given to a timing generator 10, which causes the timing generator 10 to output various timing signals and supply them to each circuit. Further, the key code output from the key input section 11 is given to the DI2 input terminal of the calculation section 4.

Figure 2 shows the main part of RAM 3. In addition to clock data (time, date), system control data, etc., RAM 3 has a data memory area that the user can freely write in according to key operations. have. That is, the RAM3 shown in FIG.
N, L, P, I, F _a , K registers and a data memory M are provided.

This data memory M is capable of writing schedule information corresponding to each row address area. Here, the schedule information is composed of time data (month, date, hour, and minute) and message data (alphabet characters, etc.). Therefore, each row of data memory M has three areas M _o1 ,
It is divided into M _o2 and M _o3 (n: an integer of 1 or more),
A flag is set in area M _o1 to set whether to retain or delete the schedule information of that row after the schedule time elapses, and in area M _o2 , time data constituting the schedule information and area M Message data is stored in _o3 . Note that the contents of the data memory M are rearranged and stored in ascending order of month, date, and time when schedule information is newly registered, changed, or added. The N register is a register in which the next notification number is stored, and the next notification number is the schedule number (numeric data corresponding to the row address of data memory M) for specifying the schedule information to be notified next, and the schedule time. Each time, the value is incremented by 1. Further, the L register is a register in which the total number of schedule information (total data number) stored in the data memory M is stored. In addition, the P register is a display page pointer for specifying the display page when displaying one page of schedule information on the display 7, the I register is an address register for data memory M, and the Fa register indicates when an alarm is being reported. flag register,
Register K is a register in which the first schedule number of the previous day is stored.

FIG. 3 shows the configuration of the display section 7. The display section 7 is composed of a liquid crystal display device, and a main digital display section 7-1 consisting of an 8-digit day-shaped display is provided in the lower region of the display screen, and a main digital display section 7-1 is provided in the upper region. In addition to the matrix display section 7-2 which displays alphabetical characters etc. with 5 digits, there is also a sub-digital display section 7-2 which consists of a 4-digit day shape display.
3 is provided. Also, in the upper right corner of the display screen, you can select whether to store or retain the schedule information as it is when the schedule time has elapsed, based on the contents set in advance in area M _o1 of data memory M.
A protect (PR) indicator (retention mark) and a delete (DE) indicator (remaining mark) are provided to clearly indicate whether to erase. In addition, the A indicator and P indicator are marks indicating AM and PM.

In addition, as shown in Figure 3, this electronic watch is equipped with various switches _S1 to _S4 , as well as a numeric keypad and alphanumeric keys (not shown) used for inputting schedule information, etc. ing.

[Operation of Example] FIG. 4 is a general flow diagram schematically showing the overall operation of this electronic timepiece. This general flow is started every time a 16 Hz clock is output from the frequency dividing circuit 9 or when a key is input. First, at step T1, the system enters a standby state (HALT) until there is a request for clock timing or key input. Now, when the key code corresponding to the operation key is output from the key input unit 11, a corresponding key processing program is specified, and key processing and display processing (step T2), which will be described later, is executed according to the operation key. Afterwards, the process returns to step T1. Furthermore, at the timing of timing, the process proceeds to step T3, where a timing process is performed. That is, a predetermined unit of data is added to the clock data stored in the RAM 3 to obtain the current time, and this is transferred to the RAM 3 and stored as new clock data. When such time counting processing is completed, an alarm processing (step T4), which will be described later, is executed, and then it is determined whether or not there is a date carry (step T5). If the result of the clock processing is now 00:00:00 a.m. and the date has been changed by the date carry output, the schedule re-editing process (step T6), which will be described later, will be executed and the process will proceed to step T7. If there is no ``day'' carry, the program proceeds directly to step T7, where it is checked whether there is a ``year'' carry. If the change is made to the next year, an initialization process (step T8) is executed in which the value of the N register that stores the next notification number is set to the initial value "1", and the process proceeds to the display process (step T9). If there is no yearly carry, the display processing at step T9 is performed, and then the process returns to step T1.

FIG. 5 is a flowchart for explaining the specific contents of the alarm processing (step T4) shown in FIG. First, in step T4-1, the RAM
It is determined whether the alarm flag "1" is set in the FA register in 3, that is, whether the alarm is sounding, and if the alarm is not sounding, the process goes to step T4.
Proceed to -2. Here, by comparing the contents of the N and L registers, it is determined whether the next notification number is greater than or equal to the total number of scheduled data.
Here, if the next notification number is greater than or equal to the total number of data, no schedule information is stored after that, so the alarm processing ends at this point, but if the next notification number is less than the total number of data,
Since the schedule information is still stored in the data memory M, the process advances to the next step T4-3.
Here, the current month, day, hour, and minute data obtained by the above-mentioned timekeeping process and the month, day, hour, and minute data of the next notification schedule specified by the next notification number in the N register and read out from the data memory M. are compared. As a result, if the two data do not match, the alarm time has not yet been reached, and the alarm processing ends. However, when a match is detected and the alarm time has arrived, the alarm flag "1" is set in the F _A register. is set (step T4-
4). Next, after the buzzer is driven and an alarm sound is generated, the alarm timer is cleared and started, and its timing operation is started (step T4-
5, T4-6). On the other hand, if it is detected in step T4-1 that an alarm is being sounded, it is determined whether a certain period of time (20 seconds) has elapsed since the alarm sound was generated based on the time measurement data of the alarm timer, and a certain period of time (20 seconds) has passed since the alarm sound was generated. The alarm sound continues to be generated until the time elapses (step T4-7). After a certain period of time has elapsed, the buzzer is stopped and the value of the N register is incremented by 1 (steps T4-8, T4
-9). Therefore, the contents of the next notification number are incremented each time the alarm time arrives, and the next notification schedule is specified.

FIG. 6 is a flowchart for explaining the specific contents of the schedule re-editing process (step T6) shown in FIG. First, when this flow is entered with a date carry, the values of the K and N registers are compared (step T6-1). Here, when the date is changed by outputting a day carry, the first schedule number of the date before the change (for example, the previous day) is stored in the K register. Therefore, in step T6-1, it is determined whether the next notification number exceeds the first schedule number of the previous day. Initially, the first schedule number of the previous day is smaller than the next notification number, so if it is greater than or equal to the next notification number, an error occurs and the schedule reediting process is invalidated, but if it is smaller than the next notification number, step T6-2
The value of the K register is transferred to the I register. Then, of the area M _o1 in the data memory M, the area specified by the value of the I register
The setting flag is read from M _I1 (in this case, the area corresponding to the first schedule information), and it is determined whether it is "1" or not (step T6).
-3). In this case, "1" corresponds to holding schedule information, and "0" corresponds to erasing schedule information, so if it is currently set to erase, the data memory M specified by the value of the I register Area M _I1 (M _I1 , M _I2 , M _I3 )
The contents (initial schedule information) are all cleared (step T6-4). When the first schedule information is cleared in this way, the process proceeds to the next step T6-5, where a transfer process is executed in which the second and subsequent schedule information of the previous day is incremented by one address, and thereby the data memory M
The contents of are filled in one by one to fill in the empty areas. When the contents of the data memory M have been edited based on the deletion of the first schedule information in this way, the process proceeds to the next step T6-6, where the next notification number in the N register is decremented by 1, and the total number of data in the L register is is reduced by -1. And next step T
At step 6-7, it is checked whether the contents of the I register have exceeded the value of the N register. Now, if the previous day's schedule number is 1, the value of the N register is subtracted by 1 as described above, so that the value of the I register matches the next notification number, but if it is 2 or more, the next notification number is This is detected in step T6-7 and the process returns to step T6-3.
In this case, since the contents of the data memory M have been packed by the above transfer process (step T6-5), the second schedule information is transferred and stored in the address area where the first schedule information was stored. As a result, the contents of M _I1 preset for the second schedule information are checked. Even in this case
If M _I1 = 0 (erasure), the same processing as described above (steps T6-4 to T6-7) is executed and the second
The th schedule information is deleted, and all subsequent schedule information is filled in one by one. If the number of schedule information for the previous day is two, the content of the I register matches the value of the N register, but if it is three or more, the process returns to step T6-3. In this case, since the third schedule information is stored in the address area where the first schedule information was stored, it is checked whether the third schedule information is to be deleted or retained. If M _I1 = 1 (maintained) now,
Proceeding from step T6-3 to step T6-8,
After incrementing the value of the I register by 1, the process directly advances to step T6-7.
Therefore, in the case of retention, the schedule information will not be deleted, but will be retained as the schedule information for the next year. If the number of schedule information for the previous day is 3, the contents of the I register match the value of the N register at this point, but if it is 4 or more, the process returns from step T6-4 to step T6-3. Processing depending on whether the fourth schedule information is retained or deleted is executed in the same manner as described above. In this way, when it is detected at step T6-7 that the contents of the I register have become equal to or greater than the value of the N register, the process advances to step T6-9.
The next broadcast number in the N register is transferred to the K register. As a result, the next day, the re-editing process is performed from the schedule information specified by the value of this K register. As a result of the schedule re-editing process described above being executed every time the date is changed, the schedule information for the previous day that is set to be deleted will be deleted, but the other schedule information will be updated to next year's schedule information. is retained as.

FIG. 7 is a flowchart showing specific details of the key processing and display processing (step T2) shown in FIG. FIG. 8 is a diagram showing display states that change according to key operations. First, when entering this flow, it is checked whether the switch S3 has been operated (step T2-1). Here, the switch S3 is a mode switch for switching between the normal time display mode and the schedule mode. When this switch S3 is operated, the mode switching process (step T2-2) is executed, and the mode is switched between the normal time display mode and the schedule mode. Switching is performed. If the schedule mode is canceled and the mode is switched to the normal time display mode, the process proceeds from step T2-3 for determining the mode to step T2-4, where the current time obtained by the timekeeping process is displayed. When the normal time display mode is switched to schedule, the process advances from step T2-3 to step T2-5, where the next notification number in the N register is transferred to the display page pointer P, and the data specified by that value is transferred. The schedule information in memory M is read out and displayed (step T2-6). Figure 8 A and B are switch S3
FIG. 8A corresponds to the normal time display mode, FIG. 8B corresponds to the schedule mode, and the display contents are changed according to the mode by operating the switch S3. In this case, when switching to schedule mode, the next schedule information will be displayed, so that, for example, the next schedule will be "July 1st, 3:45, TOKYO".
It can be confirmed that

However, in this schedule mode,
When switch S4 is operated, step T2-7
When it is detected that the switch S4 has been operated, the process proceeds to step T2-8, where the mode is determined. Here, if the mode is the normal time display mode, the operation of the switch S4 is invalidated, but if the mode is the schedule mode, the process advances to step T2-9 and switching between the write mode and the read mode is performed. Therefore, the switch S4 functions as a write/read changeover switch in the schedule mode, and when it is switched to the read mode, this is detected in step T2-10 and the process proceeds to step T2-11. Then, processing for editing the contents of the data memory M is performed. That is,
When the write mode is released, the contents of the data memory M are edited so that the schedule information in the data memory M is arranged in ascending order of month, date, and time. Therefore, whenever schedule information is newly set, changed, or added to data memory M, the contents of data memory M are edited and rearranged in ascending order of month, day, and minute. It will be done.

Further, when the switch S1 is operated, it is detected in step T2-12 and the process is executed in step T2-12.
-13, where it is determined whether the mode is scheduled. Here, if the switch S1 is operated in the normal time display mode, the operation of the switch S1 is disabled, but if the switch S1 is operated in the schedule mode, the step T
At step 2-14, it is checked whether it is in write mode. now,
If it is read mode, the next step T2-15
Then, the value of the display page pointer P and the total number of data in the register are compared. If the number of displayed pages is smaller than the total number of data, proceed to step T.
Proceed to 2-18, and the value of the display page pointer P is +
1, but if the number of displayed pages is still less than the total number of data, the schedule information of the page specified by the value of the display page pointer P is read from the data memory M and displayed (step T2-19, T2-17). Therefore, in the schedule read mode, initially the schedule information of the page corresponding to the next notification number is automatically displayed, but in this state, the switch S
Each time you operate 1, the value of the display page pointer P increases.
As a result of being incremented by 1, future schedule information will be sequentially displayed each time the switch S1 is operated. FIGS. 8B, C, and D show a state in which the display contents are changed one page at a time in response to the operation of this switch S1. Therefore, switch S1 comes to function as a page change key. However, when the schedule information of the last page is displayed, the switch
1 is operated, the process advances from step T2-15 to step T2-18, where the value of the display page pointer P is incremented, and as a result, the number of displayed pages exceeds all the data, and as a result, the process proceeds from step T2-15 to step T2-18. Step T2-19 to T2-20
, and a blank display appears (see Figure 8E).
In this state, if the switch S1 is operated once more, the process moves from step T2-15 to step T2-1.
6, the display page pointer P is set to "1", and the schedule information for the first page is thereby displayed (step T2-1).
7). In this way, the contents of data memory M are displayed cyclically by operating switch S1.
It becomes possible to confirm each schedule information written in the data memory M in advance.

Next, the operation when writing schedule information will be explained. New registration of schedule information,
When adding or changing, first operate switch S4 to set the schedule write mode (step T2-9). In this write mode, when switch S1 is operated, this is detected in step T2-14 and the process proceeds to step T2-21.
Page change display processing similar to steps T2-15 to T2-20 is performed. Therefore, in the case of new registration or additional registration, switch S1 is operated to search for an empty page (blank display). In addition, in the case of a change, the page to be changed is searched and displayed. In this state, when the switch S2 is operated, the process proceeds to step T2-22, where the mode is determined. If the mode is the normal time display mode, the operation of the switch S2 is invalidated, but if the mode is the schedule mode, the process proceeds to step T2-23, where it is determined whether the mode is the write mode. Since we are currently in the schedule write mode, the program proceeds to step T2-28, where the cursor is moved by one digit and displayed as the switch S2 is operated. Such processing is executed every time switch S2 is operated,
As a result, when the cursor moves to a desired digit position and schedule information is input by operating the numeric keypad or alphanumeric key, the input character will be written in that digit. Therefore, in the schedule write mode, desired schedule information can be written by operating the switch S2 to select a digit position, and then operating the numeric keypad or alphabet keys. In addition, switch S2 is in the schedule mode, and the switch S2 is set to step T2-2.
If it is determined in step 3 that the write mode is not in effect, the process proceeds to step T2-24, where the contents of area M _p1 specified by the value of display page pointer P among area M _o1 in data memory M are determined, and the result is ,
When “1” (hold), “0” (erase) is transferred to area M _p1 , and when “0”, area
“1” is transferred to M _p1 (step T2-2
5, T2-26). That is, the contents of area M _p1 are rewritten by operating switch S2. Therefore, in this case, switch _S2 functions as a protect/delete switch. When such protect/delete switching processing is completed, the schedule information of the page corresponding to the value of the display page pointer P is displayed, and this shows whether the schedule information of that page is set to "retain" or not. , you can check whether it has been "erased" by checking the lighting status of the PR display and DE display.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and can be modified and applied in various ways without departing from the scope of the present invention. For example, in the above embodiment, the present invention is applied to an electronic watch, but the present invention is not limited to this, but can also be applied to a small electronic calculator or a data storage device itself called a data bank.

[Effects of the Invention] As explained in detail above, this invention erases schedule information including a preset date when the date of the current time is changed. Not only can you check the schedule at any time during the day, but you can also set a new schedule after the schedule is deleted, making it possible to save memory without wasting the limited memory capacity. It has the effect of becoming.

[Brief explanation of drawings]

The drawings show one embodiment of the present invention, and FIG. 1 is a block circuit diagram of an electronic timepiece to which this invention is applied, FIG. 2 is a main configuration diagram of the RAM shown in FIG. 1, and FIG.
The figure is a configuration diagram of the display section shown in Figure 1, and Figure 4 is a general flowchart showing an outline of the overall operation.
FIG. 5 is a flowchart explaining the specific details of the alarm process shown in FIG. 4, FIG. 6 is a flowchart explaining the specific content of the schedule re-editing process shown in FIG. 4, and FIG. FIG. 4 is a flowchart for explaining the specific contents of the key processing and display processing shown in FIG. 4, and FIG. 8 is a diagram of display states that change according to switch operations. 1...ROM, 2...instruction decoder, 3...
RAM, 4...Arithmetic unit, 5...Address control unit,
7...Display section, 11...Key input section.

Claims (1)

[Claims] 1. Timekeeping means for obtaining current time information including date;
schedule storage means for storing a plurality of schedule time information including dates; display means for displaying a plurality of schedule time information stored in the schedule storage means; and current time information obtained by the timekeeping means and the schedule storage means. a coincidence detecting means for detecting a match with the schedule time information stored in the timer; a detecting means for detecting a date change in the current time information obtained by the clocking means; A schedule display device comprising: erasing means for erasing the previous day's schedule time information from among the schedule time information currently displayed. 2. Timekeeping means for obtaining current time information including date;
a schedule storage means for storing a plurality of schedule time information including dates along with erased and non-erased data; a display means for displaying a plurality of schedule time information stored in the schedule storage means; and a current time obtained by the time measurement means. a coincidence detection means for detecting a coincidence between the information and the schedule time information stored in the schedule storage means; a detection means for detecting a change in the date of the current time information obtained by the time measurement means; A schedule display comprising: erasing means for erasing schedule time information of the previous day from among the schedule time information stored in the schedule storage means and in which erasure data is stored. Device.