JPH0260338U - - Google Patents
Info
- Publication number
- JPH0260338U JPH0260338U JP13826788U JP13826788U JPH0260338U JP H0260338 U JPH0260338 U JP H0260338U JP 13826788 U JP13826788 U JP 13826788U JP 13826788 U JP13826788 U JP 13826788U JP H0260338 U JPH0260338 U JP H0260338U
- Authority
- JP
- Japan
- Prior art keywords
- sample
- converter
- hold circuits
- rewriting
- analog signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Analogue/Digital Conversion (AREA)
Description
第１図はこの考案の一実施例による多チヤンネ
ルアナログ信号出力装置を適用したシステムの構
成を示すブロツク図、第２図は同システムにおけ
るホールドデータ書き換え時のＣＰＵ１の動作を
示すフローチヤート、第３図は上記多チヤンネル
アナログ信号出力装置の他の適用例を示す図、第
４図は従来の多チヤンネルアナログ信号出力装置
の適用例を示すブロツク図である。
１……ＣＰＵ、５……データラツチ回路、７…
…Ｄ／Ａコンバータ、９……出力バツフア回路、
１３……デコーダ、１５……ＲＯＭ、１７……Ｒ
ＡＭ、２１……サンプルホールド回路。
FIG. 1 is a block diagram showing the configuration of a system to which a multi-channel analog signal output device according to an embodiment of the invention is applied, FIG. 2 is a flowchart showing the operation of the CPU 1 when rewriting hold data in the same system, and FIG. This figure shows another application example of the multi-channel analog signal output device, and FIG. 4 is a block diagram showing an application example of the conventional multi-channel analog signal output device. 1...CPU, 5...Data latch circuit, 7...
...D/A converter, 9...output buffer circuit,
13...Decoder, 15...ROM, 17...R
AM, 21...Sample and hold circuit.
Claims (1)
た複数のサンプルホールド回路と、 該サンプルホールド回路を択一的にイネーブル
とする選択手段と、 前記サンプルホールド回路の内容を周期的に書
き換える書き換え手段と を具備することを特徴とする多チヤンネルアナロ
グ信号出力装置。[Claims for Utility Model Registration] A single D/A converter, a plurality of sample-and-hold circuits connected in parallel to the output terminal of this D/A converter, and a selection for selectively enabling the sample-and-hold circuits. A multi-channel analog signal output device, comprising: a rewriting means for periodically rewriting the contents of the sample and hold circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13826788U JPH0260338U (en) | 1988-10-24 | 1988-10-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13826788U JPH0260338U (en) | 1988-10-24 | 1988-10-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0260338U true JPH0260338U (en) | 1990-05-02 |
Family
ID=31400448
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13826788U Pending JPH0260338U (en) | 1988-10-24 | 1988-10-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0260338U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63136724A (en) * | 1986-11-27 | 1988-06-08 | Matsushita Graphic Commun Syst Inc | Multi-output d/a conversion circuit |
-
1988
- 1988-10-24 JP JP13826788U patent/JPH0260338U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63136724A (en) * | 1986-11-27 | 1988-06-08 | Matsushita Graphic Commun Syst Inc | Multi-output d/a conversion circuit |
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