JPH0260436A - Multiplex power source system - Google Patents

Abstract

PURPOSE:To balance a load between power source equipments through simplified wiring without requiring adjusting work by calculating power consumption in each power source equipment digitally and transferring the data between the power source equipments. CONSTITUTION:At first, voltages at points (a), (b), (c), (d) in each secondary circuit are read out and stored in a RAM 42. Then a microcomputer 40 calculates power consumption in its power source equipment 400 and stores the calculated power consumption in the RAM 42. Then an average power consumption is calculated based on that data and data representing power consumption of load being transferred from other power source equipments 400, and the calculated average power consumption is stored in the RAM 42. Thereafter, the power consumption of load stored in its power source equipment 400 is compared with the average power consumption and next pulse ON times of power transistors 23a, 23b are controlled based on the comparison result and the current voltage levels at points (a), (b), (c), (d) stored in the RAM 24 thus averaging power supply from each power source equipment 400 to the load.

Description

[Detailed Description of the Invention] [Objective of the Invention 1] (Industrial Application Field) The present invention is a method of multiplexing a plurality of power supply devices having the same structure so that each can provide a constant voltage to a common load. This invention relates to a multiplexed power supply system configured by

(Prior art) In recent years, in order to keep the operation of stabilized power supplies more stable, two or more sets of power supplies of the same composition are combined, and each supply of stabilized DC to a common load has been developed. Multiplexed power supply systems configured to perform

Examples of this multiplex power supply system include the following.

FIG. 9 is a circuit diagram showing this multiplex power supply system.

As shown in the figure, this system allows a plurality of switching power supply devices (hereinafter simply referred to as power supply devices) 100 having the same structure to each provide a constant voltage to a common load 200. It is configured in a multiplexed manner.

In this system, load balance control is performed by the controller 300 so that power is supplied from each power supply device 100 to the common load 200 in an averaged manner.

Next, the configuration of each power supply device]00 will be explained. 1 is a filter, 2 is a rectifier circuit, C1 is a smoothing capacitor, 3 is a switching power transistor, 4 is a transformer, 5 is a snubber circuit, 6 is a control circuit (PWM) that controls the switching operation of the power transistor 4, 7 and R1 are an insulating photocoupler and a protective resistor inserted between the control circuit 6 and the controller 300, respectively.

Also, Dl and D2 are rectifier diodes connected to the secondary side of the transformer 4, L and C2 are choke coils and smoothing capacitors that respectively constitute a smoothing circuit for compressing ripples in the input current, and 8 is a rectifier diode connected to the secondary side of the transformer 4. An insulating pipe is used to provide insulation from the next side and to transfer the current flowing to the secondary side circuit back to the control circuit 6. R2 is an insulating film for transferring the current flowing into the secondary side circuit section back to the control circuit 6. Low resistance, R3, is the negative front resistance.

Inside the controller 300, 9 is an adder for adding up the potential difference between points A and B across the low resistance R2 for power supply detection 1]4 in each power supply secondary circuit; A of the adder and each power supply secondary circuit
R5 is a feedback resistor related to the adder 9, ]0 is a voltage divider for obtaining the average voltage in each power supply secondary circuit from the addition result of the adder 9. are each a voltage divider ] 0? This operational amplifier uses the average voltage obtained by Il as a reference voltage, compares this with the voltage at point A of each power supply secondary circuit, and outputs the result to the control circuit 6 of each power supply device 100.

Next, the operation of this multiplex power supply system will be explained.

In normal operation, each power supply 1. ．． 00 performs the same operation as follows.

First, a commercial AC is connected to the input section of each switching power supply device 100.
When a 100vq source is turned on, the current is input to the rectifier circuit 2 via the filter 1 and full-wave rectification is performed. As a result, a charge of approximately 140 cm is accumulated in the smoothing capacitor C1.

When a sufficient charge is accumulated in the smoothing capacitor CI, the control circuit 6 starts the switching operation of the power transistor 3.

This causes a continuous current to be generated in each power supply secondary circuit.

After this, the ripple of the current flowing through each power supply secondary circuit is
The voltage is compressed in a smoothing circuit composed of a choke coil L1 and a smoothing capacitor C2, and the constant voltage obtained thereby is applied to the load 200.

On the other hand, the constant voltage obtained in each power supply secondary circuit is fed back to the control circuit 6 via the insulating photo coupler 8, respectively.

Based on this feedback voltage, the control circuit 6 controls the on-width of the pulse sent to the base of the power transistor 3 so that the voltage applied to the load 200 from each power supply secondary side circuit remains constant.

On the other hand, A across the low resistance R2 in each power supply secondary circuit
The voltages at point and point B are respectively input to the adder 9 of the controller 300, thereby obtaining the total value of the output voltages in each power supply secondary side circuit.

That is, since the voltage drop due to the low resistance R2 between point A and point B is approximately proportional to the fjt power supply, the result obtained by the adder 9 is
This value corresponds to the total power supplied to 00.

Thereafter, the addition result is input to the voltage divider 10, where it is divided by the number of power supplies 100 to calculate its average value.

Next, in each operational amplifier 11, the value obtained by the voltage divider 10 is used as the reference voltage, and this and the A of each power supply secondary side circuit are
A comparison is made with the voltage at the point, and the comparison result is output to the control circuit 6 of each power supply device 100.

Based on the output data from the controller 300, each control circuit 6 determines the on-width of the output pulse from the power transistor 3, and controls the load 20 of each power supply 100.
Balance control of the supplied power with respect to 0 is performed.

However, in the multiplex power supply system configured as follows, the sense PJ S l for transferring the output voltage in each secondary circuit to the controller 300;
The output data from Controller 1 Herola 300 is transferred to each power supply unit 1.
Since analog load balance control is performed using the command line s2 for transferring the data to 00, the following problems have arisen.

FIG. 10 is a diagram showing a multiplex power supply system constructed by combining a plurality of power supply devices each having three constant voltage output sections, centering on the sense line s1 and command line S2 described above.

As can be seen from this figure, load balance control using this method requires as many sense S1 and command lines S2 as the number of constant voltage outputs from each power supply 100.
0 and the controller 300 was very complicated.

In addition, with this type of system, when a new system is assembled, a malfunctioning power supply], or an OO is replaced, there is a need to adjust the output to balance the output between each power supply. The adjustment work required a great deal of effort.

Furthermore, in this system, when one power supply device 100 fails, load balance control is interrupted, resulting in a problem that the load is concentrated on a specific power supply device]00.

(Problems to be Solved by the Invention) The present invention is intended to solve the above-mentioned problems in the conventional multiplexed power supply system, and it calculates the load power consumption in each power supply device by digital processing. By mutually transferring the data obtained through processing between each power supply, the load supply power at each power supply can be adjusted with simpler wiring connections and without the need for preliminary adjustment work for each power supply. L1 provides a multiplex power supply system that can perform balance control with high precision.
It has been the target.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above-mentioned object, the multiplex power supply system of the present invention includes a power supply device that obtains stabilized direct current from an input current and supplies it to a load. In a multiplexed power supply system configured by multiplexing these power supplies to supply DC to a common load, each power supply is provided with digital information about the load power consumption of its own power supply. A power consumption calculation means that calculates the power consumption, a data transfer means that transfers the power value calculated by the power consumption calculation means to another power supply device, and a data transfer means that transfers the power value transferred from the data transfer means of the other power supply device and itself. Compare the average power consumption value and the power value calculated by the own power consumption calculation means with the average value calculation means that calculates the average power consumption value from the sum 1 with the power value calculated by the power consumption calculation means of and a power supply control means for controlling the power supplied to the load of its own power supply device based on the comparison result.

(Function) In the multiplex power supply system of the present invention, the power consumption calculation means digitally calculates the load power consumption of its own power supply device, and the power value obtained thereby is used to calculate the load power consumption of the own power supply device, and the power Calculate the average power consumption value from the sum of the power values transferred from the power supply devices, and then calculate the supplied power based on the comparison result between this average power consumption value and the power value calculated by your own power consumption calculation means. Since the control means controls the power supplied to the load by its own power supply device, it is possible to control the balance of the power supplied to the load in each power supply device with a simpler wiring connection and without requiring adjustment work for each power supply device. It becomes possible to perform the process at high viscosity.

(Example) Hereinafter, an example of the present invention will be described in detail based on the drawings.

] 0 FIG. 1 is a circuit diagram showing the configuration of a multiplex power supply system according to an embodiment of the present invention.

As shown in the figure, this system consists of a plurality of switching power supplies (hereinafter simply referred to as 'power supplies') 400 having the same structure, or multiple switching power supplies that can each provide a constant voltage to a common load 500. It is structured as follows.

Next, the configuration of these power supply devices 400 will be explained.

21 is a filter, 22 is commercial A that has passed through filter 21
C1 is a rectifier circuit that rectifies OOV, C1 is a smoothing capacitor that accumulates the charge after rectification, 23a and 23b are power transistors provided corresponding to the +5V and +12V secondary side output sections, respectively, and 24a and 24b are single circuits. An input/output type transformer, 25a12'5b is a snubber circuit that consumes the energy stored in the primary coil of the corresponding transformer 24a, 24b when each power transistor 23a, 23b is turned off, 26 is a snubber circuit for each power transistor 23a, 23b. This control circuit functions as a power consumption calculation means, an average value calculation means, a comparison means, and a power supply control means for controlling the pulse-on width of the load 500 and controlling the balance of the power supplied to the load 500.

In addition, RI R2 is connected to each power transistor 23.
a, a resistor connected to the emitter side of 23b, DI-DB
are rectifier diodes connected to the secondary side of each transformer 24a, 24b, and among these, DB and D6 each function to prevent reverse flow of current from the negative 1as side.

Furthermore, Ll, L2, C2, and C3 are choke coils and smoothing capacitors that constitute a smoothing circuit for compressing current ripples generated in the secondary coils of the respective transformers 24a and 24b, respectively, and R3 and R4 are respectively for the respective secondary coils. This is a low resistance for detecting load consumption and small force inserted between points a and b and between points c and d of the side circuit.

Furthermore, 27, 28, 29, and 30 are from the first point where the voltages at points a, b, c, and d across the above-mentioned resistors R3 and R4 are fed to the control circuit 26 through insulation. The fourth insulating photocouplers, R5 and RI3, are resistances in the load 500, respectively.

Next, the configuration of the control circuit 26 mentioned above will be explained.

40 is a microcomputer that centrally controls the control circuit 26; 41 is a ROM that stores a control program executed by the microcomputer 40; 42 is a RAM that is used as a work area for the microcomputer 40; power) transistors 23a, 23b
A that converts the voltages at points e and f on the emitter side of the A and the outputs from the first to fourth insulating photocouplers 27, 28, 29, and 30 into digital data consisting of 8 bits.
The A/D converter 44 is a first 8-bit register that temporarily holds the digital data output from the A/D converter 43.

Also, 45a and 45b are first and second drivers that output %l pulses to the bases of the corresponding power transistors 23a and 23b, respectively; 46 is a driver that outputs output data from the control circuit 26 to the control circuit 26 of the other power supply device 400; Interface 1-lime 47 is an interface receiver 48 that receives data output from the control circuit 26 of another power supply device 400.
is a light emitting diode for notifying an operator etc. of the occurrence of an abnormality in each power supply device 400 by flashing a light; R7 is a resistor for protecting the light emitting diode 48; 49 is a second 8-bit register that holds various input/output signals; 50 is a timer for generating operation timing in the control circuit 26;
51 is a switch for setting the power supply device number of each power supply device 400.

Further, the O-th bit of the second 8-bit register 49 described above contains a signal to be transmitted from the interface driver 46,
The signal received at the interface receiver 47 is set in the [th] bit. Further, the second bit contains a signal output to the light emitting diode 48, and the third bit I
. The signal output to the first driver 45a is set respectively. Further, the fourth to sixth bits are set to a signal set by the switch 5], and the seventh bit is set to a signal output to the second driver 45b.

Next, the operation of the multiplex power supply system configured as follows will be explained.

First, when a C100V power source is inserted into the input section of each power supply device 40o, the current is inputted to the rectifier circuit 22 via the filter 21, and full-wave rectification is performed. Charge is accumulated.

Here, the control circuit 26 controls each power transistor 2-,
-3a, 2:Starts the switching operation at 3b.

When each power transistor 23a, 2''3b is on, the charge accumulated in the smoothing capacitor c1 flows as a current to the primary coil of each transformer 24a, 24b, thereby causing each secondary coil of each transformer 24a, 24b to flow. A current flows through the next coil in a direction that makes the rectifier diodes DI D3, D4, and D6 conductive.

In addition, when the power transistors 23a and 23b are in an off state, the snubber circuits 25a and 25b consume the energy stored in the secondary coil in the direction in which the rectifier diodes D2 and D5 conduct to the secondary coil, respectively. current flows. This causes a continuous current to flow through each secondary circuit.

After this, the ripple of the current flowing through each secondary circuit is reduced to choke coils Ll, L2 and smoothing capacitors C2, C3.
A constant voltage is applied to the load 500.

On the other hand, the voltages generated at points a, b, 6, and d of each secondary circuit are applied to the first to fourth insulating photocouplers 2, respectively.
7.28.29.30 to the A/D converter 43 of the control circuit 26.

Thereafter, the voltage input to the A/D converter 43 is converted into 8-bit digital data and temporarily held in the first 8-hint register 44.

Thereafter, the microcomputer 40 transfers the second 8-bit register based on the data held in the first 8-bit register 44.
By controlling the signals set in the third and seventh bits of the bit register 49, the pulse-on width of each power transistor 23a, 23b is determined via the first and second drivers 45a and 145b, respectively. As a result, each power transistor 23a responds to voltage fluctuations generated in each secondary circuit.
, 23b is controlled.

Next, the load supply power balance control operation in this embodiment system will be explained using FIGS. 2 to 8.

FIG. 2 is a flowchart showing the flow of load balance control operations during power-on in this system.

A commercial 100V power supply is applied to the AC input section, and the control circuit 2
6, the microcomputer 40 executes load balance control in accordance with the control program stored in the ROM 41 as follows.

First, initial values are set in the RAM 42 and the second four 8-bit registers, and the timer 50 and the first 8-bit register 44 are reset.
Furthermore, masking is performed to inhibit generation of a timeout interrupt, which will be described later (step 2).

After this, the voltages at points b and d in each secondary circuit are transferred to the third and fourth insulating photocouplers 29 and 30, respectively.
The data is taken into the control circuit 26 via the A/D converter 43, converted into digital data, and stored in the RAM 42 (step 22).

Next, each power transistor 23a, 23b is controlled on/off, and an operation for raising the voltage at point a and six points in each secondary side circuit is started. Here, the control circuit 26 a
The voltages at points and 6 points are connected to the first and second insulating photocouplers 27.
．． 28, and while reading the value, confirm completion of voltage rise (steps 23 and 24).

Subsequently, it is determined whether the voltage data at points b and d stored in the RAM 42 are normal.

That is, point b -5■±0, 25V, point d -1,2V
If it is within the range of ±0.6■, it is determined to be normal (step 25).

]8 If this is not determined to be normal, try using another power supply
It is determined that the constant voltage output operation of 00 is not completed and sends a clear signal to the system body (step 2).
6). On the other hand, if it is determined to be normal, the clear signal to the main body is transferred and the timeout interrupt is unmasked (step 27).

After canceling the mask, a set time (1 μs) for generating a time-out interrupt for vector address F is set in the timer 50 (step 28).

Note that the timer 50 can be set with respective set times for a plurality of timeout interrupt destinations.

FIG. 3 is a flowchart showing processing operations based on this timeout interrupt.

As shown in the figure, the timeout interrupt processing defined in this system includes data reception interrupt (pector address C), data transmission interrupt (pector address B), and one voltage value reading interrupt (pector address B). Pectoral address C), first power transistor off interrupt (pectoral address D), second power l.
It consists of a transistor off interrupt (vector address E), a transistor on interrupt (vector address F), and a transistor on interrupt (vector address F).

That is, as described above, by setting the timer 50 to the set time (1 μs) for interrupting the vector address C, after the set time has elapsed, the power transistor 2
The ON operation of 3a and 23b is started.

The voltage raising operation in step 23 shown in FIG. 2 will be explained with reference to FIG.
3b is turned on, and after that, in the process of vector address C, while reading the voltage at point a and point 0, the voltage on the node is gradually changed until the value reaches the specified voltage (5.8V, 12.8V). Increase it to the maximum value,
When the respective specified voltages are reached, each power transistor 23 is
Perform the off operation of a and 23b. This results in point a and 0
A voltage rise at a point is performed.

Now, in step 28 of FIG. 2, when the interrupt setting time (1 μs) to the vector address F is set in the timer 50, after waiting for the setting time to elapse (two steps), a timeout interrupt is generated. Then, processing of vector address F is started.

The flow of subsequent processing will be explained using waveform diagrams in FIGS. 3 and 4.

In FIG. 4, TO indicates the timing at which processing of vector address F is started.

When processing of this vector address F is started, the 10'' signal is set to the third and seventh bits of the second 8-bit register 49, and this causes each driver 45
A and 45b output a "]" signal to turn on each power transistor 23a and 23b. At the same time, five types of set times t1 to t5 are set in the timer 50.

These set times t1 to t5 correspond to t1 to t5 in the signal timing diagram of FIG. 4, respectively, and the respective timeout vector addresses are C and E.
, D, F, and C addresses.

When the processing of vector address F is completed, the process enters the timeout interrupt waiting state again.

Then, after a time t1, that is, at the timing of T1, an interrupt to the vector address C occurs.

First, read the voltages at points a, b, c, and c in each secondary circuit, and store these in the RAM 42 shown in FIG.
The data is stored at addresses M4 to M7.

Thereafter, the microcomputer 40 calculates the load power consumption in its own power supply device 400 from the voltage value data stored in the RAM 42, and sends the result to the RAli 42.
Store it at address M9.

Then, the average power consumption value is calculated from this data and the data indicating the load power consumption in the other power supply apparatuses 400 transferred from the other power supply apparatuses 400 and stored in addresses MiO to M1.1 of the RAM 42, and the average power consumption value is calculated. RAM4
Store in M12 of 2.

After this, address M! of RAM42! The load power consumption value of the own power supply device 400 stored in ll is compared with the average power consumption value, and the comparison result and M4 to M of the RAM 42 are
The next pulse-on times t3 and t2 of each power transistor 23a and 23b are determined from the current voltage values of points alb, c, and d stored in
3. Store each in M2.

After this, an abnormality check is performed.

The contents of this abnormality check will be explained using the flowchart of FIG.

First, in step 6], +5■ at points a and b
Perform overvoltage check. And point a +8 ■ -1-1
If point b is +8.5■ or more, the process moves to step 62, and the system body and other power supplies 400 are notified of this fact.

In step 63, a +5⁻ undervoltage check is performed at points a and b. And point a is +4.8v or less,
If the voltage at point b is less than +4v, the process moves to step 62.

In step 64, a ++2V overvoltage check is performed at points C and d, and if the voltage at point C is 5V or higher and the voltage at point d is +135V or higher, the process moves to step 62.

In step 65, a +1.2V undervoltage check is performed at points C and d, and if the voltage at point C is +1.0.8V or less,
If point d is below +l0VIJu, the process moves to step 62.

In step 66, an overcurrent check is performed at the +5■ output section. In this case, (voltage at point a - voltage at point b) > 1. ．． When the voltage is 6V, the process moves to step 62. In other words, if the potential difference between point a and point b is 1.6■, then R1 = 0.05Ω, the drop voltage of diode D3 is 0.6V, and the current is 20A, then 20A x O, 05Ω + 0.8V = 1.6
V, and if a current of 2OA or more flows, an overcurrent occurs.

Furthermore, in step 67, an overcurrent check is performed at the +12■ output section. In this case as well, R1=0.
05Ω, drop voltage of diode D6 1■, current 1. When OA, 10A x O, 05Ω+lV=1. ．． If the voltage becomes 5V and a current of IOA or more flows, an overcurrent will occur.

If any of these abnormalities are detected, data to that effect is transferred to the main body and other power supply devices 400 in step 62.

This data transfer is performed at the 0th bit of the second 8-bit register 49.
This is done by driving the interface driver 46 by controlling the signal to be set in the bit. At the same time, the switching operation in its own power supply device 4°O is stopped (step 68).

Furthermore, the second bit of the second 8-bit register 49
The operator is informed of the occurrence of an abnormality by setting the rOJ signal and the "1" signal every second to make the light emitting diode 48 blink (step 69.69a).

Incidentally, if these abnormalities are not detected, the system enters a state of waiting for an interrupt in step 2 in FIG.

Now, when a timeout of time t2 in FIG. 4 occurs, an off interrupt for the second power transistor 23b at vector address E is started.

In this processing operation, the voltage at point f of the resistor R2 is read at the timing T2 in FIG. 4, and the human power from the second switching transistor 23b is calculated from that value and the pulse width t2. Then, store that value in RAM42.
9 as +12V-next side input power.

Similarly, when a timeout of time t3 in FIG. 4 occurs, an off interrupt for the first power transistor 23a at the vector address D is started.

That is, in this processing operation, first, the voltage at point e of the resistor R1 is read at the timing T3 in FIG. 4, and the input power to the first power transistor 23a is estimated from that value and the pulse width t3. Then, the value is stored in the RAM 42 as the +5■-next side input power of M9.

Next, when a timeout occurs at time t5 in FIG. 4, the befter address C
Address processing begins.

In this case, each power is determined at the appropriate time for t1 time.
1. Pulse on time t3 of transistors 23a and 23b,
t2 is corrected and the corrected value is stored in M3 of RAM42.
, M2 respectively.

The calculation of these pulse on times t3 and t2 is as follows: In Fig. 4, when the voltage at point b is lower than -5V at Tl T4, the next pulse on width is increased from the previous pulse on width, and each secondary This is done by increasing the energy supplied to the side circuit.

At this time, the load power consumption value and the average power consumption value in the own power supply device 400 are compared, and based on the result, t
3. The pulse-on width at t3 is controlled to average the power supplied to the load in each power supply device 400.

As described above, the load supply power balance control in the multiplex power supply system of this embodiment is performed.

On the other hand, when the microcomputer 4o is powered on and the switching operation is started, +5V output power = (voltage at point a - voltage at point A - voltage at point D3) x voltage at point b / R, 3 resistance + 12v output power = ( c point voltage - 0 point voltage - D6 voltage)
Calculate the output power of each secondary side output section using the formula: xb lightning voltage/R4 resistance.

In addition, the primary side human power force due to the emitter resistance of each power transistor 23a, 23b is calculated as +5V power force (χ/R1+χ'/R1)÷2X in section t4 of Fig. 4.
(t3 / t4) XV i → -12V input electric car (y/R2+y' /R2) ÷ 2
4) It becomes XVi. On the other hand, Vi is the charge accumulated in the smoothing capacitor CI, that is, the input DC voltage.

The results obtained from this previous calculation are based on the power supply unit 400
The data is stored in M9 of the RAM 42 in the computer, and is also transferred to another power supply device 400.

This data transfer is performed using a serial data transfer method, and when the time allotted sequentially to each power supply device 400 or power supply device number has elapsed, its own data transfer is performed.
At other times, reception control is performed.

FIG. 7 is a diagram showing serial data transfer when power supply numbers #1 to #n are assigned to each power supply device 400, respectively.
When the number of 00s is four, there are #n+1 dummy 118 intervals, so in this power supply system, its own data transmission time cycles every 5 times.

Furthermore, FIG. 8 shows how the meaning of the transferred data is defined for each unit time.

As shown in the figure, the first three bits are a data transfer start flag indicating that data transfer has started. Next 3
The bits indicate the power supply number, in this case r
oSO, OJ, that is, power supply number 1 is shown. The next 8 bits I• indicate the power consumption in the +5V- secondary circuit, and the next 8 bits indicate the power consumption in the +12V secondary circuit. Furthermore, the next 8 bits indicate the primary side power consumption due to the emitter resistor R1 of the -5■ side power transistor 23a, and the next 8 bits indicate the primary side power consumption due to the emitter resistor R2 of the +12V side power transistor 23b.

Next, the operation of this data transfer control will be explained.

First, the microcomputer 40 determines its own power supply device number from the set state of the switch 5], and stores the data in M1 of the RAM 42.

The data transfer control at power-up will be omitted here, or after power-up, pig transfer control will be performed from the interrupt wait state in step 29 in FIG. 2 by data reception interrupt processing at vector address A. .

As a result, the microcomputer 40 reads the data of the first bits of the four second 8-bit registers, and sequentially stores the read data in M13 of the RAM 42.

After this, by setting the set time IQAzs in the timer and specifying the vector address A, 1. OIt
After s has elapsed, the interrupt processing for the vector address A is started again.

In this way, lPino I Tsutsun real data is 10
Read each Azs and interpret the data when M3 of RAM42 is filled.

In interpreting this data, if the first 3 bits (data transfer start frequency) are all "1", it is judged as normal.The next 3 bits of data are the power supply number, so each The data of the newly calculated load power consumption value in any of the power supplies 400 is stored in the RAM 42.
It is determined in which of M9 to Mll the data should be stored.

Furthermore, in this data transfer control, if it is the next turn to transfer data from its own power supply device 400, the process shifts to the data transmission interrupt at vector address B in FIG.

Then, it reads its own power consumption value data from M9 of the RAM 42 and transfers it to the other power supply device 400 one bit at a time.

That is, after reading 1 bit from M9 of the RAM 42, once reading the second 8-bit register 49, and setting the j-bit data to be transferred to the other power supply device 400 to the 0th bit, read this 8-bit register again. By writing 8-bit data to 4, other power supply 4
00 and data transfer to the system itself.

Thereafter, by setting a set time of 10 .mu.s in the timer and specifying the vector address B, the interrupt processing for the vector address B is started again after ]OLIS has elapsed.

In this way, one bit from the 0th bit of the first 8-bit transceiver 49 is transferred every 1 Qzzs.

Thus, in the multiple power supply system of this embodiment, by calculating the load power consumption inside the control circuit 26 of each power supply apparatus 400, it is possible to perform balance control of the load supply power of each power supply apparatus 400.

Therefore, unlike conventional multiplex power supply systems, there is no need to draw out sense lines, command lines, etc. from each power supply device to the outside, and the number of lines can be reduced without significantly reducing the number of lines, thereby simplifying the configuration. can.

Furthermore, even if one of the power supply devices fails, the balance control of the load supply power in the other power supply devices is not affected, so reliability is improved.

Furthermore, even if there is an error in the set voltage of each power supply, data transfer of the load power consumption value between each power supply eliminates the need to adjust the output of each power supply.

In the example system described above, for example, on the +5V side, the load power consumption is calculated from the voltages at points a, b, and point e of the resistor R1, or the load power consumption is calculated from only the voltages at points a and b. It is also possible to calculate power.

[Effects of the Invention] As explained below, according to the multiplex power supply system of the present invention, the load power consumption in each power supply device is calculated by digital processing, and the data obtained by this processing is By mutually transferring power between power supplies, it is possible to control the balance of the load supply power in each power supply with high viscosity with a simpler wiring connection and without the need for adjustment work for each power supply. .

[Brief Description of the Drawings] Fig. 1 is a circuit diagram for explaining the configuration of a multiplex power supply system according to an embodiment of the present invention, and Fig. 2 shows load balance control of each power supply device in the system of Fig. 1. FIG. 3 is a flowchart showing the processing operation using a timeout interrupt for load balance control, and FIG. 4 is a flowchart showing the output voltage waveform during load balance control. 5 is a diagram showing the contents of the RAM in the system of FIG. 1, and FIG.
, Fig. 7 is a diagram for explaining the data transfer method between each power supply device in the system shown in Fig. 1, and Fig. 8 is a diagram for explaining the meaning of data at each unit time in the data transfer method shown in Fig. 7. FIG. 9 is a circuit diagram for explaining the configuration of a conventional multiplex power supply system, and FIG. 10 is a block diagram showing the system of FIG. 9 with a focus on sense lines and command lines. 26...control circuit, 40...microcomputer,
41... ROM, 42... RAM, 46... Interface driver 47... Interface lens driver, 400
Switching power supply, 500/load. ■Applicant Toshiba Corporation

Claims (1)

[Claims] (1) A plurality of power supply devices are provided to obtain stabilized direct current from the input current and supply it to the load, and these power supply devices are multiplexed so that they each supply the said direct current to a common load. In the multiplex power supply system, each power supply device includes a power consumption calculation means that digitally calculates the load power consumption of its own power supply device, and a power consumption calculation means that calculates the power consumption value calculated by the power consumption calculation means for the other power supply devices. Average value calculation of calculating an average power consumption value from the sum of the power value transferred from the data transfer means to be transferred, the data transfer means of the other power supply device, and the power value calculated by the own power consumption calculation means. means, a comparison means for comparing the average power consumption value and the power value calculated by the own power consumption calculating means, and controlling the power supplied to the load by the own power supply device based on the comparison result. What is claimed is: 1. A multiplex power supply system characterized by comprising a supply power control means.