JPH026073B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an envelope control method for an electronic musical instrument that controls the envelope of an output musical tone of the electronic musical instrument.

In electronic musical instruments, the envelope is an extremely important element in composing musical tones, but conventional electronic musical instruments are often designed using analog methods, so the envelope also has a CR time constant. This can be done by configuring the circuit with , or by setting the envelope waveform in advance in a storage device. However, such a configuration requires a plurality of CR circuits and storage devices corresponding to each musical instrument, making the circuit configuration complicated and expensive.

The present invention has been made in view of the above points, and divides the envelope into multiple statuses, and for statuses whose levels change over time, numerical data for determining the time interval, and for statuses whose level changes over time, and numerical data for determining the time interval, For the status to be held, the husband/husband player inputs numerical data to determine the level value, and the calculation speed is controlled according to the time interval and level value determined by the input numerical data. The present invention provides an envelope control method for an electronic musical instrument in which an envelope output is obtained and the envelope of a musical tone is controlled by the envelope output.

Hereinafter, one embodiment of the present invention will be described in detail based on the drawings.

FIG. 1 shows the overall configuration according to the present invention.
1 is a key matrix in which a large number of performance keys are arranged as shown in Figure 2. In this case, 84 keys are arranged in 12
It is arranged in columns and 7 rows. 2 is clock pulse
This is an 84-decimal counting circuit that counts CP1, and is composed of a 4-bit hexadecimal binary column counting circuit 2a and a 3-bit heptad binary row counting circuit 2b, and each bit output of the column counting circuit 2a corresponds to a musical scale. To the decoder 3, each bit output of the row counting circuit 2b is supplied to an octave decoder 4, which sequentially generates a timing signal.

The details of the matrix circuit 1 are shown in FIG. 3, and the 84 keys are input from the scale decoder 3.
It is coupled to twelve input lines 1-1, . . . , 1-12 and output lines 1-13, . and the output lines 1-13,...,1
-19 is each output line 1 of octave decoder 4
-20, ..., 1-26 and connected to the OR circuit 1-34 via AND circuits 1-27, ..., 1-33, and when the key is operated, an octave timing signal The OR circuit 1-34 outputs an operation timing signal from the scale decoder 3 corresponding to the above. Further, the 4-way and 8-way bit stage outputs of the column counting circuit 2a are coupled to an AND circuit 5, which resets the column counting circuit 2a when the output rises and supplies a "+1" increment signal to the row counting circuit 2b. , row counting circuit 2
Each bit stage output of B is coupled to an AND circuit 6 and performs a counting operation so as to reset the row counting circuit 2b when the output rises. Therefore, the column counting circuits 2a,
The row counting circuit 2b performs counting operations in hexadecimal and heptadary, respectively.

The output of each bit stage of the counting circuit 2 is supplied to a 7-bit parallel first register 7 and a matching circuit 8 in synchronization with an output signal from an AND circuit 9, which will be described later. The bit stage output is a 7-bit parallel second register 10.
and is supplied to the coincidence circuit 8 in synchronization with an output signal from an AND circuit 11, which will be described later.
The 7-bit parallel numerical information in the second register is supplied to the pitch clock control circuit 12, which supplies a clock signal with a frequency corresponding to the pitch based on the numerical information to the address control circuit 13 as an address step signal. , musical sound waveform storage device 1
4 is read out at each address step.

The tone waveform storage device 14 digitally stores the half-wave tone waveform shown in FIG. 4, for example.
It is composed of RAM (random access memory) and has a storage capacity of, for example, 256 (steps) x 11 (bits) = 2816 (bits). On the other hand, the address control circuit is shown in FIG. 5, and is provided with an address counter 13-1 that performs an 8-bit up/down counting operation to obtain a binary counting state of 256 steps from "0" to "255". . That is, the address counter 13-1 sequentially counts up from "0" to "255" and reads out the half-wave musical sound waveform stored in the musical sound waveform storage device 14, and then counts down "255". '' to the counting state of ``0'' and read out the tone waveform in the reverse direction, thereby reading out and outputting the full-wave tone waveform. Therefore, the clock signal of the frequency corresponding to the designated pitch from the pitch clock control circuit 12 (see FIG. 6a) is sent to the address counter 13-1.
, the tone waveform storage device 14 is sequentially addressed in the upward direction. and,
When the address counter 13-1 reaches the counting state of "255" as shown in FIG. 6, a carry signal is supplied to the OR circuit 13-2 as shown in FIG. )
The AND circuit 13-4 to which the side output of the circuit 13-3 and the performance command are applied is opened, and its output signal is applied to the DF/F circuit 13-5. this
The DF/F circuit 13-5 generates a signal from the Q side output at the rising edge of the output signal obtained by inverting the pitch clock signal mentioned above by the inverter 13-6, and issues a down command to the address counter 13-1 as shown in FIG. 6c. supply the signal. Further, this down command signal is fed back to the OR circuit 13-2 and the AND circuit 1
It is also applied to the input terminal of 3-7. When the address counter 13-1 performs a down counting operation based on the down command signal, the address counter 13-1
When the count becomes "0", a "0" detection signal as shown in FIG. 6d is obtained from the inverter 13-9 via the OR circuit 13-8 and applied to the AND circuit 13-7. At this time, the AND circuit 13-7 has
Since the signal from the DF/F circuit 13-3 side is also applied, this AND circuit 13-7 is opened, and its output signal is applied to the data input terminal of the DF/F circuit 13-3, which clocks the pitch clock. The output state is inverted in synchronization with the signal, and the S signal as shown in FIG. 6e is obtained from the Q side output. Since the Q side output signal of this DF/F circuit 13-8 is applied to the gate circuit 15, when the S signal is output, the gate output is prohibited and the output state is set to "0". That is, the address counter 13-1 changes from a counting state of "0" to a counting state of "255" at the time of output in FIG. 6e due to the down command, but at this point, output from the gate circuit 15 is prohibited. . And DF/F
When the S signal is output from the Q side output terminal of the circuit 13-3, the output of the AND circuits 13-4 and 13-7 is prohibited, and the address changes from the down command to the up command again as shown in Figure 6c. Counter 13-
1 is counted in the upward direction and is incremented from the "0" counting state. Therefore, as shown in FIG. 4, the half-wave musical sound waveforms stored in the musical sound waveform storage device 14 are sequentially addressed as the counting state of the address counter 13-1 from "0" to "255" to "0". It is read out as a full-wave musical sound waveform, but if you want to read it out again after this one cycle, the "0" address should be changed as follows: "0" → "255" → "0""0" → "255"... Since it has to be specified continuously, an S signal from the DF/F circuit 13-3 is provided, and an additional circuit for one step is required. Further, the down command signal from the address control circuit 13 is supplied to the D/A conversion circuit 16 as a polarity inversion signal, and the address counter 13-1
The digital value read out from the tone waveform storage device 14 via the gate circuit 15 is converted into an analog quantity. .

Note that although the tone waveform storage device 14 stores half waves, it is of course possible to store it as a full wave tone waveform, although in this case the storage capacity and number of address steps will increase. The configuration of the address control circuit 13 can be simplified, and there is no need to control the address counter 13-1 in the down direction.

Further, during performance, the timing signal corresponding to the operated key outputted from the OR circuit 1-34 of the key matrix circuit 1 is sent via the OR circuit 17 to an 84-bit signal having a memory bit number corresponding to the number of keys. It is stored in the corresponding storage bit position of shift register 18. This shift register 18 is sequentially shifted in synchronization with the clock signal CP1, and the output signal from this shift register 18 is passed through an AND circuit 19 to which an output signal from a 20 ms measurement counter 20, which will be described later, is supplied. and is fed back to the OR circuit 17.

21 is a ternary counting circuit that sequentially outputs count value signals from the outputs of "0", "1", and "2";
The output is "2" at the first input terminal of the AND circuit 11.
The output is connected to the first input terminal of the AND circuit 22, the "0" output is connected to the first input terminal of the AND circuit 9,
Gate control is performed in the order of "0", "1", and "2" outputs. The output signal from the OR circuit 17 is connected to the other input terminal of the AND circuit 9, and the output signal is connected to the first input terminal of the OR circuit 23.
The coincidence output signal of the coincidence circuit 8 is connected to the second input terminal of the matching circuit 8, and the output signal is connected to the second input terminal of the OR circuit 23, and the second input terminal of the AND circuit 11 is connected to a 16 ms measurement counter 24, which will be described later. The S signal or start command shown in FIG. 6e from the address control circuit 13 is applied to the third input terminal, and the output signal is coupled to the third input terminal of the OR circuit 23. The ternary counter 21 is incremented by the output signal of the OR circuit 23. Note that the clock frequencies of CP1, CP2, and CP3 to be described later are not particularly limited, but in this embodiment, CP1 is a 64KHz (15.625μs) clock, and the clock frequency of CP1 is 64KHz (15.625μs), and the clock frequency of CP1 is 64KHz (15.625μs). One cycle is 15.625μs×84=1.3125m
It is s. CP2 was obtained by dividing CP1 by 64.
The clock is 1KHz (1ms), and the measurement counter 24 is composed of 5 bits, and has a half period of the MSB (i.e., the time from the clear state until the MSB becomes 1).
is 16ms. The measurement counter 20 is similarly configured with 5 bits, and the output obtained by decoding the counter value 10100 (20 in decimal) is sent to the inverter 31 and the AND circuit 1.
9 to obtain a signal 20ms after key-on.

The 16ms measurement counter 24 is an AND circuit 1
1, the clock signal CP2 is immediately output from the initial state via the AND circuit 25, and an output signal is obtained after 16 ms has elapsed. and is coupled to the AND circuit 25 to stop the measurement state.

In other words, the 16 ms measurement counter 24 sequentially switches every 16 ms in response to each of a plurality of pitch specifications pressed simultaneously as a chord performance, and time-divisionally changes the musical sound waveform according to the corresponding pitch clock signal. In this case, the switching control is performed immediately after 16 ms has passed and when the S signal shown in FIG. 6e is generated in the counting state of the address counter 13-1. It is something that will come to be done.

Further, the timing signal corresponding to the operation key outputted from the OR circuit 1-34 of the key matrix circuit 1 is supplied to one input terminal of the AND circuit 27, and the other input terminal is supplied to the shift register 1-34.
The output signal from 8 is provided via an inverter 28. The output signal of the AND circuit 27 is supplied as an attack signal to an envelope circuit 29, which will be described later, and also clears the measurement counter 20. Immediately after this measurement counter 20 is cleared, the clock signal CP2 is output from its initial state via the AND circuit 30.
It counts and obtains an output signal after 20ms.
The output signal is passed through an inverter 31 and becomes a gate inhibit signal for the AND circuit 30. In other words, from among the 84-bit shift register that stores the timing signals of keys operated during performance, the keys that have not been operated within 20ms from the moment of the most recent key input are is to erase the stored value from the shift register 18.

Further, the envelope signal from the envelope circuit 29 is applied to an analog multiplication and amplification circuit 33 via a D/A conversion circuit 32 together with the output of the D/A conversion circuit 16 to which the above-mentioned musical sound waveform readout output is supplied. Here, a pitch with a tone is finally created and outputted from the speaker 34 as a musical tone.

Also, OR circuit 1- of key matrix circuit 1
The operation timing signal outputted from the counter 34 is counted by a counter 35, and the counted value is preset in the register 36 by the carry signal of the counting circuit 2, and the counter 3 is preset by the signal via the delay circuit 37.
5 is cleared. The output value of the register 36 is then supplied to the analog multiplication and amplification circuit 33. That is, this counter 35 counts the number of keys pressed simultaneously during one cycle of the counting circuit 2, and the volume is also controlled based on the value corresponding to the counted value.

FIG. 7 shows a specific example of the envelope circuit 29. The envelope is shown as a solid line in FIG. 8, and generally has an attack status, a decay status, a sustain status, and a release status. In this embodiment, the attack time, decay time, sustain level, and release time are set to arbitrary numerical values for each of these statuses in advance before playing.
A key input device 29-1 having 16 keys is provided. These keys "0", . , ..., 29-6 to the shift register 29-7. This shift register 29-7 is composed of a 4-digit data storage device in which 4-bit parallel storage elements 29-8, . . . , 29-11 are connected in series, and the output of the storage element 29-11 is connected to the OR circuit. 29-3,
..., it is set to be returned on 29-6.
On the other hand, an operation signal output from the key input device 29-1 every time a key is operated is applied to a delayed flip-flop (hereinafter referred to as DF/F) circuit 29-13 via an OR circuit 29-12, and a clock signal is output from the key input device 29-1.
This is output from the side in synchronization with CP3.
Therefore, an AND circuit 29- obtains the logical product of the side output of the DF/F circuit 29-13 and the OR circuit 29-12.
14 generates a one shot signal at the rising edge and is supplied to the first input terminal of the OR circuit 29-15.
The output of this OR circuit 29-15 is applied as a shift signal to the shift register 29-7, and is incremented to a quaternary counter 29-16 which counts in synchronization with the shift operation of this shift register 29-7. Applied as a signal.

That is, the numerical codes corresponding to the keys operated on the key input device 29-1 to specify the attack time, decay time, sustain level, and release time are finally stored in the storage element 29-11 as the attack time and the storage element 29. -10 as the decay time, storage element 29-9 as the sustain level value, and storage element 29-8 as the release time.

The counter 29-16 has 3-bit first, second, and third storage elements, and each bit output thereof is fed back to the input side of the first storage element via an OR circuit 29-17 and an inverter 29-18. If the output of the inverter 29-18 is a, the output of the first storage element of the counter 29-16 is b, the output of the second storage element is c, and the output of the third storage element is d, the initial In this state, each of the a, b, c, and d outputs is in the "1000" state, and each time the counting step signal from the OR circuit 29-15 is applied, the outputs are "0100" and "0100", respectively.
It changes as "0010" and "0001".

Storage element 29- of said shift register 29-7
The outputs of each bit stage of 8 are decoded by decoders 29-20, and the numerical codes are "1", . . .
It now gives an output of "16". On the other hand, the clock signal CP3 is counted by a 16-bit binary counting circuit 29-21, and each bit output is connected to each output "1", . . . , "16" of the decoder 29-20 and an AND circuit 29-22, . ..., 29-37 are logically combined. And AND circuit 29-
Each output of 22, ..., 29-37 is an OR circuit 29
-38 to one input terminal of the AND circuit 29-39, and is also applied to the DF/F circuit 29-40 to clear the binary counting circuit 29-21 in synchronization with the clock signal CP3. . That is, since the binary counting circuit 29-21 operates to count the clock signal CP3 up to the output specified by the decoder 29-20,
Different time measurements will be obtained depending on the output of the decoders 29-20.

The time measurement clock signal obtained from the AND circuit 29-39 is supplied as a counting step signal to a 5-bit binary counting circuit 29-41 which performs an up-down counting operation. This binary counting circuit 29
-41 is usually counted in the upward direction, but the 4
Other than the b output of the first storage element of the forward counter 29-16, the count is performed in the down direction by a down command via the inverter 29-42.
In addition, "2" of the binary counting circuit 29-41,
The outputs of each bit stage of "4", "8", and "16" are matched with the output of the storage element 29-11 of the shift register 29-7 by the match circuit 29-43, and the outputs of all bit stages are is supplied to the D/A conversion circuit 32 shown in FIG. The coincidence signal from this coincidence circuit 29-43 is inputted to an AND circuit 29-44 together with the c output of the second storage element of the quaternary counter 29-16, and the output of this AND circuit 29-44 is further input to an inverter. 29-
45 to the AND circuits 29-39 as a gate inhibit signal.

The attack signal output from the AND circuit 27 shown in FIG. 1 in response to a key operated during performance is sent to the AND circuit 2 of the envelope circuit 29 shown in FIG.
9-46. Further, since the clock signal CP3 is connected to the second input terminal of the AND circuit 29-46, and the output of the inverter 29-42 is connected to the third input terminal, when the attack signal is applied, the AND circuit 29-46 is opened, a shift signal is supplied to the shift register 29-7 via the OR circuit 29-15, and the storage element 29-46 is opened.
The attack time numerical code stored in advance in 11 is OR circuit 29-3,...,29-
6 to the storage element 29-8, and its numerical code is applied to the decoder 29-20, and the counter 29-16 increments to the "0100" state. Then, the decoder 29-20 decodes the AND circuit 2.
One of 9-22, ..., 29-37 is selected,
OR circuit 2 is output for each time count corresponding to the numerical value.
9-38, and is counted by a binary counter 29-41 via an AND circuit 29-39. When this binary counter 29-41 reaches the maximum level value of 31 shown in FIG.
DF/F circuit 29-13 is set. Therefore,
As mentioned above, the AND circuit 29-14 and the OR circuit 2
Since the shift signal is outputted through the shift register 29-15, the decay time is shifted and stored in the storage element 29-8 of the shift register 29-7, and the counter 29-16 becomes in the "0010" state. For this reason, a down command is supplied to the binary counter 29-41, so that the count value "31" is counted "-" according to the measurement time corresponding to the set value of the decay time of the storage element 29-8. become. Then, during this down counting operation, the shift register 2
When the set value of the sustain level stored in 9-11 matches the count value of the binary counter 29-41, a match output is obtained from the match circuit 29-43, and the AND circuit 29-44 and the OR circuit 29-
45, the AND circuits 29-39 are inhibited and the counting operation is stopped and held.

This sustain level value is released by operating a release button provided separately. That is, when the release button is operated, the operation signal is supplied to the first input terminal of the AND circuit 29-48. The clock signal CP3 is connected to the second input terminal of the AND circuit 29-48, and the OR circuit 29-1 is connected to the third input terminal of the AND circuit 29-48.
7 is applied, the clock signal CP3 is applied from the output to the shift register 29-7 and the counter 29-16 via the OR circuit 29-15. Therefore, when this clock signal CP3 is applied twice, the release time set value that was shifted and stored in the storage element 29-10 at the above-mentioned stage is stored in the storage element 29-8, and is sent to the decoder 29-2.
At the same time, the output of the OR circuit 29-17 becomes "0" and the gate of the AND circuit 29-48 is prohibited.

The binary counter 29-41 is connected to an OR circuit 29-49, an AND circuit 29-51 to which a down command signal is coupled when a "0" state is detected by an inverter 29-50, and an inverter 29-50.
52, the AND circuits 29-39 are inhibited and the counting is stopped. Further, a clear signal for initial setting is applied to the shift register 29-7, counter 29-16, and binary counter 29-41.

In addition, CP3 is 32KHz, which is CP1 divided by 2.
(31.25 μs), the output of the OR circuits 29-38 is 62.5 μs, 125 μs…1024 ms, depending on the attack time, decay time, and release time settings “0”, “15”, respectively. 2048ms
A clock with a period of is obtained. Therefore, since this clock is counted by the binary counter 29-41, the time from key-on to the end of the attack state (start of decay) is 2 ms, 4 ms, . . . 32.768 s, and 65.536 s, respectively.

Next, the operation of the envelope control method based on the above embodiment will be explained.

First, prior to performance, the attack time, decay time, sustain level, and release time are digitized in advance into the shift register 29-7 in FIG. 7 in accordance with the volume envelope shown in FIG. -11,29-10,
29-9 and 29-8.

That is, in the key input device 29-1, one of the keys "0"..."15" is selected in sequence in the order of attack, decay, sustain, and release. For example, "5", "2", " If the numerical values ``8'' and ``4'' are specified, first the numerical value ``5'' is encoded by the decoder 29-2. On the other hand, this key operation causes the key operation signal to be sent to the OR circuit 29-1.
2 to the AND circuit 29-14 and the DF/F circuit 29-13, the AND circuit 29-1
A one shot signal is output from 4 and OR circuit 2
It is supplied as a shift command to the shift register 29-7 via 9-15. Therefore, the decoder 29
“1010” numerically encoded with -2 is OR circuit 2
Storage element 29- through 9-3, ..., 29-6
8 is stored. Next, "0100" coded by operating the numerical value "2" is output from the storage element 29-15 based on the shift command output from the OR circuit 29-15.
8 and the previous encoded numerical value "5" is shifted and stored in storage element 29-9. Thereafter, the numbers "8" and "4" are sequentially changed to the shift register 29 in the same manner.
-7, and finally the coded numerical value "4" is stored in the storage element 29-8, the coded numerical value "8" is stored in the storage element 29-9, the coded numerical value "2" is stored in the storage element 29-10, and the coded numerical value "2" is stored in the storage element 29-10. 29-11 coded numerical value “5”
will be retained in memory. Decoder 29-2
The output 1, ..., 16 of 0 is the numerical value "1", ...,
The clock signals CP3 are decoded in order from the smallest number of ``15'', and the smaller the number, the faster the clock signal CP3 is counted.

In the key matrix circuit 1 shown in Fig. 3, if the X key is operated during performance, the timing signal will be 84 as shown in Fig. 9.
The clock signal CP1 is set as a “1” signal with a signal present at the “4” bit position of the bit shift register 18.
is stored in synchronization with the shift operation. on the other hand,
This X key operation timing signal is AND circuit 2
AND circuit 2 of envelope circuit 29 via 7
9-46 as an attack signal. Therefore, the attack time value stored in storage element 29-11 of shift register 29-7 is shifted to storage element 29-8, and its output is supplied to decoder 29-20. Therefore, in the case of the decoder output corresponding to the set numerical value, for example "5", the binary counting circuit 29-21 outputs the decoder output corresponding to the set numerical value.
When the 16 clock signals CP3 are counted, an output signal is obtained from the AND circuit 29-26, and this output signal is sent to the OR circuit 29-38 and the AND circuit 29-29.
39, the binary counter 29-41 is
1" counting step and the attack time starts to rise. Further, the output signal from the AND circuit 29-26 is applied to the DF/F circuit 29-40 to clear the binary counting circuit 29-21, so that the clock signal CP3 is counted again from the initial state.
In this way, the AND circuit 29-26 increments the binary counter 29-41 until the count value "31" (11111) is reached every time the AND circuit 29-26 counts the 16 clock signals CP3. When the count value reaches "31", AND circuit 29-
Since the output signal is obtained from 47 and supplied to the OR circuit 29-12, a shift signal is generated from the OR circuit 29-15. Therefore, the set value "2" of the decay time is stored in the storage element 29-8 in a shift manner. be done. At this time, since the counter 29-16 has a signal at the c output, a down command signal is supplied from the inverter 29-42 to the binary counter 29-41.
During this decay time, the binary counting circuit 29-21 operates in the same manner as the attack time.
is the clock signal CP3 at a repetition period corresponding to the output of the decoder corresponding to the specified value "2".
In this case, the binary counter 29-41 is operated to count down from the count value "31".

At this decay time, when the attack signal from the AND circuit 27 is applied to the AND circuit 29-46 of the envelope circuit 29 by operating the performance key again, the clock signal CP3 is output from the AND circuit 29-46 and the OR circuit 29 -15 to shift register 29-7,
A counting step signal is supplied to the counter 29-16.
At this time, since the counter 29-16 is in the "0010" state, the AND circuit 29-46
Clock signal until 9-16 reaches "0100" state
It will output CP3 (in this case 3 shots),
Naturally, three shift commands are supplied to the shift register 29-7, and the set attack time value "5" is again shifted and stored in the storage element 29-8.

Therefore, as can be seen from the dotted line in FIG. 8, the volume is set to rise again from the middle of the decay time, and as described above, the binary counter 29- 41 is now incremented in the upward direction up to the count value "31". Binary counter 29-4
1, when the count value reaches "31", the decay time is set again, and the count is performed in the downward direction as described above.
Then, when the counted value of the binary counter 29-41 matches the sustain level value "8" shifted and stored in the storage element 29-11 during the down counting operation during this decay time, the matching circuit 29-
AND circuit 29-3 in response to the output signal from 43.
Gate 9 is closed and the counting operation is stopped.

At this sustain level, when the attack signal is applied from the AND circuit 27 to the AND circuits 29-46 of the envelope circuit 29 by operating the performance key again, the clock signal CP3 continues until the counter 29-16 reaches the "0100" state. OR circuit 2
9-15 (3 shots in this case), the attack time setting value "5" is shifted and stored in the memory element 29-8 again, and the volume changes again from the sustain level as shown by the dotted line in Figure 8. Set to rising state. Then, the operation is repeated as described above, and the binary counter 29-41 is counted in the upward direction until the count value reaches "31", after which the cycle shifts to the decay time.

When the release button is operated in this sustain level state, the AND circuit 29-48 outputs two clock signals CP3, and the set release time value "4" is shifted to the memory element 29-8. Become remembered. Therefore, as in the case of attack and daylighting mentioned above,
The binary counter 29-41 is operated to count down to a count value of "0" in accordance with the measurement time corresponding to the numerical value of the release time. Furthermore, when the attack signal is outputted from the AND circuit 27 and applied to the AND circuits 29-46 by operating the performance key again at the release time, the volume can be set to a rising state.

Therefore, the digital count value of the binary counter 29-41 is supplied to the D/A conversion circuit 32 as a volume envelope control signal as shown in FIG. 8, and is converted into an analog quantity to control the volume. be.

In Fig. 7, the key input device 29-1 is used to set the ADSR numerically using the numeric keys, but the dial setting method can also be used to set multiple ADSR values that are required in advance in the ROM (read-only memory). It can be changed in various ways, such as storing the ADSR value of the envelope and designating a desired address. Furthermore, the shift register 29-7 is not limited to a bit-parallel configuration, but may also be configured in a bit-serial configuration, or other memory may be used.
Furthermore, the configuration of the binary counting circuit 29-21 is not limited to the embodiment, and may be as shown in FIG. 10, for example. That is, FIG. 10 will be briefly explained. A 5-bit binary counter 38 for counting the clock signal CP3 is provided, and an AND circuit group 44 is formed by combining the outputs of each bit stage and the outputs thereof via the inverters 39, . . . , 43. From the 5 outputs of this AND circuit group 44, a binary counter 38
16, 8, 1 cycle count value "32"
The output is configured to obtain 4, 2, and 1 pulse signals. Furthermore, an OR circuit group 45 is configured such that 1, .
6, and the output of the AND circuit group 46 is supplied to an AND circuit 48 via an OR circuit 47. Therefore, the AND circuit 48 outputs as many clock signals CP3 as the number corresponding to the outputs of the designated decoders 29-20, and is applied to the AND circuits 29-39 in FIG. Further, it can also be configured as shown in FIG. That is, even if the output obtained by decoding each output of the binary counting circuit 29-21 in FIG. good.
Then, each time a match is detected, a binary counter 29-2
Make sure to clear 1.

It goes without saying that the circuit configuration based on this embodiment can be modified in various ways without departing from the gist of the present invention.

As detailed above, the present invention divides the envelope into multiple statuses, and provides numerical data for determining the time interval for statuses whose level changes over time, and for statuses that maintain a constant level. The performer can input numerical data for determining the level value, and is provided with calculation means for performing calculations in accordance with the time interval and level value determined by the input numerical data to obtain an envelope output. The envelope of the musical sound is controlled by this envelope output. Envelope control can be performed with a simple digital circuit configuration, and among the envelope statuses, the time interval and constant level of the status whose level changes with time Since the player can freely control the level value of the status that holds, it is possible to obtain various musical tones desired by the player in a more complete form.

[Brief explanation of drawings]

Fig. 1 is an overall configuration diagram according to the present invention, Fig. 2 is a diagram showing a performance keyboard, Fig. 3 is a detailed diagram of a key matrix circuit, Fig. 4 is a diagram showing a musical sound waveform, and Fig. 5 is a musical sound waveform. Figure 6 is a detailed diagram of the read address control circuit of Figure 5, Figure 7 is a detailed diagram of the envelope circuit, Figure 8 is an envelope waveform diagram, and Figure 9 is an explanation of key operation timing. 10 is a diagram showing another embodiment showing a part of the envelope circuit of FIG. 7, and FIG. 11 is a diagram illustrating another embodiment. 1... Key matrix circuit, 29... Envelope circuit, 29-1... Key input device, 29-
7...Shift register, 29-16...Counter, 29-20...Decoder, 29-21...Binary counting circuit, 29-22,..., 29-37...
...AND circuit, 29-39...AND circuit, 29
-41... Binary counter, 29-43... Match circuit, 29-46... AND circuit.

Claims (1)

[Claims] 1. A set of numerical data for inputting numerical data for determining the time interval of a status whose level changes over time and the level value of a status that maintains a constant level in an envelope consisting of a plurality of statuses. Numerical input means consisting of an input device; Storage means for sequentially storing numerical data input at different timings by operating a set of input devices of the numerical input means; and Numerical data stored in the storage means. Calculations are performed at a speed according to the numerical data used to determine the time interval to obtain an envelope output whose level changes over time, and an envelope output at a constant level is obtained according to the numerical data used to determine the stored level value. 1. An envelope control method for an electronic musical instrument, comprising: a calculation means for calculating the envelope output of the calculation means; and a control means for controlling an envelope of a musical tone based on an envelope output of the calculation means.