JPH0260893U - - Google Patents

Info

Publication number
JPH0260893U
JPH0260893U JP14135788U JP14135788U JPH0260893U JP H0260893 U JPH0260893 U JP H0260893U JP 14135788 U JP14135788 U JP 14135788U JP 14135788 U JP14135788 U JP 14135788U JP H0260893 U JPH0260893 U JP H0260893U
Authority
JP
Japan
Prior art keywords
symbol
refresh display
block diagram
display period
refresh
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14135788U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP14135788U priority Critical patent/JPH0260893U/ja
Publication of JPH0260893U publication Critical patent/JPH0260893U/ja
Pending legal-status Critical Current

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  • Radar Systems Or Details Thereof (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの考案の一実施例によるレーダ指示
機のシンボル・リフレツシユ表示装置のブロツク
図、第2図はこの考案の他の実施例を示すブロツ
ク図、第3図は従来のレーダ指示機のシンボル・
リフレツシユ表示装置のブロツク図である。 1はセクタ番号バツフア、2はセクタ番号デコ
ーダ、3はセクタ番号検出器、4はシンボル・デ
ータ書き込み選択スイツチ、5はシンボル・リフ
レツシユ表示用メモリ、6はCRT、7はシンボ
ル・リフレツシユ期間(セクタ数)設定スイツチ
、8は減算器、9は消去メモリ番号デコーダ、1
0はセクタ番号対応シンボル数カウンタ、11は
加算器、12はシンボル表示最大数設定値、13
は比較器、14はクリアするメモリ番号カウンタ
である。なお図中同一符号は同一又は相当部分を
示す。
Fig. 1 is a block diagram of a symbol refresh display device for a radar indicator according to one embodiment of this invention, Fig. 2 is a block diagram showing another embodiment of this invention, and Fig. 3 is a block diagram of a conventional radar indicator. symbol·
FIG. 2 is a block diagram of a refresh display device. 1 is a sector number buffer, 2 is a sector number decoder, 3 is a sector number detector, 4 is a symbol data write selection switch, 5 is a memory for symbol refresh display, 6 is a CRT, 7 is a symbol refresh period (number of sectors) ) Setting switch, 8 is a subtracter, 9 is an erase memory number decoder, 1
0 is the symbol number counter corresponding to the sector number, 11 is the adder, 12 is the maximum symbol display number setting value, 13
is a comparator, and 14 is a memory number counter to be cleared. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

【実用新案登録請求の範囲】 レーダ指示機において、 シンボルのリフレツシユ表示期間を所要の値に
設定するリフレツシユ表示期間設定手段を備えた
ことを特徴とするレーダ指示機。
[Claims for Utility Model Registration] A radar indicator characterized by comprising: a refresh display period setting means for setting a symbol refresh display period to a required value.
JP14135788U 1988-10-28 1988-10-28 Pending JPH0260893U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14135788U JPH0260893U (en) 1988-10-28 1988-10-28

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14135788U JPH0260893U (en) 1988-10-28 1988-10-28

Publications (1)

Publication Number Publication Date
JPH0260893U true JPH0260893U (en) 1990-05-07

Family

ID=31406343

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14135788U Pending JPH0260893U (en) 1988-10-28 1988-10-28

Country Status (1)

Country Link
JP (1) JPH0260893U (en)

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