JPH0341349U - - Google Patents

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Publication number
JPH0341349U
JPH0341349U JP10105689U JP10105689U JPH0341349U JP H0341349 U JPH0341349 U JP H0341349U JP 10105689 U JP10105689 U JP 10105689U JP 10105689 U JP10105689 U JP 10105689U JP H0341349 U JPH0341349 U JP H0341349U
Authority
JP
Japan
Prior art keywords
function
processor
bus
selection signal
address decoder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10105689U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP10105689U priority Critical patent/JPH0341349U/ja
Publication of JPH0341349U publication Critical patent/JPH0341349U/ja
Pending legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案に係る関数の自動選択装置の一
実施例の機能ブロツク図である。 1……プロセツサバス、2……データバスバツ
フア、3……内部データバス、4……アドレスデ
コーダ、5……アドレス選択信号、6……関数セ
レクタ、7……関数選択の外部要因、81〜8n
……メモリブロツク、91〜9n……メモリブロ
ツク選択信号。
FIG. 1 is a functional block diagram of an embodiment of an automatic function selection device according to the present invention. 1...Processor bus, 2...Data bus buffer, 3...Internal data bus, 4...Address decoder, 5...Address selection signal, 6...Function selector, 7...External factor for function selection, 81- 8n
...Memory block, 91-9n...Memory block selection signal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] プロセツサバスと、前記プロセツサバスと内部
データバスを接続するデータバスバツフアと、前
記プロセツサバスからのアドレスをデコードし関
数のポインタとエリアを判定するアドレスデコー
ダと、関数単位でプロセツサのインストラクシヨ
ンを書き込んだメモリブロツクと、前記アドレス
デコーダからの選択信号と外部要因とから必要な
関数を選択し前記メモリブロツクの選択信号を出
力する関数セレクタとからなることを特徴とする
関数の自動選択装置。
a processor bus, a data bus buffer that connects the processor bus and an internal data bus, an address decoder that decodes addresses from the processor bus and determines function pointers and areas, and a memory in which processor instructions are written for each function. 1. An automatic function selection device comprising: a block; and a function selector that selects a necessary function from a selection signal from the address decoder and an external factor and outputs a selection signal for the memory block.
JP10105689U 1989-08-31 1989-08-31 Pending JPH0341349U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10105689U JPH0341349U (en) 1989-08-31 1989-08-31

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10105689U JPH0341349U (en) 1989-08-31 1989-08-31

Publications (1)

Publication Number Publication Date
JPH0341349U true JPH0341349U (en) 1991-04-19

Family

ID=31650029

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10105689U Pending JPH0341349U (en) 1989-08-31 1989-08-31

Country Status (1)

Country Link
JP (1) JPH0341349U (en)

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