JPH0261818B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse circuit multiplexing processing circuit that multiplexes pulse circuits in which the timing of pulses as output signals has significance and selectively outputs the output pulses of these pulse circuits.

Conventionally, it has been extremely difficult to multiplex devices or circuits whose output is in the form of pulses and whose timing is an important factor for the following reasons. That is, (1) If multiplexed devices or circuits are independent, pulse outputs are difficult to match even if there is a slight difference in the operation timing of the circuits. Even though this shift in operation timing does not originally affect control performance at all, it is determined that the output of each multiplexer or circuit is incorrect because of the shift. (2) In general, a control system includes a detection device, in which there is always a certain physical error, and the timing of the output pulse of the multiplexing device or circuit is shifted due to this error. Furthermore, (3) in the case of a signal whose pulse timing is significant, it is necessary to perform multiplexing processing and output it to the controller at the moment it is output. Therefore, in conventional multiplex processing devices of this type, it is difficult to connect multiplexed devices or circuits in some way, or to use these devices or circuits in a dependent relationship (master-slave). However, the original functions of multiplexing, such as independence and redundancy, were partially sacrificed. Therefore, when the pulse output from a multiplexed device or circuit is used to control another device, such as a thyristor converter, it is preferable that the pulse be an energy-saving, narrow-width pulse. Since multiplexing becomes impossible even if there is a deviation, it is necessary to first convert the narrow width pulse output from the device or circuit into a wide pulse and then convert it again into a narrow width pulse. A conversion circuit was required.

An object of the present invention is to provide a pulse circuit multiplexing processing device that does not require a pulse conversion circuit without sacrificing redundancy or independence.

A feature of the present invention is that in a multiplexing processing device that selectively outputs pulse outputs of multiplexed pulse circuits, N pulse circuits and the output of each of the N pulse circuits are connected to one input terminal. and the pulse outputs of the N pulse circuits, and among these pulse outputs, i (1≦i≦
Consisting of a selection circuit that outputs an output permission signal to the other input terminal of the AND gate group at the time when the N-1)th pulse is output, and an OR gate that takes the logical sum of the outputs of each gate of the AND gate group. That's the point.

Embodiments of the present invention will be described below based on the drawings. FIG. 1 shows a conventional pulse circuit multiplexing processing device, in which 1A, 1B, 1
C is a pulse circuit that outputs a pulse signal at a predetermined timing, and the output terminals of these pulse circuits are one-shot circuits 2A, 2B, and 2C, respectively.
It is connected to one input terminal of each of AND gates 3A, 3B, and 3C via. The other input terminals of the AND gates 3A, 3B, and 3C are commonly connected to adjacent AND gates, and the outputs of these AND gates are ORed by an OR gate 5, and the output of the OR gate 5 is connected to a differentiating circuit. It is output to the outside via 6.

Next, the operation of the pulse circuit multiplexing processing device described above will be explained based on the time chart shown in FIG. In the above configuration, pulse circuits 1A, 1
When narrow-width pulses P _A , P _B , P _C (a, b, c in the same figure) with shifted timing are output from B and 1C, respectively, these narrow-width pulses P _A , P _B , and P _C are one shot. Wide pulse P _A ′, by circuits 2A, 2B, 2C
These wide pulses are converted into P _B ' and P _C ', and these wide pulses are inputted to one input terminal of AND gates 3A, 3B, and 3C. As a result, AND gates 3A, 3B,
3C outputs pulses P _A ″, P _B ″, and P _C ″ at the timings shown in g, h, and i in the figure, respectively, and in the end, the OR gate 5 outputs pulses P _B ″ from the rising edge of pulse P _A ″. A pulse P _W with a time width corresponding to the falling point is output (j in the same figure).Then, the differentiator circuit 6
It is converted again into a narrow pulse P _G and output to the outside. This narrow pulse P _G is generated by the pulse generation circuit 1A,
It is output at the same timing as the pulse output P _B of the pulse generation circuit which is output second among 1B and 1C.

In this way, conventional devices convert the narrow pulses output from each pulse circuit into wide pulses in order to eliminate the effects of timing shifts in the pulse outputs of the multiplexed pulse circuits, and then convert the narrow pulses into wide pulses. A conversion circuit is required, and particularly when applied to a thyristor control device, there is a drawback that the conversion circuit is required for each arm.

Next, FIG. 3 shows the configuration of an embodiment of the pulse circuit multiplexing processing device according to the present invention, and FIG. 4 shows a time chart showing its operation contents.

In general, the multiplexing method for pulse circuits is
There are 2AND, 2OUT, OF3, etc., but in this embodiment, the second output pulse is selectively output, and basically it is an OR configuration.

Now, in FIG. 3, each pulse circuit 1A, 1
Pulses P _A , P _B , P _C (fourth
Figures a, b, and c) are AND gates 20A and 2, respectively.
It is input to one input terminal of 0B and 20C.

On the other hand, flip-flop A (hereinafter referred to as FFA) uses the output of pulse circuit 1B or 1C to
Flip-flop B (hereinafter referred to as FFB) is set by the output of pulse circuit 1A or 1C, and flip-flop C (hereinafter referred to as FFC) is set by the output of pulse circuit 1A or 1B.
Final output of each output of pulse circuits 1A, 1B, 1C
We are creating output permission conditions to make it _PG .

Let us consider a case where the output P _A of the pulse circuit 1A is output faster than the outputs P _B and P _C of the other two pulse circuits 1B and 1C. In this case, pulse circuit 1A
The output P _A of sets FFB and FFC, and the outputs of these flip-flops are connected to the AND gate 20B,
20C is open and waiting. When a pulse P _B is output from the pulse circuit 1B in this state, this becomes the final output P _G. That is, the pulse circuits 1A, 1
Pulse circuit 1 outputs second among B and 1C
This means that the output pulse P _B of B is selected as the final output P _G. In this embodiment, the first output pulse is used to create the output permission condition, and the next output pulse is used as the final output. Since the probability that two or more multiplexed pulse circuits fail at the same time is extremely low, the probability that the second pulse output is a pulse with incorrect timing is also low.

Therefore, according to this embodiment, it is possible to avoid the problem that pulse outputs cannot be matched due to timing or errors inherent in the pulse circuit.

Furthermore, in the example above, the case where an erroneous pulse output is output early is described, but the same applies when the erroneous pulse output is output late. That is, if one of the three pulse circuits fails and the pulse is output late, the pulse output of the other two circuits is normal. This is because, out of the outputs of these two pulse circuits, the pulse that appears first creates an output permission condition, and the pulse that appears next is output. To prevent a late and erroneous output from being finally output, the multiplexing circuit is locked at the time when the final pulse is output. Furthermore, even if there is no output due to a failure in one of the three pulse circuits, a normal pulse output can be obtained by similarly selecting the second pulse to be output.

The reset conditions for flip-flops FFA, FFB, and FFC should be considered for each system, but the most common method (in the case of a control device using a microcomputer, etc.) is to reset the reset signal at the beginning of each process. There is a way to get it out.

As explained above, in this embodiment, multiplexing processing can be performed even if there is a slight timing difference without synchronizing the triplexed pulse circuits 1A, 1B, and 1C, and the detection system There is no possibility that a consistent output of pulses cannot be obtained due to individual errors in the control system. This method is actually 2OUT OF3, but the original 2OUT OF3
Rather, it is a time-series 2OUT OF3 (characteristic in that it does not AND the pulse outputs of each pulse circuit).

In the embodiment shown in FIG. 3, the or gate 10
The inputs of A, 10B, 10C and the OR gate 30 are:
Needless to say, it is preferable to provide electrical insulation.

Next, FIG. 5 shows an embodiment in which the present invention is applied to a high voltage DC control system. In this embodiment, it is used as a reset signal for flip-flops FFA, FFB, and FFC.
OFF pulse is used. In other words, in a high-voltage DC control device, when an ON pulse is output to the thyristor of a certain phase, the thyristor of the other phase is
An OFF pulse is output, and this OFF pulse is used as a reset signal.

Furthermore, when each pulse 1A, 1B, 1C is abnormal, the monitoring circuit 40 outputs a lock signal 50A, 50B, 50C.
is configured to output to each AND gate 20A, 20B, 20C, and other than these points, there is no difference in structure and operation from the embodiment shown in FIGS. 3 and 4.

Next, another embodiment of the present invention will be described based on FIGS. 6 and 7. FIG. 6 shows an example in which the pulse circuits are multiplied by N, and in the same figure, the outputs P _A , P _B ,
..., P _N are input to one input terminal of AND gates 3A, 3B, ..., 3N (Fig. 7A to
F) is input to input terminals 1 to n of the counter 60 in the gate pulse generation circuit 100. Here, the counter 60 is a preset counter, and can be preset by inputting a preset signal 70 to the preset terminal P.

Now, when the preset value "i" is preset to the counter 60 via the preset terminal P, the pulse circuits 1A to 1A are output from the output terminal _Q1 of the counter 60.
Of the pulse output output from 1N, i
At the time when the 7th pulse is output, in other words, when the count value of the counter 60 reaches "i" (7th
Figure D) Flip-flop (hereinafter referred to as FF) 6
A pulse signal is output to the set terminal S of No. 2 (G in the same figure), and the FF 62 is set. Then, from the FF62, an output permission signal 8 is sent to each AND gate 3A to 3N.
0 is output (I in the same figure), and the pulse circuits 1A~
At the time when the (i+1)th output of 1N is output (E in the same figure), a pulse P _J is output from one of the AND gate groups 3A to 3N to the OR gate 5, and this is output from the OR gate 5 to the outside as the final output _PG . (J in the same figure).

On the other hand, the reset of the FF62 is performed by the final output _PG , and the reset of the counter 60 is performed by the pulse circuit 1.
When all pulse signals are output from A to 1N,
That is, when the count value of the counter 60 reaches "n", the pulse signal 90 is output from the output terminal _Q2 .
(H in the figure) or the pulse signal 92 (K in the figure) obtained by delaying the final output P _G for a certain period of time via the delay circuit 66 (delay time td) is connected to the reset terminal R.
The system is configured to do this by inputting the following information:

In this embodiment, by selecting the preset value of the counter 60, it is possible to selectively output pulses output in a desired order as the final output among the pulses output from the pulse circuits 1A to 1N. Moreover, it goes without saying that the effects of the embodiments shown in FIGS. 3 to 5 can be similarly exhibited.

As described above, according to the present invention, it is possible to realize a pulse circuit multiplexing processing device that does not require a pulse conversion circuit, without sacrificing redundancy or independence.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a conventional pulse circuit multiplexing processing device, FIG. 2 is a time chart for explaining its operation, and FIG. 3 is a diagram of a pulse circuit multiplexing processing device according to the present invention. A block diagram showing the configuration of one embodiment, FIG. 4 is a time chart for explaining its operation, FIG. 5 is a block diagram showing the configuration of another embodiment of the present invention, and FIG. 6 is a further diagram of the present invention. A block diagram showing the configuration of another embodiment, and FIG. 7 are time charts for explaining its operation. 1A~1N...Pulse circuit, FFA, FFB, FFC
…Flip-flop, 60…Counter, 100…
Gate pulse generation circuit.

Claims (1)

[Claims] 1. In a multiplexing processing device that selectively outputs pulse outputs of multiplexed pulse circuits, N pulse circuits and an AND gate each receiving the output of each of the N pulse circuits at one input terminal thereof. and receiving pulse outputs of the N pulse circuits;
Of these pulse outputs, i (1≦i≦N-1)
A selection circuit that outputs an output permission signal to the other input terminal of the AND gate group at the time when the second pulse is output, and an OR gate that takes the logical sum of the outputs of each gate of the AND gate group. Characteristic pulse circuit multiplexing processing device.