JPH0262021A - Manufacture of semiconductor porcelain substrate of grain boundary insulation type - Google Patents
Manufacture of semiconductor porcelain substrate of grain boundary insulation typeInfo
- Publication number
- JPH0262021A JPH0262021A JP21243388A JP21243388A JPH0262021A JP H0262021 A JPH0262021 A JP H0262021A JP 21243388 A JP21243388 A JP 21243388A JP 21243388 A JP21243388 A JP 21243388A JP H0262021 A JPH0262021 A JP H0262021A
- Authority
- JP
- Japan
- Prior art keywords
- dielectric constant
- permittivity
- component
- porcelain
- composition
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 33
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 229910052573 porcelain Inorganic materials 0.000 title abstract description 30
- 238000009413 insulation Methods 0.000 title description 2
- 239000000203 mixture Substances 0.000 claims abstract description 32
- 238000000034 method Methods 0.000 claims abstract description 27
- 239000000919 ceramic Substances 0.000 claims description 28
- 238000009792 diffusion process Methods 0.000 claims description 10
- 238000010304 firing Methods 0.000 claims description 4
- 239000003990 capacitor Substances 0.000 abstract description 26
- 230000008569 process Effects 0.000 abstract description 8
- 239000001856 Ethyl cellulose Substances 0.000 abstract description 3
- ZZSNKZQZMQGXPY-UHFFFAOYSA-N Ethyl cellulose Chemical compound CCOCC1OC(OC)C(OCC)C(OCC)C1OC1C(O)C(O)C(OC)C(CO)O1 ZZSNKZQZMQGXPY-UHFFFAOYSA-N 0.000 abstract description 3
- 229920001249 ethyl cellulose Polymers 0.000 abstract description 3
- 235000019325 ethyl cellulose Nutrition 0.000 abstract description 3
- 238000001125 extrusion Methods 0.000 abstract description 3
- 239000002904 solvent Substances 0.000 abstract description 3
- 239000000725 suspension Substances 0.000 abstract description 3
- 239000000126 substance Substances 0.000 abstract 4
- 238000005192 partition Methods 0.000 abstract 1
- 239000011248 coating agent Substances 0.000 description 7
- 238000000576 coating method Methods 0.000 description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 6
- 239000012298 atmosphere Substances 0.000 description 5
- 230000008859 change Effects 0.000 description 5
- 230000007423 decrease Effects 0.000 description 5
- 238000005245 sintering Methods 0.000 description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- 238000005452 bending Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- NUJOXMJBOLGQSY-UHFFFAOYSA-N manganese dioxide Chemical compound O=[Mn]=O NUJOXMJBOLGQSY-UHFFFAOYSA-N 0.000 description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 239000011230 binding agent Substances 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- 239000000843 powder Substances 0.000 description 3
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 2
- 229910002370 SrTiO3 Inorganic materials 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- 239000000654 additive Substances 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- 238000001354 calcination Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 125000001495 ethyl group Chemical group [H]C([H])([H])C([H])([H])* 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000007935 neutral effect Effects 0.000 description 2
- 230000001737 promoting effect Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 1
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 150000004649 carbonic acid derivatives Chemical class 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000007606 doctor blade method Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 235000019441 ethanol Nutrition 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 150000002603 lanthanum Chemical class 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229920000609 methyl cellulose Polymers 0.000 description 1
- 239000001923 methylcellulose Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 238000002791 soaking Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Landscapes
- Ceramic Capacitors (AREA)
- Inorganic Insulating Materials (AREA)
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明は、2種以上の誘電率を有し、複数個のコンデン
サを内蔵する種々の電子回路用基板あるいは基体に用い
ることができる粒界絶縁型半導体磁器基板の製造方法に
関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention is directed to a grain boundary method that has two or more types of dielectric constants and can be used for various electronic circuit boards or substrates containing a plurality of capacitors. The present invention relates to a method for manufacturing an insulated semiconductor ceramic substrate.
(従来の技術) 近年、電子機器の小型化の動きが活発である。(Conventional technology) In recent years, there has been an active movement toward miniaturization of electronic devices.
このなかで、磁器基板は、その表面上に厚膜法または薄
膜法によって形成された導体回路、抵抗などを有し、さ
らにチップ形態のコンデンサおよびインダクタンス等を
実装している。しかし、この基板はその役割がただ単に
前記電子部品類を載せることにあるため、いわば電気機
能的には空間となっており、この空間内すなわち基板内
に前記電子部品の一部を移すことによって、さらに小型
化を計る試みが行われている。具体的な例として、誘電
体シートを多層化することによりコンデンサを基板内に
内蔵させて小型化する技術が提案されている。Among these, the ceramic substrate has a conductive circuit, a resistor, etc. formed by a thick film method or a thin film method on its surface, and further has chip-shaped capacitors, inductances, etc. mounted thereon. However, since the role of this board is simply to mount the electronic components, it is, so to speak, a space in terms of electrical functionality, and by moving some of the electronic components into this space, that is, into the board , attempts are being made to further reduce the size. As a specific example, a technique has been proposed in which a capacitor is built into a substrate and miniaturized by multilayering dielectric sheets.
(発明が解決しようとする課題)
しかし、誘電体シートを多層化したタイプのコンデンサ
内蔵基板は、誘電体シートと電極材料とを交互に積層し
て多層化するため、工程が煩雑になるとともに、内蔵コ
ンデンサ相互間に容量(以下クロス容量という)が大き
いため信号の漏洩憤を無視出来ないという問題点を有す
る。すなわち、コンデンサ内蔵基板を、基板内に複数個
のコンデンサがそれぞれ電気的に十分に分離された状態
で、しかも簡便な方法で形成することは、従来困難であ
った。(Problems to be Solved by the Invention) However, the type of capacitor-embedded substrate made of multilayered dielectric sheets is made up of multiple layers by alternately laminating dielectric sheets and electrode materials, which makes the process complicated and Since the capacitance between the built-in capacitors (hereinafter referred to as cross capacitance) is large, there is a problem in that signal leakage cannot be ignored. That is, it has conventionally been difficult to form a capacitor-embedded substrate in a state in which a plurality of capacitors are sufficiently electrically isolated from each other in a simple manner.
本発明の目的は、誘電率の高い粒界絶縁型半導体磁器か
らなる複数個のコンデンサを、それぞれ電気的に十分に
分離され、さらに機械的強度の低下がなく、かつ形状的
なゆがみのない状態で内蔵させることのできる磁器基板
の製造方法を提供することにある。It is an object of the present invention to connect a plurality of capacitors made of grain-boundary insulated semiconductor porcelain with a high dielectric constant to a state in which they are sufficiently electrically isolated from each other, without a decrease in mechanical strength, and without shape distortion. It is an object of the present invention to provide a method for manufacturing a ceramic substrate that can be incorporated in a ceramic substrate.
(課題を解決するための手段)
本発明は、第1段階として.SrTiO3を主成分とし
原子価制御剤を含有する高誘電率組成物からなる成形体
の主表面上に、Can、 SrOおよびBaOからなる
群から選ばれた少なくとも1種の低誘電率用成分を、あ
るいはCab、 SrOおよびBaOからなる群から選
ばれた少なくとも1種の成分55.0〜99.9モル%
と5ill□、 TiO□、 MnO□、 CuOおよ
びZnOからなる群から選ばれた少なくとも1種の成分
45.1〜0.1モル%とからなる低誘電率用組成物を
、複数個の領域が画成されるように供給し;第2段階と
して前記低誘電率用成分を前記成形体の内部に拡散させ
;第3段階として結晶粒界を絶縁することを特徴とする
粒界絶縁型半導体磁器の製造方法に関するものである。(Means for Solving the Problems) The present invention, as a first step. At least one component for low dielectric constant selected from the group consisting of Can, SrO and BaO is applied on the main surface of a molded body made of a high dielectric constant composition containing SrTiO3 as a main component and a valence control agent. Or 55.0 to 99.9 mol% of at least one component selected from the group consisting of Cab, SrO and BaO
and 45.1 to 0.1 mol% of at least one component selected from the group consisting of 5ill□, TiO□, MnO□, CuO and ZnO, in which a plurality of regions Grain boundary insulated semiconductor porcelain, characterized in that: as a second step, the low dielectric constant component is diffused into the molded body; and as a third step, grain boundaries are insulated. The present invention relates to a manufacturing method.
なお、上記低誘電率用成分、および低誘電率用組成物を
構成する成分は、すべて酸化物として記述したが、その
炭酸塩をも包含するものである。Note that although all of the components constituting the low dielectric constant component and the low dielectric constant composition are described as oxides, carbonates thereof are also included.
本発明方法の好適例では、拡散を焼成により行う。この
場合には拡散に特別な工程を必要とせず、通常粒界絶縁
型磁器基板の製造上必要とされる焼成工程の中で拡散が
実現されるという利点がある。In a preferred embodiment of the method according to the invention, the diffusion is carried out by calcination. In this case, there is an advantage that no special process is required for diffusion, and diffusion can be achieved during the firing process normally required for manufacturing grain boundary insulated ceramic substrates.
ここに「低誘電率用成分」または「低誘電率用組成物」
とは、高誘電率成形体を低誘電率に変えるために加えら
れる成分または組成物を意味するものとする。また「組
成物」とは、混合物のほかに化合物を包含するものとす
る。"Low dielectric constant component" or "low dielectric constant composition" here
shall mean a component or composition added to convert a high dielectric constant molded body to a low dielectric constant. Furthermore, the term "composition" includes compounds in addition to mixtures.
次に本発明を図面を参照して例について説明する。The invention will now be explained by way of example with reference to the drawings.
第1図は本発明方法によって製造した2種の誘電率を有
する粒界絶縁型半導体磁器基板の断面図であり、第2図
は第1図の磁器基板においてコンデンサとして用いる部
分に電極が形成されているコンデンサ内蔵磁器基板の断
面図である。第1図および第2図において、1はコンデ
ンサとして用いられる高誘電率領域であり、2は内蔵コ
ンデンサ相互間の容量を低下させるための低誘電率領域
であり、3はコンデンサの電極であり、6は粒界絶縁型
半導体磁器基板である。FIG. 1 is a cross-sectional view of a grain-boundary insulated semiconductor ceramic substrate having two types of permittivity manufactured by the method of the present invention, and FIG. 2 is a cross-sectional view of the ceramic substrate of FIG. FIG. 2 is a cross-sectional view of a ceramic substrate with a built-in capacitor. In FIGS. 1 and 2, 1 is a high dielectric constant region used as a capacitor, 2 is a low dielectric constant region for reducing the capacitance between built-in capacitors, and 3 is an electrode of the capacitor. 6 is a grain boundary insulated semiconductor ceramic substrate.
コンデンサとして用いられる高誘電率領域1において、
その誘電率は15000以上とするのが好ましい。この
場合にはセラミックの厚さが変化したとしても、コンデ
ンサ容量として1000pF以上のものを形成すること
ができ、汎用されているセラミックチップコンデンサの
内のかなり多くの種類のコンデンサを磁器内に形成する
ことができる。In the high dielectric constant region 1 used as a capacitor,
The dielectric constant is preferably 15,000 or more. In this case, even if the thickness of the ceramic changes, it is possible to form a capacitor with a capacitance of 1000 pF or more, and many types of capacitors among the commonly used ceramic chip capacitors can be formed in ceramic. be able to.
また、コンデンサを構成する磁器としては誘電率のほか
に誘電損失(tanδ)、温度特性などの性能が良好な
ものが求められている。それらを満足するものとしてS
rTiO3を主成分とする粒界絶縁型半導体磁器が知ら
れている。Furthermore, the ceramic constituting the capacitor is required to have good performance in terms of not only dielectric constant but also dielectric loss (tan δ) and temperature characteristics. As something that satisfies them, S
Grain boundary insulated semiconductor porcelain whose main component is rTiO3 is known.
SrTiO3を主成分とする粒界絶縁型半導体磁器の構
成成分として、Y2O,、Nb、O,Ta2Us、 W
O,および1、a203をはじめとするランタン系列元
素酸化物からなる群から選ばれた少なくとも1種の原子
価制御剤が用いられる。さらに、高誘電率を得るには、
磁器の結晶粒子径を大きくする必要があるが、そのため
に適当な添加剤を加えることも行われる。The constituent components of grain boundary insulated semiconductor porcelain mainly composed of SrTiO3 include Y2O,, Nb, O, Ta2Us, W
At least one valence control agent selected from the group consisting of oxides of lanthanum series elements including O, 1, and a203 is used. Furthermore, to obtain a high dielectric constant,
It is necessary to increase the crystal grain size of porcelain, and for this purpose, appropriate additives are also added.
IAnO,、Cub、 5in2. Zr0zなどの添
加剤はその例である。IAnO,,Cub, 5in2. Additives such as Zr0z are examples.
一方、主成分のSrT i03については、その温度特
性、誘電率、誘電損失などの大きさを調整するために、
Sr対T1の比を1:1から若干変化させたり、Srの
一部をCaおよびBaで置換することも可能である。On the other hand, in order to adjust the temperature characteristics, dielectric constant, dielectric loss, etc. of the main component SrT i03,
It is also possible to slightly change the ratio of Sr to T1 from 1:1 or to replace a portion of Sr with Ca and Ba.
上述の組成を有する高誘電率領域を複数個の領域に分離
するために、第1図に示すように低誘電率領域2を基板
内に設けるが、以下にその方法について第3〜6図を参
照して説明する。In order to separate the high dielectric constant region having the above-mentioned composition into a plurality of regions, a low dielectric constant region 2 is provided in the substrate as shown in FIG. 1. Refer to and explain.
先ず、第1段階として:
1)誘電率15000以」二の高誘電率組成物からなる
成形体4を押出成形法、ドクターブレード法などにより
得る。First, as a first step: 1) A molded body 4 made of a high dielectric constant composition having a dielectric constant of 15,000 or more is obtained by an extrusion method, a doctor blade method, or the like.
2)第3図に示すように、形成体4の主表面(好ましく
は表および裏の対向する両面)の所定部分に、上述の低
誘電率用成分または低誘電用組成物を、これにエチルセ
ルロース、溶剤などを加えて得たペースト5として塗布
する。この場合に、ペーストの塗布幅としては0.1m
l11以上、望ましくは0.2mm以上が必要とされる
。2) As shown in FIG. 3, the above-mentioned low dielectric constant component or low dielectric composition is applied to a predetermined portion of the main surface (preferably both the front and back surfaces) of the formed body 4, and ethyl cellulose is added thereto. , a solvent and the like are added to form a paste 5. In this case, the paste application width is 0.1 m.
The diameter is required to be l11 or more, preferably 0.2 mm or more.
次いで、第2段階として:
3)成形体中および塗布ペースト中のバインダー成分を
除(ために大気中600〜1200℃で仮焼する。Then, as a second step: 3) Calcinate at 600 to 1200° C. in the atmosphere to remove the binder component in the molded body and the coating paste.
4)この仮焼体を水素と窒素との混合ガス、水素とアル
ゴンとの混合ガスなどの還元性雰囲気、あるいは窒素、
アルゴンなどの中性雰囲気中において、1320〜14
50℃で焼成して半導体磁器を得る。またこの過程で、
塗布したペースト5中の低誘電率用成分または低誘電率
用組成物は成形体の内部に拡散し、半導体磁器基板6が
生ずる(第4図参照)。4) This calcined body is placed in a reducing atmosphere such as a mixed gas of hydrogen and nitrogen, a mixed gas of hydrogen and argon, or nitrogen,
1320-14 in a neutral atmosphere such as argon
Sintering is performed at 50° C. to obtain semiconductor porcelain. Also, in this process,
The low dielectric constant component or the low dielectric constant composition in the applied paste 5 diffuses into the molded body to form a semiconductor ceramic substrate 6 (see FIG. 4).
しかる後に、第3段階として;
5)この半導体磁器の結晶粒界を絶縁するため、例えば
重皇比が81□03/CIJO/エチルアルコール−0
,710、3/10またはPbO/エチルアルコール−
1/10である懸濁液等にドブ漬けした後に、大気中に
て1100℃〜1300℃で焼成する。これによりペー
スト5を塗布した部分は低誘電率磁器2となり、残りの
部分は高誘電率磁器1である。かくして、高誘電率磁器
1と低誘電率磁器2とからなる粒界絶縁型半導体磁器基
板6が得られる。After that, as a third step; 5) In order to insulate the crystal grain boundaries of this semiconductor porcelain, for example, the double-layer ratio is 81□03/CIJO/ethyl alcohol-0.
,710,3/10 or PbO/ethyl alcohol-
After soaking in a 1/10 suspension or the like, it is fired at 1100°C to 1300°C in the air. As a result, the part to which the paste 5 is applied becomes the low-permittivity porcelain 2, and the remaining part becomes the high-permittivity porcelain 1. In this way, a grain boundary insulated semiconductor ceramic substrate 6 consisting of the high dielectric constant ceramic 1 and the low dielectric constant ceramic 2 is obtained.
なお、粒界絶縁型半導体磁器基板6の主表面上の所望の
場合にAg、 Au、 AI、 Ni、 Cu、 2n
、 Ag−Pdなどの電極3を焼きつけることにより、
コンデンサを形成することができる。Note that Ag, Au, AI, Ni, Cu, 2n may be added to the main surface of the grain boundary insulated semiconductor ceramic substrate 6 as desired.
, By baking the electrode 3 such as Ag-Pd,
A capacitor can be formed.
なお、低誘電率化の確認は、隣り合ったコンデンサ間の
容重、すなわちクロス容量を測定することにより行うこ
とができる。Note that the reduction in dielectric constant can be confirmed by measuring the capacitance between adjacent capacitors, that is, the cross capacitance.
また、本発明方法により得られる磁器基板の基板として
の強度は、高誘電率領域のみの場合より、著しく強度が
工場する。Further, the strength of the ceramic substrate obtained by the method of the present invention as a substrate is significantly higher than that in the case of only a high dielectric constant region.
上述のように、本発明方法によりコンデンサとしての特
性が良好で、クロス容量の大幅な低減を示すコンデンサ
を内蔵させることができ、かつ、機械的強度が良好な基
板を製造することができる。As described above, the method of the present invention makes it possible to incorporate a capacitor with good capacitor characteristics and a significant reduction in cross capacitance, and to manufacture a substrate with good mechanical strength.
(作 用)
粒界絶縁後に高誘電率磁器を形成する成形体の所定の表
面上に塗布されるCab、 SrOおよびBaOからな
る群から選ばれた少なくとも1種の低誘電率用成分、ま
たはCab、 SrOおよびBaOからなる群から選ば
れた少なくとも1種の成分55.0〜99.9モル%と
Sin□、 Tin2. MnO7,CuOおよびZn
からなる群から選ばれた少なくとも1種の成分45.0
−0.1モル%とからなる低誘電率用組成物の作用を、
以下に説明する。(Function) At least one low dielectric constant component selected from the group consisting of Cab, SrO and BaO, or Cab applied on a predetermined surface of a molded body forming a high dielectric constant porcelain after grain boundary insulation. , 55.0 to 99.9 mol% of at least one component selected from the group consisting of SrO and BaO, and Sin□, Tin2. MnO7, CuO and Zn
At least one component selected from the group consisting of 45.0
-0.1 mol% of the composition for low dielectric constant,
This will be explained below.
まず、これらの低誘電率用成分または組成物を塗布物と
した場合には、塗布物の特徴として、塗布の有無により
焼結後の収縮率が大きく変化しない点を挙げることがで
きる。これにより、焼結体としての形状的なゆがみは例
えばAl2O3および5IO2の混合物を塗布物とした
場合よりも顕著に軽減され、優れた寸法安定性が得られ
る。First, when these components or compositions for low dielectric constant are used as a coated article, a characteristic of the coated article is that the shrinkage rate after sintering does not change significantly depending on whether or not it is coated. As a result, the shape distortion of the sintered body is significantly reduced compared to, for example, when a mixture of Al2O3 and 5IO2 is applied, and excellent dimensional stability is obtained.
前記高誘電率組成物からなる成形体にCab、 SrO
およびBaOからなる群から選ばれた少なくとも1種の
成分を添加した場合には、その添加量の増加とともに半
導体磁器の結晶粒径は小さくなり、体積抵抗率は増大し
、その結果誘電率は顕著に低下する。つまり、Can、
SrOおよびBaOからなる群から選ばれた少なくと
も1種の成分の存在により、高誘電率組成物は選択的に
低誘電率組成物に転化する。Cab, SrO are added to the molded body made of the high dielectric constant composition.
When at least one component selected from the group consisting of decreases to In other words, Can,
The presence of at least one component selected from the group consisting of SrO and BaO selectively converts the high dielectric constant composition into a low dielectric constant composition.
次に、Cab、 SrOおよびBaOからなる群から選
ばれた少なくとも1種の成分を高誘電率組成物からなる
成形体に塗布し、次いで粒界絶縁型半導体磁器の通常の
工程に従い、空気中焼成により脱バインダー後に、中性
または還元性の雰囲気中で焼成することにより、塗布物
は磁器内部へ拡散し、拡散域は低誘電率領域に転化する
。但し、Cab、 SrQおよびBaOの磁器内部への
拡散速度は比較的遅いため、成形体くすなわち磁器)の
厚さが厚い場合には、磁器内部への拡散が不十分となり
誘電率の低下も鈍化する。つまりCab、 SrOおよ
びBaOからなる群から選ばれた少なくとも1種の成分
を成形体表面に塗布することは、成形体くすなわち磁器
)の厚さがさほど厚くない場合、例えば磁器の厚さが0
.6ml!!以下程度以下台に有効である。Next, at least one component selected from the group consisting of Cab, SrO and BaO is applied to a molded body made of a high dielectric constant composition, and then fired in air according to the usual process for grain boundary insulated semiconductor porcelain. After removing the binder, the coating material is diffused into the interior of the porcelain by firing in a neutral or reducing atmosphere, and the diffusion region is converted into a low dielectric constant region. However, the diffusion rate of Cab, SrQ, and BaO into the interior of the porcelain is relatively slow, so if the molded body (i.e., porcelain) is thick, the diffusion into the interior of the porcelain will be insufficient and the decrease in dielectric constant will slow down. do. In other words, applying at least one component selected from the group consisting of Cab, SrO, and BaO to the surface of the molded product is effective when the thickness of the molded product (i.e., porcelain) is not very thick, for example, when the thickness of the porcelain is 0.
.. 6ml! ! It is effective for the following degrees and below.
これに対し、Cab、 SrOおよびBaOからなる群
から選ばれた少なくとも1種の成分55.0〜99.9
モル%と5in2. Tie□、 MnO□、 CuO
およびZnOからなる群から選ばれた少なくとも1種の
成分45.0〜0.1モル%とからなる低誘電率組成物
を塗布した場合には、磁器の厚さがおよそ0.6+nm
を超えても誘電率が顕著に低下する。従って、Sin、
、 Tin、、 MnO7,CuOおよび2nOはそれ
自体磁器内部に拡散するとともに、[aO,SrOおよ
びBaOの成形体内部への拡散を促進する作用を有する
。On the other hand, at least one component selected from the group consisting of Cab, SrO and BaO 55.0 to 99.9
Mol% and 5in2. Tie□, MnO□, CuO
When a low dielectric constant composition consisting of 45.0 to 0.1 mol% of at least one component selected from the group consisting of
The dielectric constant decreases significantly even if it exceeds Therefore, Sin,
, Tin, , MnO7, CuO and 2nO diffuse into the interior of the porcelain and have the effect of promoting the diffusion of [aO, SrO and BaO into the molded body.
また、5i02. Tin、、 MnO2,CuOおよ
びZnOは、低誘電率領域の機械的強度を顕著に向上さ
せる効果を有する。Also, 5i02. Tin, MnO2, CuO, and ZnO have the effect of significantly improving the mechanical strength of the low dielectric constant region.
低誘電率用組成物における組成の数値限定理由は次の通
りである。SiO□、Tin□、 MnO□、 Cur
lおよびZnOからなる群から選ばれた少なくとも1種
の成分が、45.0モル%を超えた場合には、高誘電率
から低誘電率への転化が鈍くなるとともに、曲げ強度で
代表される機械的強度が顕著に低下する。逆に、0.1
モル%未満ではCan、 SrOおよびBaOの磁器内
部への拡散促進効果が低下し、磁器の厚さが厚い場合に
は、高誘電率から低誘電率への転化が顕著に鈍くなると
ともに、機械的強度の向上が認められなくなるので好ま
しくない。The reason for limiting the numerical value of the composition in the composition for low dielectric constant is as follows. SiO□, Tin□, MnO□, Cur
When at least one component selected from the group consisting of ZnO and ZnO exceeds 45.0 mol%, the conversion from high dielectric constant to low dielectric constant becomes slow, and the bending strength is Mechanical strength decreases significantly. On the contrary, 0.1
If it is less than mol%, the effect of promoting the diffusion of Can, SrO, and BaO into the interior of the porcelain will be reduced, and if the thickness of the porcelain is thick, the conversion from a high dielectric constant to a low dielectric constant will be markedly slow, and the mechanical This is not preferable because no improvement in strength will be recognized.
所要の塗布量は成形体の厚さによって変化し、厚くなる
ほど塗布量が増加するが、通常多用されている回路磁器
基板の厚さは最大で1.6化までであるので、塗布面積
当り20mg/ am2以下の塗布量で十分である。2
0mg/ 0m2を超えて塗布した場合には、機械的強
度が大幅に低下するので好ましくない。The required amount of coating varies depending on the thickness of the molded body, and the thicker it is, the more the amount of coating increases, but since the thickness of commonly used circuit porcelain substrates is up to 1.6 mm, it is necessary to apply 20 mg per coated area. A coating amount of / am2 or less is sufficient. 2
If it is applied in an amount exceeding 0 mg/0 m2, the mechanical strength will be significantly reduced, which is not preferable.
(発明の効果)
本発明方法によれば、2種以上の誘電率を有する領域か
らなる磁器基板が得られるので、複数個のコンデンサ部
をそれぞれ電気的に十分に分離された状態で内蔵させる
ことができ、従って回路基板、ひいては電子機器の小型
化および高性能化に大きく貢献することができる。(Effects of the Invention) According to the method of the present invention, a ceramic substrate consisting of regions having two or more types of dielectric constants can be obtained, so that a plurality of capacitor parts can be incorporated in a state where they are sufficiently electrically isolated from each other. Therefore, it can greatly contribute to the miniaturization and performance improvement of circuit boards and, ultimately, electronic devices.
また、Can、 SrOおよびBaOからなる群から測
定した少なくとも1種の成分とSin、、 TiO2,
MnO2゜CuOおよびZnOからなる群から選定した
少なくとも1種の成分とを併用した場合には、拡散によ
り低誘電率化した領域は、高誘電率領域より機械的強度
がさらに増大しており、製造工程での破損などの不良発
生を軽減することもできる。Furthermore, at least one component measured from the group consisting of Can, SrO and BaO and Sin, TiO2,
When MnO2゜CuO and at least one component selected from the group consisting of ZnO are used in combination, the region with a low dielectric constant due to diffusion has a higher mechanical strength than the high dielectric constant region, making it easier to manufacture. It is also possible to reduce the occurrence of defects such as damage during the process.
加えて、低誘電率用成分または組成物を塗布拡散させた
部分つまり低誘電率領域と高誘電率領域との焼結時の収
縮率がほぼ等しいため、形状的なゆがみが少なく、厚膜
工程での位置決め精度なども、通常のAI□03基板と
同等である。In addition, the shrinkage rate during sintering of the part where the low dielectric constant component or composition is applied and diffused, that is, the low dielectric constant region and the high dielectric constant region, is almost equal, so there is little distortion in shape and it is easy to process thick films. The positioning accuracy is also the same as that of a normal AI□03 board.
(実施例) 次に本発明を実施例および比較例について説明する。(Example) Next, the present invention will be explained with reference to Examples and Comparative Examples.
第1表に示す組成物になるように各原料を秤取し、湿式
ボールミルで12時間粉砕混合し、乾燥した。次に空気
中1150℃、5時間で仮焼後、湿式ボールミルで18
時間粉砕した。この混合物を乾燥後、メチルセルロース
を加え、押出成形によりそれぞれ第2表に示す厚さの成
形体を得た。この成形体を18.8mm X 12.5
mmの大きさに打ち抜いた。成形体の表および裏の両面
に第3図に示すように、成形体4の中央位置で成形体の
短辺に平行に、第2表の「成形体への塗布物」の欄に示
す比率に調製した粉末と、エチルセルロースと、溶剤と
からなるぺ゛−ストを、上記粉末の壷が成形体における
塗布面積当り、第2表に示す値(mg/ cm’)にな
るように1.2mm幅で塗布した。なお、比較のために
塗布をしない試料も用意した。Each raw material was weighed out to give the composition shown in Table 1, pulverized and mixed in a wet ball mill for 12 hours, and dried. Next, after calcining in air at 1150℃ for 5 hours, it was heated to 18℃ in a wet ball mill.
Time crushed. After drying this mixture, methylcellulose was added and extrusion molded to obtain molded products having the thickness shown in Table 2. This molded body is 18.8mm x 12.5
It was punched out to a size of mm. As shown in FIG. 3, on both the front and back sides of the molded product, apply the ratio shown in the column of "Applied to the molded product" in Table 2, parallel to the short side of the molded product at the center position of the molded product 4. A paste consisting of the powder prepared in above, ethyl cellulose, and a solvent was mixed into a powder pot of 1.2 mm so that the powder had the value (mg/cm') shown in Table 2 per coated area of the molded body. It was applied in width. For comparison, a sample without coating was also prepared.
バインダー成分を除くために大気化中で900℃におい
て2時間仮焼した。次いで、水素10容量%と窒素90
容量%とからなる雰囲気中で、1400℃において4時
間焼成し、約20%焼結収縮した半導体磁器を得るとと
もに、前記塗布物を磁器内部へ拡散させた。この半導体
磁器を重量比でBi2O,/CuO/エチルアルコール
ー0.710.3/10の懸濁液にドブ漬は後、125
0℃、30分間空気中にて焼成して結晶粒界に絶縁層を
形成させた。In order to remove the binder component, it was calcined at 900° C. for 2 hours in an atmosphere of air. Then 10% by volume hydrogen and 90% nitrogen
% by volume at 1400° C. for 4 hours to obtain semiconductor porcelain that had sintered and shrunk by about 20%, and the coating material was diffused into the interior of the porcelain. This semiconductor porcelain was soaked in a suspension of Bi2O,/CuO/ethyl alcohol in a weight ratio of 0.710.3/10.
An insulating layer was formed at the grain boundaries by firing in air at 0° C. for 30 minutes.
このようにして得た第4図に示す半導体磁器基板6のコ
ンデンサ部として用いられる高誘電率領域1の両面に、
第5図に示すような形状で、l mmの間隔を置いてA
g電極3を焼き付けた。On both sides of the high dielectric constant region 1 used as the capacitor part of the semiconductor ceramic substrate 6 shown in FIG. 4 obtained in this way,
With the shape shown in Figure 5, A
g electrode 3 was baked.
次に、コンデンサ部の特性として、容量(nf)、見掛
けの誘電率、tan δ(%)および容量の温度変化率
を測定した。なお、容量の温度変化率とは、25℃の値
を基準として求めた一25℃〜+85℃の温度範囲にお
ける容量の変化率である。Next, the capacitance (nf), apparent dielectric constant, tan δ (%), and rate of change in capacitance with temperature were measured as characteristics of the capacitor section. Note that the rate of change in capacitance with temperature is the rate of change in capacitance in a temperature range of -25°C to +85°C, which is determined based on the value of 25°C.
なお、コンデンサ部の電気的な分離の状態を求めるため
に、同一平面上に位置する電極間の容量(クロス容量)
(pF) を測定した。In addition, in order to determine the state of electrical separation of the capacitor part, the capacitance between electrodes located on the same plane (cross capacitance)
(pF) was measured.
また、半導体磁器基板について、第4図のAおよびBで
示す線上に沿って切断し、幅2mm、厚さ15mmの試
験片を切り出し、第6図に示すように試料片を配置して
3点曲げ試験を行い、曲げ強度を測定した。In addition, the semiconductor ceramic substrate was cut along the lines A and B in Figure 4, a test piece with a width of 2 mm and a thickness of 15 mm was cut out, and the sample pieces were arranged as shown in Figure 6 and three points were cut out. A bending test was conducted to measure the bending strength.
また、成形体(18,8mm x 12.5 mm)の
短辺の長さ12.5mmに対し、焼き上がった磁器基板
の高誘電率領域および低誘電率領域における対応する長
さ(mmX第4図においてそれぞれβ1およびβ2で示
す)を測定し、次式により焼結による収縮率を求めた。In addition, with respect to the short side length of 12.5 mm of the molded body (18.8 mm x 12.5 mm), the corresponding length in the high dielectric constant region and low dielectric constant region of the fired ceramic substrate (mm x 4th (indicated by β1 and β2, respectively in the figure) were measured, and the shrinkage rate due to sintering was determined using the following formula.
これらの測定結果を第2表に示す。なお、第2表におい
て*印は比較例を示し、他のものは実施例を示す。The results of these measurements are shown in Table 2. In Table 2, * marks indicate comparative examples, and others indicate examples.
【図面の簡単な説明】
第1図は本発明方法により製造した粒界絶縁型半導体磁
器基板の1例の断面図、
第2図は第1図の磁器基板を用いたコンデンサ内蔵磁器
基板の断面図、
第3図は本発明方法において成形体に低誘電率用成分ま
たは組成物を供給した段階を示す斜視図、第4図は本発
明方法において低誘電率用成分または組成物を成形体の
内部に拡散させた段階を示す斜視図、
第5図は第2図のコンデンサ内蔵基板の一部の斜視図、
第6図は曲げ試験における試験片の配置を示す斜視図で
ある。
1・・・高誘電率領域(高誘電率磁器、コンデンサ部)
2・・・低誘電率領域(低誘電率磁器)3・・・電極
4・・・成形体(高誘電率組成物からなる成形体)5・
・・ペースト (低誘電率用成分または゛低誘電率用組
成物を含有するペースト)
6・・・粒界絶縁型半導体磁器基板
A、B・・・試験片を切り出した際の切断ラインβ1.
12・・・焼結後の長さ[Brief Description of the Drawings] Fig. 1 is a cross-sectional view of an example of a grain-boundary insulated semiconductor ceramic substrate manufactured by the method of the present invention, and Fig. 2 is a cross-sectional view of a capacitor-embedded ceramic substrate using the ceramic substrate of Fig. 1. Figure 3 is a perspective view showing a stage in which a low dielectric constant component or composition is supplied to a molded body in the method of the present invention, and Figure 4 is a perspective view showing a stage in which a low dielectric constant component or composition is supplied to a molded body in the method of the present invention. FIG. 5 is a perspective view of a part of the capacitor-embedded board of FIG. 2; FIG. 6 is a perspective view showing the arrangement of test pieces in a bending test. 1... High permittivity area (high permittivity porcelain, capacitor part)
2... Low dielectric constant region (low dielectric constant porcelain) 3... Electrode 4... Molded body (molded body made of high dielectric constant composition) 5.
...Paste (paste containing a component for low dielectric constant or a composition for low dielectric constant) 6... Grain boundary insulated semiconductor ceramic substrate A, B... Cutting line β1 when cutting out a test piece.
12... Length after sintering
Claims (3)
る高誘電率組成分からなる成形体の主表面上に、CaO
,SrOおよびBaOからなる群から選ばれた少なくと
も1種の低誘電率用成分を、複数個の領域が画成される
ように供給し、 前記低誘電率用成分を前記成形体の内部に 拡散させ、 しかる後に結晶粒界を絶縁する ことを特徴とする粒界絶縁型半導体磁器基板の製造方法
。1. CaO
, SrO, and BaO, and supplying at least one component for low dielectric constant selected from the group consisting of , SrO, and BaO so as to define a plurality of regions, and diffusing the component for low dielectric constant into the inside of the molded body. A method for manufacturing a grain boundary insulated semiconductor ceramic substrate, comprising: insulating the grain boundaries, and then insulating the grain boundaries.
aO,SrO,およびBaOからなる群から選ばれた少
なくとも1種の成分55.0〜99.9モル%とSiO
_2,TiO_2,MnO_2,CuOおよびZnOか
らなる群から選ばれた少なくとも1種の成分45.0〜
0.1モル%とからなる低誘電率用組成物を複数個の領
域が画成されるように供給する請求項1記載の方法。2. C on the main surface of the molded body made of the high dielectric constant composition.
55.0 to 99.9 mol% of at least one component selected from the group consisting of aO, SrO, and BaO and SiO
At least one component selected from the group consisting of _2, TiO_2, MnO_2, CuO and ZnO 45.0~
2. The method of claim 1, wherein the low dielectric constant composition comprising 0.1 mol % is provided so as to define a plurality of regions.
の方法。3. 3. The method according to claim 1, wherein said diffusion is performed by firing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21243388A JPH0262021A (en) | 1988-08-29 | 1988-08-29 | Manufacture of semiconductor porcelain substrate of grain boundary insulation type |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21243388A JPH0262021A (en) | 1988-08-29 | 1988-08-29 | Manufacture of semiconductor porcelain substrate of grain boundary insulation type |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0262021A true JPH0262021A (en) | 1990-03-01 |
Family
ID=16622521
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21243388A Pending JPH0262021A (en) | 1988-08-29 | 1988-08-29 | Manufacture of semiconductor porcelain substrate of grain boundary insulation type |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0262021A (en) |
-
1988
- 1988-08-29 JP JP21243388A patent/JPH0262021A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2001240466A (en) | Porcelain of dielectrics and electronic parts of laminated ceramics | |
| WO2010058496A1 (en) | Ceramic composition, ceramic green sheet, and ceramic electronic component | |
| JP2568208B2 (en) | Ceramic, circuit substrate and electronic circuit substrate using the same, and method of manufacturing ceramic | |
| KR20040057102A (en) | Low temperature sinterable dielectric composition, multilayer ceramic capacitor, ceramic electronic device | |
| KR102024028B1 (en) | OJ dielectric composition used for nickel electrode | |
| JP2608288B2 (en) | Ceramic, circuit board and electronic circuit board using the same | |
| JP2568204B2 (en) | Ceramic, circuit board and electronic circuit board using the same | |
| JPH025019B2 (en) | ||
| JPH0552602B2 (en) | ||
| JPH0262021A (en) | Manufacture of semiconductor porcelain substrate of grain boundary insulation type | |
| JPH02150010A (en) | Laminated porcelain capacitor | |
| JPH0236510A (en) | Manufacture of porcelain substrate with built-in capacitor | |
| JP2608289B2 (en) | Ceramic, circuit substrate and electronic circuit substrate using the same, and method of manufacturing ceramic | |
| JPH0296318A (en) | Manufacture of grain boundary insulation type semiconductor porcelain substrate | |
| JP3179830B2 (en) | Dielectric porcelain composition | |
| JPH02121392A (en) | Capacitor built-in composite circuit board and manufacture thereof | |
| JPH0243715A (en) | Manufacture of grain boundary insulating type semiconductor porcelain substrate | |
| JPS621596B2 (en) | ||
| JPH02141471A (en) | Ceramics substrate for containing reduction reoxidation type semiconductor ceramics capacitor and production thereof | |
| JPH03129810A (en) | Laminated type ceramic chip capacitor and manufacture thereof | |
| JPH04284610A (en) | Composite laminated component | |
| JPH02170512A (en) | Grain boundary insulation type semiconductor porcelain substrate and manufacture thereof | |
| JPH0756850B2 (en) | Ceramic multilayer capacitor and manufacturing method thereof | |
| JP2000143344A (en) | Dielectric ceramic composition and multilayer ceramic capacitor using the same | |
| JPH02177520A (en) | Manufacture of semiconductor porcelain substrate |