JPH0262066B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a communication control device for a data communication device. In particular, the present invention relates to a communication control device that reduces the number of steps by having hardware handle part of the processing performed by software.

[Description of Prior Art] The line control circuit of a conventional communication control device is, for example,
Periodically read reception control signals such as circuit numbers 106 and 107 of CCITT Recommendation V24 according to software instructions and detect changes in them, or create and execute various timer procedures for monitoring communication procedures using software. Was. Although these processes are simple processes, a large amount of software processing time is lost.

In particular, in the case of a common control type communication control device configured to control multiple communication lines with one processor, the burden on the control device increases, making it difficult to accommodate high-speed terminals and large numbers of terminals. A constraining problem had arisen.

FIG. 1 is a diagram showing the configuration of a conventional communication control device. Reference numeral 1 in the drawing denotes a processor connected via a common control bus 2 so as to control a plurality of line control units 3. In this explanation, for the sake of convenience, eight lines will be explained, and the line control circuit 3 uses an LSI commonly called a general-purpose transmission/reception control circuit. This LSI has
Line timers and reception control signal change detection circuits sufficient for control such as CCITT Recommendations V24 and V35 are not necessarily provided.

Reference numeral 4 in the drawing indicates an interface between data terminal equipment (DTE) and data control equipment (DCE) recommended in V24, V35, etc., which handles signals including a large number of transmission and reception control signals in addition to transmission and reception data. A modem 5 in the drawing connects the data terminal device 6 to the line control circuit 3. In such a communication control device, the control of the processor 1 requires the measurement of multiple line timers and the detection of multiple control signal changes for each line control, which requires a large amount of processing and requires a large amount of software. becomes complicated.

[Purpose of the invention]

The present invention reduces the processing amount of the control processor, simplifies its software, and
An object of the present invention is to provide a device that can increase the number of lines that can be controlled by a single control processor and increase the communication speed of the lines.

[Features of the invention]

The present invention provides each line control unit of a communication control device that controls multiple lines with a plurality of line timers based on a time division multiplex common control circuit and a plurality of receiving control signal change detection circuits that can be realized with small hardware as hardware. The configuration is configured to report to the software via an interrupt after the set time has elapsed or when a change occurs in the received control signal, reducing the number of software processing steps, allocating this time to other important processing, and increasing speed. It is characterized by being able to process lines and multiple communication lines.

In other words, the present invention improves the communication processing capacity of a communication control circuit accommodating multiple communication lines having functions such as CCITT Recommendations V24 and V35, by eliminating time counting and conventional control signal change detection, which were conventionally performed by a processor based on instructions from software. In order to improve the performance, it is implemented using separate hardware. That is, each line control circuit is provided with a time division multiplex control circuit using a memory that can be realized with a small amount of hardware, and provided with a plurality of line timer circuits for counting time and a plurality of reception control signal change detection circuits. If the line timer has a time value set by software and is started, a change in the received control signal is detected when the set time has elapsed, and if the change detection circuit is started by software, a change is detected in the received control signal. It is characterized in that it reports this to the software by interrupting the software, thereby improving the processing capacity of the software and making it possible to accommodate high-speed lines and a large number of communication lines.

[Explanation based on examples]

FIG. 2 is a block diagram of a device according to an embodiment of the present invention. Reference numerals 1, 2, 3, and 5 in the figure have the same names and functions as the respective parts explained in FIG. 1. Reference numeral 10 in the drawings represents a time division multiplex common control circuit added according to the present invention so that each modem 5 is connected to the common bus 2. In addition, in the present invention, for each line, the CCITT recommendation V24 indicated by reference numeral 11 in the drawing,
The V35 is characterized by having multiple reception control signal change detection circuits and multiple line timers. Reference numeral 12 in the drawing indicates a signal line of the data terminal-data control (DTE-DCE) device interface other than reception control signals.

Here, a circuit will be described using as an example a circuit having four line timers and four reception control signal change detection circuits per line, that is, eight lines and 32 line timers and 32 change detection circuits.

FIG. 3 is a format diagram of an address counter. This uses 32 line timers and 32
FIG. 4 is a 64-decimal address counter format diagram that specifies the processing time of each change detection circuit and a memory address. Reference numeral 21 in the drawing indicates bits “2 ³ ”, “2 ⁴ ” and “2 ⁵ ” of the address counter, which indicate memory addresses for 8 lines, and reference numeral 22 indicates the line timer section or change detection circuit section in each line memory. The "2 ⁰ " and "2 ¹ " bits 23 in the drawing indicate the line timer and change detection circuit numbers in the memory.

FIG. 4 shows a memory division state for time division multiplexing, which is periodically accessed by an address counter (51 in FIG. 5) corresponding to the format diagram of FIG. Reference numeral 30 in the figure is, for example, a 64-word memory, which is divided into memory areas corresponding to each line control section indicated by reference numerals 31, 32, . . . 38, and a line timer 39 and 40.
It is distinguished into the change detection part. The memory areas 39 and 40 are each divided into four line timer sections and four change detection sections.

FIG. 5 is a detailed block diagram of a device according to an embodiment of the present invention. The outputs of the 4-1 selection circuit 58 for line number 0 to the 4-1 selection circuit 59 for line number 7 are input to an 8-1 selection circuit 60 for line control, respectively. The output of the selection circuit 60 is input to the change detection circuit 62 via the current reception control signal 64. The output of the address counter 51 is sent from the 4-1 selection circuit 58 of the line number 0 to the line number 7 via the "2 ⁰ " and "2 ¹ " bits 23 of the address counter 51.
4-1 selection circuit 59, "2 ³ ", "2 ⁴ ",
8-1 for line control via "2 ⁵ " bit 21
It is input to the selection circuit 60, further inputted to the 2-1 selection circuit 56 via the "2 ² " bit 22, and further inputted to the memory 30 via the "2 ⁰ " to "2 ⁵ " bits 53 (21+22+23). with status register 6
Enter 9.

The output of the memory 30 is input to a memory data holding register 54, and the output of this register 54 is input to an interrupt signal generation circuit 66, as well as a change detection circuit 62 and a line timer circuit 65. The outputs of the change detection circuit 62 and the line timer circuit 65 are respectively connected to a 2-1 selection circuit 56.
Enter. The output of the 2-1 selection circuit 56 and the activation signal 55 from the processor 1 are input to the memory 30. One output of the interrupt signal generation circuit 66 is an interrupt signal 67 to the processor 1, and the other output is input to the status register 69 which issues a status register signal 70 to the processor 1 via a status register set signal 68. do. Next, the functions of each block in the circuit shown in FIG. 5 will be explained. Drawing code 51
is an address counter corresponding to the format diagram shown in FIG. 3, and the address shown in this counter specifies what processing should be performed.

The reference numeral 30 in the drawing is a memory shown in FIG. 4, which temporarily stores information for time division multiplex processing, and "2 ⁰ " of the address counter 51 shown in the drawing numeral 53.
The memory area is selected by ~ ²⁵ bits (21+22+23). Drawing code 54 is the beginning of each process,
This is a register that holds the contents of the memory stored one cycle ago. The reference numeral 55 in the drawing is a line for information writing and start signal from the processor 1, and the reference numeral 56 is a 2-1 selection circuit for selecting a line timer circuit or a change detection circuit, which is a line for the address counter 51 indicated by the reference numeral 22 in the drawing. Indicated by the ``2 ² '' bit.

Reference numeral 58 in the figure is a 4-1 selection circuit that selects the reception control signal for line ^number 0 and line number 7, and 59 is a 4-1 selection circuit that selects the reception control signal for line number ⁷ . selected. The reference numeral 60 in the drawing is an 8-1 selection circuit for selecting a line, and the address counter 5 indicated by the reference numeral 21 in the drawing
It is selected by the ``2 <sup>3</sup> '', ``2 ⁴ '', and ``2 ⁵ '' bits of 1. The drawing code 62 is a change detection circuit, and the drawing code 63 is a change detection circuit.
This circuit compares the information one cycle before with the current information 64 and detects a change in the information. Reference number 65 in the drawing is a line timer circuit, which inputs "+" to information from one cycle before.
This is a circuit that performs addition of 1. Reference numeral 66 in the drawing designates an interrupt signal generation circuit, which generates an interrupt signal 67 based on the change detection or specified time arrival signal detected by the change detection circuit 62 and line timer circuit 65 and stored in the memory 30, and outputs the interrupt signal 67 to the processor 1 (CPU).
It also generates a status register set signal 68 that sets bits ²⁰ to ²⁵ of the address counter 51 in the status register 69 indicating what kind of interrupt it is. Reference numeral 70 in the figure is an interrupt status register signal to the processor 1.

The operation of the device of the present invention is shown. The processor 1 uses the signal line 55 to activate the specified memory address. In the case of a line timer, start it and set the time value at the same time. When the address counter 51 reaches the value of this specified address, the contents of this memory are held in the memory data holding register 54, and in the case of change detection, the change detection circuit 62 detects the state from the holding memory one cycle ago. , the current state of the current received control signal 64 from the 8-1 selection circuit is compared, and in the case of a line timer, +1 is added to the timer value in the line timer circuit 65, and the result is selected by the 2-1 selection circuit 56. It is stored in the memory 30. By repeating the above operations, the change detection signal or line timer specified time arrival signal is stored in the memory 30, and when detected by the interrupt signal generation circuit 66, an interrupt signal 67 from the interrupt signal generation circuit 66 is sent to the processor 1. The processor 1 receives this interrupt, receives the contents of the status register 69 from the status register signal 70, and can know what type of interrupt it is.

〔Effect of the invention〕

The time-division multiplex common control circuit of the present invention described above is a time-division multiplex common control circuit that can implement multiple line timers and multiple reception control signal change detection circuits in a line control unit of a communication control device accommodating multiple lines with a small amount of hardware. Added by a circuit using multiple common control method,
By delegating processing that was conventionally performed by software, it has the effect of improving processing capacity and making it possible to accommodate high-speed lines and a large number of communication lines.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional communication control device. FIG. 2 is a block diagram of a communication control device according to an embodiment of the present invention. FIG. 3 is an address counter signal format diagram according to an embodiment of the present invention. FIG. 4 is an area layout diagram of a memory portion according to an embodiment of the present invention. FIG. 5 is a detailed diagram of a block configuration of an apparatus according to an embodiment of the present invention. 1...Processor, 2...Common control bus, 3...
...Line control circuit, 4...Data terminal (DTE)-data control equipment (DCE) interface, 5...
...Modem, 6...Data terminal device, 10...Time division multiplexing common control circuit, 11...Reception control signal, 1
2...DTE-DCE interface other than reception control signals, 21...Address counter "2 ³ ",
"2 ⁴ ", "2 ⁵ " bits, 22... "2 ² " bits of the address counter, 23... "2 ⁰ ", "2 ¹ " bits of the address counter, 30... memory, 39...
Memory area for line timer, 40...Memory area for change detection circuit, 51...Address counter, 53...Address counter "2 ⁰ " to "2 ⁵ "
Bit (21+22+23), 54...Memory data holding register, 56...2-1 selection circuit, 58-
59...4-1 selection circuit, 60...8 for line control
-1 selection circuit, 62... Change detection circuit, 63...
One cycle previous data from retention memory, 65...
Line timer circuit, 66... interrupt signal generation circuit,
67...Interrupt signal, 68...Status register set signal, 69...Status register.

Claims (1)

[Scope of Claims] 1. A plurality of line control circuits provided for each communication line and controlling modems of the respective communication lines, and a plurality of line control circuits connected to the plurality of line control circuits by a common control bus to commonly control the line control circuits. a change detection circuit coupled to the processor and each of the modems and configured to detect changes in received control signals sent from each of the modems by time-sharing processing; A time division multiplex control circuit including a line timer circuit that measures the elapsed generation time of the signal sent out from each modem is provided, and the change detection circuit is activated by the processor and then assigned to the processor when a change is detected. 1. A communication line control device comprising: means for transmitting an interrupt signal; and wherein the line timer circuit includes means for transmitting an interrupt signal to the processor when the time set by the processor is counted.