JPH026237B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to an improvement in a semiconductor device in which a normal semiconductor element and an optical semiconductor element coexist on the same substrate.

BACKGROUND ART Conventionally, the one shown in FIG. 1 is known as a semiconductor device in which, for example, a logic field effect semiconductor element and an optical semiconductor element are formed on the same substrate.

In the figure, 1 is a semi-insulating GaAs substrate, 2 is an n
type GaAs active layer, 3 is n-type GaAs layer, 4 is n-type
GaAlAs clad layer, 5 is n-type GaAs active layer, 6
is a p-type GaAlAs cladding layer, 7 is a p ⁺ type GaAs cap layer, 8 is a p-side electrode made of AuZn, and 9 is a p-side electrode made of AuZn.
A drain electrode made of AuGe, 10 a gate electrode made of Al, and 11 a source electrode made of AuGe. Note that QT indicates a field effect transistor portion and QL indicates a semiconductor laser portion.

When a voltage is applied to this device with the polarity shown, a current flows as indicated by arrow I. Since this current is controlled by the expansion of the depletion layer generated by the negative voltage applied to the gate electrode 10, the light emitted from the semiconductor laser portion QL can be modulated using the negative voltage as a signal.

By the way, in this conventional example, since the step between the field effect transistor part QT and the semiconductor laser part QL is large (for example, 3 to 5 [μm]), the photolithography of the electrodes of the field effect transistor, especially the gate electrode, is difficult. This makes microfabrication difficult, and since the current flows through the active layer 2, which has a low carrier concentration, as a wiring, the wiring resistance is high.

Therefore, a device having the structure shown in FIG. 2 has also been proposed.

In the figure, 21 is an n-type GaAs substrate, 22 is an n-type GaAs substrate, and 22 is an n-type GaAs substrate.
23 is an n-type GaAlAs active layer, 24 is a p-type GaAlAs clad layer, 25 is an n-type
GaAs layer, 26 is semi-insulating GaAlAs layer, 27 is n
type GaAs active layer, 28 is a silicon dioxide insulating film,
29 is a p-type impurity diffusion region, 30 is a p-side electrode made of AuCr, 31 is a drain electrode made of AuGeNi, 32 is a gate electrode made of AuCr, and 33 is a p-side electrode made of AuCr.
A source electrode made of AuGeNi, 34 an n-side electrode made of AuGeNi, QT a field effect transistor part, and QL a semiconductor laser part.

In this device, when a voltage is applied to the illustrated polarity, a current shown by arrow I ₁ flows, which passes through the source electrode 33 and the p-side electrode 30 and flows as shown by arrow I ₂ . This current is also controlled by how the depletion layer generated in the active layer 27 spreads due to the negative voltage applied to the gate electrode 32. Therefore, as described above, the emitted light of the semiconductor laser portion QL can be modulated.

According to this conventional example, although the step difference between the semiconductor laser portion QL and the field effect transistor portion QT is eliminated and the wiring resistance is not a problem, another drawback occurs. That is, in this device,
Since the semi-insulating GaAlAs layer 26 is formed by epitaxial growth, its specific resistance ρ is usually ~10 ^{3 ~ 4}
It is about [Ω-cm] and cannot be made too high.
Therefore, the current indicated by the arrow _I1 flows as indicated by the broken line arrow, and the semiconductor laser portion QL does not operate normally. Incidentally, the specific resistance ρ in the semi-insulating GaAs substrate 1 shown in Figure 1 is
10 ^{6 to 7} [Ωcm] can be obtained.

Purpose of the Invention The present invention provides a structure in which a normal semiconductor element and an optical semiconductor element such as a semiconductor laser or an LED are arranged side by side on a high resistivity semi-insulating substrate so that there is no difference in level between the semiconductor element and the optical semiconductor element. This makes it possible to suppress the resistance of the wiring connecting the device to a low level.

Embodiment of the Invention FIGS. 3 to 7 are cross-sectional views of essential parts of a semiconductor device at key points in the process for explaining the manufacturing process of an embodiment of the present invention. I will explain while referring to it.

Refer to Figure 3 (1) On the semi-insulating GaAs substrate 31, the thickness is ~6000 [Å].
A silicon dioxide film 51 is formed by, for example, a CVD method.

(2) The silicon dioxide film 51 is patterned using ordinary photolithography technology to selectively form windows.

(3) Using the patterned silicon dioxide film 51 as a mask, the substrate 31 is etched to a depth of about 7 to 8 [μm].

See FIG. 4 (4) The silicon dioxide film 51 is patterned again to slightly enlarge the previously formed window.

(5) Using the silicon dioxide film 51 as a mask, Zn is diffused into the substrate 31 to a depth of ~50 [μm] p ⁺
(p>10 ²⁰ [cm ^-3 ]) type wiring layer 32 is formed.

Refer to Figure 5 (6) After removing the silicon dioxide film 51, an n-type layer, which is an active layer in a normal semiconductor device, is formed by molecular beam epitaxial growth (MBE).
The GaAs layer 33 is grown to a thickness of, for example, about 0.2 [μm]. The temperature at this time is 600 to 700 [° C.], the time is 1 to 3 [hours], and the concentration of n-type impurity is 1×10 ¹⁷ [cm ⁻³ ].

During this step, the n ^- type
P-type impurities creep into the GaAs layer 33 and convert n-type to p-type. In addition, the temperature is 600 [℃] and 1
The creeping diffusion depth in time is ~0.5 [μm]
That's about it.

(7) A silicon dioxide film 52 is formed by the CVD method, and this is patterned by lithography to cover the thick portions of the substrate 31, the stepped portions, and the substrate 3.
1. Leave the part that covers part of the thinned part of 1 and remove the others.

(8) Apply the MBE method again to grow the p ⁺ type GaAs layer 34, which is the p-side contact layer of the semiconductor laser, to a thickness of, for example, about 2 to 3 [μm]. In addition, p
The type impurity concentration is about 5×10 ¹⁸ [cm ⁻³ ].

Next, the p-type carrier confinement layer
The GaAlAs layer 35 is grown to a thickness of, for example, about 1 [μm]. In addition, the p-type impurity concentration is 1×10 ¹⁷
It is about [cm ^-3 ].

Subsequently, an n-type GaAs layer 36 as an active layer is formed to a thickness of, for example, 0.2 [μm]. Note that the n-type impurity concentration is about 1×10 ¹⁷ [cm ⁻³ ].

Next is the n-type carrier confinement layer.
The GaAlAs layer 37 is formed to have a thickness of, for example, about 1 [μm]. In addition, the n-type impurity concentration is 1×10 ¹⁷ [cm
^-3 ].

Subsequently, an n ⁺ type GaAs layer 38 serving as an n-side contact layer is formed to a thickness of, for example, about 1 [μm].
Note that the n-type impurity concentration is approximately 1×10 ¹⁸ [cm ⁻³ ].

This growth is continuous. Each layer grown on the silicon dioxide film 52 becomes polycrystalline. In the figure, this is indicated by the symbol 39.

See Figure 6 (9) AuGe/Ni for the n-side electrode of optical semiconductor devices.
is formed to a thickness of approximately 3000 Å by vacuum evaporation.

(10) Using normal photolithography technology, n ⁺
A layer with a width of 10 [μm] and a length of 300 [μm] is formed on the type GaAs layer 38.
m] stripe electrodes 40 are formed, and then
Heat treatment is performed at a temperature of 420 [° C.] and a time of 1 [minute] in a nitrogen atmosphere.

(11) Width 250 [μ] so as to cover the stripe electrode 40
m], a mask with a length of 310 [μm] is formed using a photoresist film (not shown), and each of the previously formed semiconductor layers is etched to form a p ⁺ type GaAs layer 34.
Continue until exposed. At this time, a mixed solution of H ₂ SO ₄ /H ₂ O ₂ /H ₂ O (1/8/1) can be used as the etching solution. Incidentally, since the etching rate of the polycrystalline layer on the silicon dioxide film 52 is twice as fast as that of the single crystal layer,
It is completely removed in the etching process. Furthermore, control to stop the etching at the p ⁺ type GaAs layer 34 is performed depending on the etching rate and time, but if the p ⁺ type GaAs layer 34 is formed thickly, even if the etching is slightly over-etched, No problems arise.

See Figure 7 (12) After removing the silicon dioxide film 52, a AuZn film is deposited to a thickness of, for example, ~3000 [Å] by vacuum evaporation.
The contact layer 41 is formed by patterning the contact layer 41 and removing it except for those on the p ⁺ type wiring layer 32 located in the thick part of the substrate 31.
Next, heat treatment is performed at a temperature of 450 [° C.] for a time of 5 [minutes] in a nitrogen atmosphere.

(13) AuGe/Ni is deposited by vacuum evaporation method to a thickness of e.g.
It is formed to a thickness of about 3000 [Å] and patterned to form a drain electrode 42 and a source electrode 43. Next, heat treatment is performed at a temperature of 420 [° C.] for a time of 1 [minute] in a nitrogen atmosphere.

(14) Deposit Al to a thickness of e.g. ~2000 Å using vacuum evaporation method.
The gate electrode 44 is formed by patterning the gate electrode 44.

In this way, the field effect transistor portion QT is formed in the thick portion (mesa-shaped portion) of the substrate 31, and the semiconductor laser portion QL is formed in the thin portion (recess).

In the above embodiment, the transistor part QT and the laser part QL are formed by diffusing Zn at a high concentration ^.
Although electrically connected by the type wiring layer 32,
Alternatively, a single crystal layer with high impurity concentration, e.g.
A p ⁺ (or n ⁺ ) type GaAs layer may also be used. n ⁺ type
When using a GaAs layer, the semiconductor laser part
It is sufficient to invert the conductivity type of each layer in the QL and change the electrode material used to form the resistive contact. Incidentally, the resonator end face in the laser may be formed in the step (11) described above, but it is also possible to use conventional cleavage.

Effects of the Invention As can be seen from the above explanation, according to the present invention, since a semi-insulating single crystal substrate with high resistivity is used, there is a risk that the current flowing between the semiconductor element and the optical semiconductor element may be bypassed. In addition, since the current flows through a wiring layer made of a low resistance diffusion layer or a single crystal layer, it is easy to extract a large output.Furthermore, since there are multiple layers, the length is inevitably increased. The height of the optical semiconductor element is formed on the surface below the step formed by etching the substrate, and the normal semiconductor element is formed on the unetched surface of the substrate, that is, the surface above the step. have substantially the same height, making it easier to form fine patterns when performing lithography.

[Brief explanation of drawings]

Figures 1 and 2 are sectional views of the main parts of the conventional example;
7 to 7 are sectional views of essential parts of a semiconductor device at key points in the process for explaining the process of manufacturing an embodiment of the present invention. In the figure, 31 is a semi-insulating material with steps.
32 is a p ⁺ type wiring layer, 33 is an n type GaAs layer which is an active layer, 34 is a p ⁺ type GaAs layer which is a p side contact layer, 35 is a p type GaAlAs layer which is a carrier confinement layer, and 36 is a GaAs substrate. n-type active layer
GaAs layer, 37 is n-type carrier confinement layer
GaAlAs layer, 38 is n ⁺ type which is n side contact layer
40 is a stripe electrode, 41 is a contact layer, 42 is a drain electrode, 43 is a source electrode, and 44 is a gate electrode.

Claims (1)

[Claims] 1. A semi-insulating single-crystal substrate having a step on its surface, comprising a diffusion layer or a single-crystal layer with a high impurity concentration formed between the upper surface and the lower surface of the step in the substrate. a wiring layer; a normal semiconductor element formed on the upper surface of the step; a wiring layer laminated on the lower surface of the step; A semiconductor device comprising an optical semiconductor element electrically coupled to the ordinary semiconductor element.