JPH026261B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a synchronous data transmission system using a split-phase code as a transmission code.

(Prior art) A split-phase code has different signal levels in the first half and the second half of the "1" and "0" codes, respectively.As shown in Figure 1, the first half of the code
The signal with the high level and the second half of the code as the low level is "1", the first half is the low level, and the second half is the low level.
The signal set to High level is set to "0". In Figure 1, “1” is High level and “0” is High level.
An NRZ code with a low level is also shown, but in this split-phase code, the signal level in the first half of the code is the signal level in the NRZ code of "1" or "0" that the code represents.
In addition, for “1” as a split phase code,
A signal in which the first half is a low level and the second half is a high level is used, and a signal in which the first half is a high level and the second half is a low level may also be used for "0".

In decoding from a split-phase code to an NRZ code, if the delimitation of each code in the signal sequence of the split-phase code is incorrect, erroneous decoding will occur until the correct delimitation method is restored. Next, I will give an example.

FIG. 2 shows an example of a demodulation circuit from a split-phase code to an NRZ code. In the first half of the time chart in Figure 3, the split-phase code data input to the split-phase code input terminal 1 of the demodulation circuit in Figure 2 is input as a series of "0"s, and then the PLL of the demodulation circuit A time chart of each signal in the demodulation circuit is shown in a state where the oscillation frequency of circuit 2 has been determined. In Fig. 2, a D-type flip-flop (hereinafter abbreviated as D-FF) 3 functions as a demodulator, and the other parts generate a clock with twice the frequency of the code from input split-phase code data. This is the part that creates the clock that extracts it and divides it by 1/2 to demodulate the split-phase code to the NRZ code.

The operation of the demodulation circuit shown in FIG. 2 will be described first with reference to the time chart shown in FIG. 3 when the input data is continuous "0" or continuous "1". Split-phase code continuous “0” signal b input from split-phase code data input terminal 1
is input to the differentiating circuit 4, and the differentiating circuit 4 outputs a pulse signal indicating a polarity change point (hereinafter referred to as a polarity change point) which is a point of change of signal b from High level to Low level or from Low level to High level. It is extracted as an output signal c. In the PLL circuit 2 surrounded by the dotted line in FIG. 2, a clock with twice the frequency of the input signal f is obtained as the output a of the voltage controlled oscillator 2-3. The output a of this voltage controlled oscillator 2-3
Divide the frequency by 1/2 using D-FF2-4. This frequency-divided signal d is fed back to the phase comparator 2-1. In addition, by inputting the output a of the voltage controlled oscillator 2-3 to the inverter 5 and dividing the output by 1/2 by the D-FF 6, a signal e is obtained, and this signal e has a phase of 90° with respect to the signal d. The signal will be shifted. This signal e is used as a clock when demodulating the split phase code into the NRZ code. The output signal c of the differentiating circuit 4 is the feedback signal e, which is High.
You can pass through AND gate 7 only when the level is 3rd.
In the figure, every other pulse signal f, which is half of the pulse train of the output signal c of the differentiating circuit 4, is input to the phase comparator 2-1. This signal f is compared in phase with the signal d to be fed back by a phase comparator 2-1.

The output signal a of the voltage controlled oscillator 2-3 is D-FF
When dividing the frequency by 1/2 by 2-4, d ₁ and d ₂ in FIG. 3 can be generated as the output signal d of the D-FF 2-4. The demodulated clock signals e correspond to the signals d ₁ and d ₂ as e ₁ and e ₂ in FIG. 3, respectively. Since the input data signal b is "0" continuously, the pulse signal c indicating the polarity change point of the input split-phase code output from the differentiating circuit 4 is at the center of each code and at the boundary between codes. Since it is always output, if the demodulation clock is e ₁ , AND
The output of gate 7 becomes f ₁ , and when input to phase converter 2-1, f ₁ and d ₁ are aligned in phase, phase comparator 2-1 does not output an error output, and a, e ₁ , d PLL circuit 2 is stabilized with each signal of _{e 1} and f ₁ , and the demodulation clock is e ₁
Confirmed as Even when the demodulation clock is e ₂ ,
The output of AND gate 7 becomes f ₂ , and phase comparator 2
f ₂ and d ₂ inputted to -1 are in phase, phase comparator 2-1 does not output an error output, and a, e ₂ , d ₂ ,
The PLL circuit 2 is stabilized with each signal _f2 , and the demodulation clock is determined as _e2 . Demodulation clock e is D-FF
The split-phase code signal b is input to the clock input of D-FF3, and the split-phase code signal b is input to the D input of D-FF3.
is converted to NRZ code by latching at the rising edge of the clock. g ₁ and g ₂ in FIG. 3 are signals demodulated from input data corresponding to e ₁ and e ₂ , respectively. Since _e1 latches the first half of each symbol of input data signal b, it is the correct demodulation clock for this split-phase code. Since e ₂ latches the latter half of each symbol of input data signal b, the demodulated signal g ₂ becomes a series of "1s" different from the series of "0s" of input data signal b. That is, demodulation clock _e2 is a demodulation clock that is out of phase. In this way, when the input data is "0" continuously, both a correct demodulation clock and an erroneous demodulation clock can be determined. In a split-phase code, the polarity change point occurs at the center of the code and at the boundary between codes, not only in the case of continuous "0" but also in the case of continuous "1", so even in the case of continuous "1", Both true and false demodulation clocks have drawbacks that can be determined.

However, as shown on the right side of the time chart in Figure 3, when a signal in which the code "1" and the code "0" appear alternately as input data is output, the third
As shown on the right side of c in the figure, the polarity change point is only at the center of one code and not at the boundary between the code "1" and the code "0". Therefore, during the period when "1" and " ₀ " appear alternately, AND
A pulse signal indicating a polarity change point is not input from the gate to the phase comparator 2-1. Therefore, a phase error signal is output from the phase comparator 2-1, and the oscillation frequency of the output a of the voltage controlled oscillator 2-3 changes. By changing signal a, signal a is halved
The frequency-divided signal d ₂ and signal e ₂ also change. If "1" and "0" are input as data alternately after "1" continuous data is input, as shown in the time chart of each signal in Figure 2 shown in Figure 4, at the beginning. Among them, AND gate output signal f ₂
, the voltage controlled oscillator 2-3 is not output to the phase comparator 2-1.
Since only the signal obtained by dividing the output a by 1/2 is input, the voltage controlled oscillator 2-3 is used as the PLL circuit 2.
The frequency of the output a decreases. Therefore, the signal a
The frequency of the signals d ₂ and e ₂ , which are obtained by dividing the frequency by 1/2, also decreases, and the signal
The High level part of e ₂ is delayed. As this delaying process progresses, the pulse of signal c and the high level portion of signal e ₂ overlap in time, as shown in the central portion of f ₂ in FIG. A pulse indicating the polarity change point at the center of the sign of the input data of the signal c is now output as the output _f2 , and is input to the phase comparator 2-1. At this point, the phase comparator 2-1 obtains two signals that can be compared, and the PLL circuit 2 works so that the phase of the signal _d2 gradually aligns with the phase of the pulse train of the signal _f2 , thereby changing the sign of the input data. _The pulse train _of signal c, which indicates the polarity change point at the center of
As the phase of d ₂ approaches, the output signal f ₂ of the AND gate 7, which is a pulse train that finally indicates the inflection point at the center of the sign of the input data, and the output a of the voltage controlled oscillator 2-3 are divided by 1/2. The phase comparator _{2-1 does not output an error output, and the signals d 2} and d ₂ are in phase, and the phase comparator 2-1 does not output an error output.
The PLL circuit 2 is stabilized by the signals d ₂ and f ₂ , and the demodulation clock e ₂ is established, becoming a demodulation clock with the same correct phase as the demodulation clock e ₁ . Therefore, in order to determine the correct demodulation clock when the demodulation clock is incorrect during operation or when starting up the system, use the circuit in Figure 2 to determine the correct demodulation clock by using a signal that alternately repeats "1" and "0". If the necessary length is given as a data input signal, the correct demodulation clock can be naturally drawn in and determined by the original function of the circuit shown in FIG.

Now, in a synchronous data transmission system using a split-phase code as a transmission code, a frame consisting of a frame synchronization signal and data as shown in FIG. 6 is transmitted between a transmitting device and a receiving device as shown in FIG. communicate. In the transmitter 10 of FIG. 5, the counter 13 is operated by the transmission clock from the clock generation circuit 12, and every time one frame is counted, the counter 13 generates a transmission frame synchronization pulse from the frame synchronization signal generation circuit 14. At step 14, a frame synchronization signal is generated.
The NRZ code signal synchronized with the transmission clock from the transmission data input terminal 11 is sent to the frame generation circuit 1.
5, the signal is multiplexed with a frame synchronization signal to produce a signal having the frame structure shown in FIG. It is output to the output terminal 18.
On the other hand, in the receiving device 20, the split-phase code received signal from the transmitting device 10 inputted from the received signal input terminal 21 is amplified by the input circuit 22 and inputted to the demodulation clock extraction circuit 25 and the demodulator 23. A demodulation clock extraction circuit 25 extracts a demodulation clock necessary for demodulation from the output signal of the input circuit 22, and the demodulation clock is inputted to a demodulator 23, and the output signal of the input circuit 22 is converted from a split-phase code to an NRZ code. Ru. The signal converted into the NRZ code is input to the frame synchronization circuit 24, which detects a frame synchronization signal, synchronizes the frame, and outputs a received frame synchronization pulse. The counter 26 is reset by the received frame synchronization pulse from the frame synchronization circuit 24, and counts the demodulation clock from the demodulation clock extraction circuit 25.

In this synchronous data transmission system shown in Fig. 5,
The frame is sent out regardless of the presence or absence of sending data, and if there is no sending data, a series of "1"s occurs as data. Therefore, the receiving device 20
There is a possibility that an erroneous demodulation clock may be captured during system startup, or an erroneous demodulation clock may be captured due to an error during normal operation, and erroneous demodulation may be performed until the correct demodulation clock is established.

Conventionally, as a countermeasure for this, in order to determine the correct demodulation clock, the frame synchronization signal includes a repeating signal of "0" and "1" in an amount sufficient to determine the correct demodulation clock, or the data is As a result, a repeating signal of "0" and "1" was inserted.

In addition, FIG. 7 is a diagram showing a fifth-order reset type scrambler, and as shown in FIG.
The input data is randomized by inputting the pseudorandom signal from the pseudorandom signal generation circuit 30 to one input of the circuit 32 and inputting the input data from the input terminal 31 to the other input of the EX-OR circuit 32. , continuous "0" or continuous "1" data is facilitated in determining the correct demodulation clock at the receiving device, thereby preventing capture of an erroneous demodulation clock. However, these means have disadvantages such as a reduction in transmission efficiency and an increase in the number of circuits.

(Object of the Invention) In order to eliminate these drawbacks in a synchronous data transmission system, the present invention provides a low level signal for each code bit synchronized with a transmission frame for an input signal.
The present invention provides a data transmission system using a split-phase code that makes it easy to determine the correct demodulation clock on the receiving side with a simple configuration using a signal that repeatedly inverts the level and high level.

(Structure and operation of the invention) The present invention will be explained in detail below.

FIG. 8 shows an embodiment of the present invention, and is an example of a synchronous data transmission system. In contrast to the diagram of the conventional synchronous data transmission system shown in Figure 5, EX
-OR circuit 19 and EX-OR circuit 28 are added, and it is the same as the other one in FIG. In FIG. 8, j is the transmission clock output from the clock generation circuit 12, k is the least significant bit (LSB) output signal of the counter 13 that counts the transmission clock, and
High level for each input clock pulse,
There is a signal that alternately repeats low level, low level for odd numbered bits of the frame and low level for even numbered bits.
High level. l is transmission data input terminal 1
NRZ code transmission data signal synchronized with the transmission clock from 1, m is EX- with k and l as inputs.
Output signal of OR circuit 19, n is modulator 16
, p is the demodulation clock which is the output signal of the demodulation clock extraction circuit 25, and q is a high signal for each demodulation clock pulse input to the counter 26.
This is the LSB output of the counter 26 which alternately repeats high and low levels, and the odd-numbered bits of the frame are at the low level, and the even-numbered bits are at the high level. s is a signal obtained by demodulating the split phase code obtained from the output of the input circuit 22 into an NRZ code by the demodulator 23, and t is the signal EX- to which q and s are input.
This is the output signal of the OR circuit 28.

In FIG. 9, the above j, k, l, m, n, p, q,
A time chart of s and t is shown. In a synchronous data transmission system, a frame consisting of a frame synchronization signal and data as shown in FIG. 6 is constructed and transmitted. In the synchronous data transmission system shown in FIG. 8, in the transmitting device 10, the counter 13 is operated by the transmission clock from the clock generation circuit 12, and the transmission clock is counted for one frame. The frame synchronization pulse is generated by the frame synchronization signal generation circuit 14.
The frame synchronization signal generation circuit 14 generates a frame synchronization signal. The signal l of the NRZ code synchronized with the transmission clock from the transmission data input terminal 11 is sent to a counter 13 which alternately repeats low level and high level, such as low level for odd numbered bits of the frame and high level for even numbered bits, for every code bit. along with the LSB output signal k of EX−
By being input to the inputs of the OR circuit 19, the signals are scrambled, and the output of the EX-OR circuit 19 becomes a signal in which every other bit is inverted, with even-numbered bits being inverted. The output signal m of this EX-OR circuit is multiplexed with the frame synchronization signal in the frame generation circuit 15, and an NRZ code signal having the frame structure shown in FIG. 6 is generated. This signal is exchanged from the NRZ code to a split phase code by the modulator 16, driven by the output circuit 17, and output from the transmission signal output terminal 18.

On the other hand, in the receiving device 20, the received signal input terminal 21
The split-phase code received signal from the transmitter 10 is received and amplified by the input circuit 22, and is input to the demodulation clock extraction circuit 25 and the demodulator 23. Demodulation clock extraction circuit 25
A demodulation clock p necessary for demodulation is extracted from the output signal of the input circuit 22, and the output signal of the input circuit 22 is converted from the split phase code by the demodulation clock p in the demodulator 23.
Exchanged to NRZ code. The signal s converted into NRZ code is input to a frame synchronization circuit 24, which detects a frame synchronization signal, synchronizes the frame, and outputs a received frame synchronization pulse. Further, the counter 26 is reset by the received frame synchronization pulse from the frame synchronization circuit 24, and counts the demodulation clock from the demodulation clock extraction circuit 25. Also, the demodulated
The NRZ code signal s is sent to a synchronized counter 26.
For each demodulated clock input to the EX-
By inputting the signal to the input of the OR circuit 28, the signal is descrambled. In this way, EX
A signal obtained by inverting every other bit of the signal s demodulated by the demodulator 23 is obtained as the output signal f of the -OR circuit 28.

By the above-mentioned scrambling on the transmitting side and descrambling on the receiving side, the received data output terminal 2
7, the original signal l before being scrambled by the EX-OR circuit 19 in the transmitter 10 can be obtained.

As explained above, the transmission data signal l input to the transmitting device 10 is scrambled by the EX-OR circuit 19 and the sign is inverted for every other bit, so that if there is no data to be transmitted, continuous "0" etc. Preventing the sending of consecutive “0”s and “1”s that are harmful to data demodulation in the receiving device 20,
Furthermore, when the system start-up data is "0" consecutively, a code repeating "0" and "1" can be transmitted to determine the correct demodulation clock in the receiving device 20.

Further, FIG. 10 shows an embodiment in which the embodiment shown in FIG. 8 is partially modified. In the embodiment of FIG.
The signal scrambled by the EX-OR circuit 19 in the transmitter 10 is sent to the transmit signal input terminal 11.
In the embodiment of FIG. 10, the signal l from
The signal l from the transmission data input terminal 11 is directly sent to the frame generation circuit 15 without being scrambled.
Then, the output signal of the frame generation circuit 15 is EX-ORed with the output signal k of the counter 13.
The circuit 19 scrambles the signal, the output is input to the modulator 16, and the frame synchronization circuit 24 of the receiver 20 scrambles the frame synchronization signal output by the frame synchronization signal generation circuit 14 of the transmitter 10. is modified so that it is treated as a frame synchronization signal.
Even in this case, the only difference from the case shown in FIG. 8 is that the transmitter 10 scrambles the signal including the frame synchronization signal.
The same effect as the embodiment shown in FIG. 8 can be obtained.

(Effects of the Invention) As described above, according to the present invention, an input signal is scrambled using an output signal that is inverted for each symbol synchronized with a transmission frame, and " It is possible to prevent continuous 0's and 1's, and by converting continuous 0's at system start-up into repeated data of 0's and 1's, correct demodulation can be achieved on the receiving side. The clock can be fixed,
Moreover, it is economical because the circuit is simple and can be realized.

[Brief explanation of drawings]

Figure 1 is a time chart to explain the NRZ code and split phase code, and Figure 2 is a time chart to explain the NRZ code and split-phase code.
A block diagram showing a conventional split-phase code demodulation circuit using a PLL circuit, Figures 3 and 4 are time charts showing each signal in Figure 2, and Figure 5 shows a conventional synchronous data transmission system. A block diagram showing an example, FIG. 6 a time chart showing a transmission frame, FIG. 7 a block diagram showing an example of a conventional fifth-order reset type scrambler, and FIG. 8 a synchronous type scrambler which is an embodiment of the present invention. FIG. 9 is a block diagram of the data transmission system, FIG. 9 is a time chart showing each signal in FIG. 8, and FIG. 10 is a block diagram showing another embodiment of the present invention.

Claims (1)

[Scope of Claims] 1. A clock generation circuit that generates a transmission clock, a counter that outputs a transmission frame synchronization pulse every time the transmission clock is counted for one frame, and a transmission NRZ code data signal synchronized with the transmission clock. an exclusive OR circuit that calculates an exclusive OR with the least significant bit output signal of the counter and outputs an exclusive OR signal; a frame synchronization signal generation circuit that generates a frame synchronization signal using the transmission frame synchronization pulse; a frame generation circuit that generates a transmission NRZ frame signal using the exclusive OR signal and the frame synchronization signal, a modulator that converts the transmission NRZ frame signal into a transmission split-phase signal, and a transmission output according to the transmission split-phase signal. A data transmission method that uses a split-phase code that is equipped with an output circuit that outputs a signal. 2. A clock generation circuit that generates a transmission clock, a counter that outputs a transmission frame synchronization pulse every time the transmission clock is counted for one frame, and a frame synchronization signal generation circuit that generates a frame synchronization signal using the transmission frame synchronization pulse. , transmitted using a transmit NRZ code data signal synchronized with the transmit clock and the frame synchronization signal.
a frame generation circuit that generates an NRZ frame signal; an exclusive OR circuit that calculates an exclusive OR of the transmitted NRZ frame signal and the least significant bit output signal of the counter and outputs an exclusive OR signal; A data transmission system using a split-phase code, which includes a modulator that converts a logical OR signal into a transmission split-phase signal, and an output circuit that outputs a transmission output signal based on the transmission split-phase signal.